PPC.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This is the top level entry point for the PowerPC target. 11// 12//===----------------------------------------------------------------------===// 13 14// Get the target-independent interfaces which we are implementing. 15// 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// PowerPC Subtarget features. 20// 21 22//===----------------------------------------------------------------------===// 23// CPU Directives // 24//===----------------------------------------------------------------------===// 25 26def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">; 27def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">; 28def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">; 29def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 30def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 31def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 32def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">; 33def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">; 34def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">; 35def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">; 36def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">; 37def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">; 38def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective", 39 "PPC::DIR_E500mc", "">; 40def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective", 41 "PPC::DIR_E5500", "">; 42def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">; 43def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">; 44def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">; 45def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">; 46def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">; 47def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">; 48def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">; 49 50def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 51 "Enable 64-bit instructions">; 52def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 53 "Enable 64-bit registers usage for ppc32 [beta]">; 54def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 55 "Use condition-register bits individually">; 56def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 57 "Enable Altivec instructions">; 58def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 59 "Enable the MFOCRF instruction">; 60def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 61 "Enable the fsqrt instruction">; 62def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 63 "Enable the fcpsgn instruction">; 64def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 65 "Enable the fre instruction">; 66def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 67 "Enable the fres instruction">; 68def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 69 "Enable the frsqrte instruction">; 70def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 71 "Enable the frsqrtes instruction">; 72def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 73 "Assume higher precision reciprocal estimates">; 74def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 75 "Enable the stfiwx instruction">; 76def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 77 "Enable the lfiwax instruction">; 78def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 79 "Enable the fri[mnpz] instructions">; 80def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 81 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">; 82def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 83 "Enable the isel instruction">; 84def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true", 85 "Enable the popcnt[dw] instructions">; 86def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 87 "Enable the ldbrx instruction">; 88def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 89 "Enable Book E instructions">; 90def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", 91 "Enable QPX instructions">; 92def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 93 "Enable VSX instructions", 94 [FeatureAltivec]>; 95 96def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true", 97 "Treat mftb as deprecated">; 98def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 99 "Treat vector data stream cache control instructions as deprecated">; 100 101// Note: Future features to add when support is extended to more 102// recent ISA levels: 103// 104// CMPB p6, p6x, p7 cmpb 105// DFP p6, p6x, p7 decimal floating-point instructions 106// POPCNTB p5 through p7 popcntb and related instructions 107// VSX p7 vector-scalar instruction set 108 109//===----------------------------------------------------------------------===// 110// Classes used for relation maps. 111//===----------------------------------------------------------------------===// 112// RecFormRel - Filter class used to relate non-record-form instructions with 113// their record-form variants. 114class RecFormRel; 115 116// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 117// FMA instruction forms with their corresponding factor-killing forms. 118class AltVSXFMARel { 119 bit IsVSXFMAAlt = 0; 120} 121 122//===----------------------------------------------------------------------===// 123// Relation Map Definitions. 124//===----------------------------------------------------------------------===// 125 126def getRecordFormOpcode : InstrMapping { 127 let FilterClass = "RecFormRel"; 128 // Instructions with the same BaseName and Interpretation64Bit values 129 // form a row. 130 let RowFields = ["BaseName", "Interpretation64Bit"]; 131 // Instructions with the same RC value form a column. 132 let ColFields = ["RC"]; 133 // The key column are the non-record-form instructions. 134 let KeyCol = ["0"]; 135 // Value columns RC=1 136 let ValueCols = [["1"]]; 137} 138 139def getNonRecordFormOpcode : InstrMapping { 140 let FilterClass = "RecFormRel"; 141 // Instructions with the same BaseName and Interpretation64Bit values 142 // form a row. 143 let RowFields = ["BaseName", "Interpretation64Bit"]; 144 // Instructions with the same RC value form a column. 145 let ColFields = ["RC"]; 146 // The key column are the record-form instructions. 147 let KeyCol = ["1"]; 148 // Value columns are RC=0 149 let ValueCols = [["0"]]; 150} 151 152def getAltVSXFMAOpcode : InstrMapping { 153 let FilterClass = "AltVSXFMARel"; 154 // Instructions with the same BaseName and Interpretation64Bit values 155 // form a row. 156 let RowFields = ["BaseName"]; 157 // Instructions with the same RC value form a column. 158 let ColFields = ["IsVSXFMAAlt"]; 159 // The key column are the (default) addend-killing instructions. 160 let KeyCol = ["0"]; 161 // Value columns IsVSXFMAAlt=1 162 let ValueCols = [["1"]]; 163} 164 165//===----------------------------------------------------------------------===// 166// Register File Description 167//===----------------------------------------------------------------------===// 168 169include "PPCRegisterInfo.td" 170include "PPCSchedule.td" 171include "PPCInstrInfo.td" 172 173//===----------------------------------------------------------------------===// 174// PowerPC processors supported. 175// 176 177def : Processor<"generic", G3Itineraries, [Directive32]>; 178def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 179 FeatureFRES, FeatureFRSQRTE, 180 FeatureBookE, DeprecatedMFTB]>; 181def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 182 FeatureFRES, FeatureFRSQRTE, 183 FeatureBookE, DeprecatedMFTB]>; 184def : Processor<"601", G3Itineraries, [Directive601]>; 185def : Processor<"602", G3Itineraries, [Directive602]>; 186def : Processor<"603", G3Itineraries, [Directive603, 187 FeatureFRES, FeatureFRSQRTE]>; 188def : Processor<"603e", G3Itineraries, [Directive603, 189 FeatureFRES, FeatureFRSQRTE]>; 190def : Processor<"603ev", G3Itineraries, [Directive603, 191 FeatureFRES, FeatureFRSQRTE]>; 192def : Processor<"604", G3Itineraries, [Directive604, 193 FeatureFRES, FeatureFRSQRTE]>; 194def : Processor<"604e", G3Itineraries, [Directive604, 195 FeatureFRES, FeatureFRSQRTE]>; 196def : Processor<"620", G3Itineraries, [Directive620, 197 FeatureFRES, FeatureFRSQRTE]>; 198def : Processor<"750", G4Itineraries, [Directive750, 199 FeatureFRES, FeatureFRSQRTE]>; 200def : Processor<"g3", G3Itineraries, [Directive750, 201 FeatureFRES, FeatureFRSQRTE]>; 202def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 203 FeatureFRES, FeatureFRSQRTE]>; 204def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 205 FeatureFRES, FeatureFRSQRTE]>; 206def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 207 FeatureFRES, FeatureFRSQRTE]>; 208def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 209 FeatureFRES, FeatureFRSQRTE]>; 210def : ProcessorModel<"970", G5Model, 211 [Directive970, FeatureAltivec, 212 FeatureMFOCRF, FeatureFSqrt, 213 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 214 Feature64Bit /*, Feature64BitRegs */]>; 215def : ProcessorModel<"g5", G5Model, 216 [Directive970, FeatureAltivec, 217 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 218 FeatureFRES, FeatureFRSQRTE, 219 Feature64Bit /*, Feature64BitRegs */, 220 DeprecatedMFTB, DeprecatedDST]>; 221def : ProcessorModel<"e500mc", PPCE500mcModel, 222 [DirectiveE500mc, FeatureMFOCRF, 223 FeatureSTFIWX, FeatureBookE, FeatureISEL, 224 DeprecatedMFTB]>; 225def : ProcessorModel<"e5500", PPCE5500Model, 226 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 227 FeatureSTFIWX, FeatureBookE, FeatureISEL, 228 DeprecatedMFTB]>; 229def : ProcessorModel<"a2", PPCA2Model, 230 [DirectiveA2, FeatureBookE, FeatureMFOCRF, 231 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 232 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 233 FeatureSTFIWX, FeatureLFIWAX, 234 FeatureFPRND, FeatureFPCVT, FeatureISEL, 235 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit 236 /*, Feature64BitRegs */, DeprecatedMFTB]>; 237def : ProcessorModel<"a2q", PPCA2Model, 238 [DirectiveA2, FeatureBookE, FeatureMFOCRF, 239 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 240 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 241 FeatureSTFIWX, FeatureLFIWAX, 242 FeatureFPRND, FeatureFPCVT, FeatureISEL, 243 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit 244 /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>; 245def : ProcessorModel<"pwr3", G5Model, 246 [DirectivePwr3, FeatureAltivec, 247 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 248 FeatureSTFIWX, Feature64Bit]>; 249def : ProcessorModel<"pwr4", G5Model, 250 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 251 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 252 FeatureSTFIWX, Feature64Bit]>; 253def : ProcessorModel<"pwr5", G5Model, 254 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 255 FeatureFSqrt, FeatureFRE, FeatureFRES, 256 FeatureFRSQRTE, FeatureFRSQRTES, 257 FeatureSTFIWX, Feature64Bit, 258 DeprecatedMFTB, DeprecatedDST]>; 259def : ProcessorModel<"pwr5x", G5Model, 260 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 261 FeatureFSqrt, FeatureFRE, FeatureFRES, 262 FeatureFRSQRTE, FeatureFRSQRTES, 263 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 264 DeprecatedMFTB, DeprecatedDST]>; 265def : ProcessorModel<"pwr6", G5Model, 266 [DirectivePwr6, FeatureAltivec, 267 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 268 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 269 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, 270 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 271 DeprecatedMFTB, DeprecatedDST]>; 272def : ProcessorModel<"pwr6x", G5Model, 273 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 274 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 275 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 276 FeatureSTFIWX, FeatureLFIWAX, 277 FeatureFPRND, Feature64Bit, 278 DeprecatedMFTB, DeprecatedDST]>; 279def : ProcessorModel<"pwr7", P7Model, 280 [DirectivePwr7, FeatureAltivec, 281 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 282 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 283 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, 284 FeatureFPRND, FeatureFPCVT, FeatureISEL, 285 FeaturePOPCNTD, FeatureLDBRX, 286 Feature64Bit /*, Feature64BitRegs */, 287 DeprecatedMFTB, DeprecatedDST]>; 288def : Processor<"ppc", G3Itineraries, [Directive32]>; 289def : ProcessorModel<"ppc64", G5Model, 290 [Directive64, FeatureAltivec, 291 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 292 FeatureFRSQRTE, FeatureSTFIWX, 293 Feature64Bit /*, Feature64BitRegs */]>; 294def : ProcessorModel<"ppc64le", G5Model, 295 [Directive64, FeatureAltivec, 296 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 297 FeatureFRSQRTE, FeatureSTFIWX, 298 Feature64Bit /*, Feature64BitRegs */]>; 299 300//===----------------------------------------------------------------------===// 301// Calling Conventions 302//===----------------------------------------------------------------------===// 303 304include "PPCCallingConv.td" 305 306def PPCInstrInfo : InstrInfo { 307 let isLittleEndianEncoding = 1; 308 309 // FIXME: Unset this when no longer needed! 310 let decodePositionallyEncodedOperands = 1; 311 312 let noNamedPositionallyEncodedOperands = 1; 313} 314 315def PPCAsmParser : AsmParser { 316 let ShouldEmitMatchRegisterName = 0; 317} 318 319def PPCAsmParserVariant : AsmParserVariant { 320 int Variant = 0; 321 322 // We do not use hard coded registers in asm strings. However, some 323 // InstAlias definitions use immediate literals. Set RegisterPrefix 324 // so that those are not misinterpreted as registers. 325 string RegisterPrefix = "%"; 326} 327 328def PPC : Target { 329 // Information about the instructions. 330 let InstructionSet = PPCInstrInfo; 331 332 let AssemblyParsers = [PPCAsmParser]; 333 let AssemblyParserVariants = [PPCAsmParserVariant]; 334} 335