PPC.td revision 5bb16fdbb363abee2b9495116ff1a97568460cae 
1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is the top level entry point for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing.
15//
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// PowerPC Subtarget features.
20//
21 
22//===----------------------------------------------------------------------===//
23// CPU Directives                                                             //
24//===----------------------------------------------------------------------===//
25
26def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39                                       "PPC::DIR_E500mc", "">;
40def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective", 
41                                       "PPC::DIR_E5500", "">;
42def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
43def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
44
45def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
46                                        "Enable 64-bit instructions">;
47def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
48                              "Enable 64-bit registers usage for ppc32 [beta]">;
49def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
50                                        "Enable Altivec instructions">;
51def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
52                                        "Enable the MFOCRF instruction">;
53def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
54                                        "Enable the fsqrt instruction">;
55def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
56                                        "Enable the stfiwx instruction">;
57def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
58                                        "Enable the isel instruction">;
59def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
60                                        "Enable Book E instructions">;
61def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
62                                        "Enable QPX instructions">;
63
64//===----------------------------------------------------------------------===//
65// Register File Description
66//===----------------------------------------------------------------------===//
67
68include "PPCRegisterInfo.td"
69include "PPCSchedule.td"
70include "PPCInstrInfo.td"
71
72//===----------------------------------------------------------------------===//
73// PowerPC processors supported.
74//
75
76def : Processor<"generic", G3Itineraries, [Directive32]>;
77def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
78                                           FeatureBookE]>;
79def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
80                                           FeatureBookE]>;
81def : Processor<"601", G3Itineraries, [Directive601]>;
82def : Processor<"602", G3Itineraries, [Directive602]>;
83def : Processor<"603", G3Itineraries, [Directive603]>;
84def : Processor<"603e", G3Itineraries, [Directive603]>;
85def : Processor<"603ev", G3Itineraries, [Directive603]>;
86def : Processor<"604", G3Itineraries, [Directive604]>;
87def : Processor<"604e", G3Itineraries, [Directive604]>;
88def : Processor<"620", G3Itineraries, [Directive620]>;
89def : Processor<"750", G4Itineraries, [Directive750]>;
90def : Processor<"g3", G3Itineraries, [Directive750]>;
91def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
92def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
93def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
94def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
95def : Processor<"970", G5Itineraries,
96                  [Directive970, FeatureAltivec,
97                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
98                   Feature64Bit /*, Feature64BitRegs */]>;
99def : Processor<"g5", G5Itineraries,
100                  [Directive970, FeatureAltivec,
101                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
102                   Feature64Bit /*, Feature64BitRegs */]>;
103def : ProcessorModel<"e500mc", PPCE500mcModel,
104                  [DirectiveE500mc, FeatureMFOCRF,
105                   FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
106def : ProcessorModel<"e5500", PPCE5500Model,
107                  [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
108                   FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
109def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
110                                         FeatureMFOCRF, FeatureFSqrt,
111                                         FeatureSTFIWX, FeatureISEL,
112                                         Feature64Bit
113                                     /*, Feature64BitRegs */]>;
114def : Processor<"a2q", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
115                                          FeatureMFOCRF, FeatureFSqrt,
116                                          FeatureSTFIWX, FeatureISEL,
117                                          Feature64Bit /*, Feature64BitRegs */,
118                                          FeatureQPX]>;
119def : Processor<"pwr6", G5Itineraries,
120                  [DirectivePwr6, FeatureAltivec,
121                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
122                   Feature64Bit /*, Feature64BitRegs */]>;
123def : Processor<"pwr7", G5Itineraries,
124                  [DirectivePwr7, FeatureAltivec,
125                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
126                   FeatureISEL, Feature64Bit /*, Feature64BitRegs */]>;
127def : Processor<"ppc", G3Itineraries, [Directive32]>;
128def : Processor<"ppc64", G5Itineraries,
129                  [Directive64, FeatureAltivec,
130                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
131                   Feature64Bit /*, Feature64BitRegs */]>;
132
133
134//===----------------------------------------------------------------------===//
135// Calling Conventions
136//===----------------------------------------------------------------------===//
137
138include "PPCCallingConv.td"
139
140def PPCInstrInfo : InstrInfo {
141  let isLittleEndianEncoding = 1;
142}
143
144def PPCAsmWriter : AsmWriter {
145  string AsmWriterClassName  = "InstPrinter";
146  bit isMCAsmWriter = 1;
147}
148
149def PPC : Target {
150  // Information about the instructions.
151  let InstructionSet = PPCInstrInfo;
152  
153  let AssemblyWriters = [PPCAsmWriter];
154}
155