PPC.td revision 827307b95fa909e35a3ddef612f9f50ffcf0963a 
1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is the top level entry point for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing.
15//
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// PowerPC Subtarget features.
20//
21 
22//===----------------------------------------------------------------------===//
23// CPU Directives                                                             //
24//===----------------------------------------------------------------------===//
25
26def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39                                       "PPC::DIR_E500mc", "">;
40def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective", 
41                                       "PPC::DIR_E5500", "">;
42def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
49
50def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
51                                        "Enable 64-bit instructions">;
52def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
53                              "Enable 64-bit registers usage for ppc32 [beta]">;
54def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
55                                        "Enable Altivec instructions">;
56def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
57                                        "Enable the MFOCRF instruction">;
58def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
59                                        "Enable the fsqrt instruction">;
60def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
61                                        "Enable the fre instruction">;
62def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
63                                        "Enable the fres instruction">;
64def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
65                                        "Enable the frsqrte instruction">;
66def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
67                                        "Enable the frsqrtes instruction">;
68def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
69                              "Assume higher precision reciprocal estimates">;
70def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
71                                        "Enable the stfiwx instruction">;
72def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
73                                        "Enable the lfiwax instruction">;
74def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
75                                        "Enable the fri[mnpz] instructions">;
76def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
77  "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
78def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
79                                        "Enable the isel instruction">;
80def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
81                                        "Enable the popcnt[dw] instructions">;
82def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
83                                        "Enable the ldbrx instruction">;
84def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
85                                        "Enable Book E instructions">;
86def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
87                                        "Enable QPX instructions">;
88
89// Note: Future features to add when support is extended to more
90// recent ISA levels:
91//
92// CMPB         p6, p6x, p7        cmpb
93// DFP          p6, p6x, p7        decimal floating-point instructions
94// FRE          p5 through p7      fre (vs. fres, available since p3)
95// FRSQRTES     p5 through p7      frsqrtes (vs. frsqrte, available since p3)
96// POPCNTB      p5 through p7      popcntb and related instructions
97// RECIP_PREC   p6, p6x, p7        higher precision reciprocal estimates
98// VSX          p7                 vector-scalar instruction set
99
100//===----------------------------------------------------------------------===//
101// Register File Description
102//===----------------------------------------------------------------------===//
103
104include "PPCRegisterInfo.td"
105include "PPCSchedule.td"
106include "PPCInstrInfo.td"
107
108//===----------------------------------------------------------------------===//
109// PowerPC processors supported.
110//
111
112def : Processor<"generic", G3Itineraries, [Directive32]>;
113def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
114                                           FeatureFRES, FeatureFRSQRTE,
115                                           FeatureBookE]>;
116def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
117                                           FeatureFRES, FeatureFRSQRTE,
118                                           FeatureBookE]>;
119def : Processor<"601", G3Itineraries, [Directive601]>;
120def : Processor<"602", G3Itineraries, [Directive602]>;
121def : Processor<"603", G3Itineraries, [Directive603,
122                                       FeatureFRES, FeatureFRSQRTE]>;
123def : Processor<"603e", G3Itineraries, [Directive603,
124                                        FeatureFRES, FeatureFRSQRTE]>;
125def : Processor<"603ev", G3Itineraries, [Directive603,
126                                         FeatureFRES, FeatureFRSQRTE]>;
127def : Processor<"604", G3Itineraries, [Directive604,
128                                       FeatureFRES, FeatureFRSQRTE]>;
129def : Processor<"604e", G3Itineraries, [Directive604,
130                                        FeatureFRES, FeatureFRSQRTE]>;
131def : Processor<"620", G3Itineraries, [Directive620,
132                                       FeatureFRES, FeatureFRSQRTE]>;
133def : Processor<"750", G4Itineraries, [Directive750,
134                                       FeatureFRES, FeatureFRSQRTE]>;
135def : Processor<"g3", G3Itineraries, [Directive750,
136                                      FeatureFRES, FeatureFRSQRTE]>;
137def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
138                                        FeatureFRES, FeatureFRSQRTE]>;
139def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
140                                      FeatureFRES, FeatureFRSQRTE]>;
141def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
142                                            FeatureFRES, FeatureFRSQRTE]>;
143def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
144                                           FeatureFRES, FeatureFRSQRTE]>;
145def : Processor<"970", G5Itineraries,
146                  [Directive970, FeatureAltivec,
147                   FeatureMFOCRF, FeatureFSqrt,
148                   FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
149                   Feature64Bit /*, Feature64BitRegs */]>;
150def : Processor<"g5", G5Itineraries,
151                  [Directive970, FeatureAltivec,
152                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
153                   FeatureFRES, FeatureFRSQRTE,
154                   Feature64Bit /*, Feature64BitRegs */]>;
155def : ProcessorModel<"e500mc", PPCE500mcModel,
156                  [DirectiveE500mc, FeatureMFOCRF,
157                   FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
158def : ProcessorModel<"e5500", PPCE5500Model,
159                  [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
160                   FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
161def : Processor<"a2", PPCA2Itineraries,
162                  [DirectiveA2, FeatureBookE, FeatureMFOCRF,
163                   FeatureFSqrt, FeatureFRE, FeatureFRES,
164                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
165                   FeatureSTFIWX, FeatureLFIWAX,
166                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
167                   FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
168               /*, Feature64BitRegs */]>;
169def : Processor<"a2q", PPCA2Itineraries,
170                  [DirectiveA2, FeatureBookE, FeatureMFOCRF,
171                   FeatureFSqrt, FeatureFRE, FeatureFRES,
172                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
173                   FeatureSTFIWX, FeatureLFIWAX,
174                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
175                   FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
176               /*, Feature64BitRegs */, FeatureQPX]>;
177def : Processor<"pwr3", G5Itineraries,
178                  [DirectivePwr3, FeatureAltivec,
179                   FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
180                   FeatureSTFIWX, Feature64Bit]>;
181def : Processor<"pwr4", G5Itineraries,
182                  [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
183                   FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
184                   FeatureSTFIWX, Feature64Bit]>;
185def : Processor<"pwr5", G5Itineraries,
186                  [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
187                   FeatureFSqrt, FeatureFRE, FeatureFRES,
188                   FeatureFRSQRTE, FeatureFRSQRTES,
189                   FeatureSTFIWX, Feature64Bit]>;
190def : Processor<"pwr5x", G5Itineraries,
191                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
192                   FeatureFSqrt, FeatureFRE, FeatureFRES,
193                   FeatureFRSQRTE, FeatureFRSQRTES,
194                   FeatureSTFIWX, FeatureFPRND, Feature64Bit]>;
195def : Processor<"pwr6", G5Itineraries,
196                  [DirectivePwr6, FeatureAltivec,
197                   FeatureMFOCRF, FeatureFSqrt, FeatureFRE,
198                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
199                   FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
200                   FeatureFPRND, Feature64Bit /*, Feature64BitRegs */]>;
201def : Processor<"pwr6x", G5Itineraries,
202                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
203                   FeatureFSqrt, FeatureFRE, FeatureFRES,
204                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
205                   FeatureSTFIWX, FeatureLFIWAX,
206                   FeatureFPRND, Feature64Bit]>;
207def : Processor<"pwr7", G5Itineraries,
208                  [DirectivePwr7, FeatureAltivec,
209                   FeatureMFOCRF, FeatureFSqrt, FeatureFRE,
210                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
211                   FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
212                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
213                   FeaturePOPCNTD, FeatureLDBRX,
214                   Feature64Bit /*, Feature64BitRegs */]>;
215def : Processor<"ppc", G3Itineraries, [Directive32]>;
216def : Processor<"ppc64", G5Itineraries,
217                  [Directive64, FeatureAltivec,
218                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
219                   Feature64Bit /*, Feature64BitRegs */]>;
220
221
222//===----------------------------------------------------------------------===//
223// Calling Conventions
224//===----------------------------------------------------------------------===//
225
226include "PPCCallingConv.td"
227
228def PPCInstrInfo : InstrInfo {
229  let isLittleEndianEncoding = 1;
230}
231
232def PPCAsmWriter : AsmWriter {
233  string AsmWriterClassName  = "InstPrinter";
234  bit isMCAsmWriter = 1;
235}
236
237def PPC : Target {
238  // Information about the instructions.
239  let InstructionSet = PPCInstrInfo;
240  
241  let AssemblyWriters = [PPCAsmWriter];
242}
243