PPCCallingConv.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This describes the calling conventions for the PowerPC 32- and 64-bit
11// architectures.
12//
13//===----------------------------------------------------------------------===//
14
15/// CCIfSubtarget - Match if the current subtarget has a feature F.
16class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
18class CCIfNotSubtarget<string F, CCAction A>
19 : CCIf<!strconcat("!State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
20
21//===----------------------------------------------------------------------===//
22// Return Value Calling Convention
23//===----------------------------------------------------------------------===//
24
25// Return-value convention for PowerPC
26def RetCC_PPC : CallingConv<[
27  // On PPC64, integer return values are always promoted to i64
28  CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
29  CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,
30
31  CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
32  CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
33  CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
34  
35  CCIfType<[f32], CCAssignToReg<[F1, F2]>>,
36  CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>,
37  
38  // Vector types are always returned in V2.
39  CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>,
40  CCIfType<[v2f64, v2i64], CCAssignToReg<[VSH2]>>
41]>;
42
43
44// Note that we don't currently have calling conventions for 64-bit
45// PowerPC, but handle all the complexities of the ABI in the lowering
46// logic.  FIXME: See if the logic can be simplified with use of CCs.
47// This may require some extensions to current table generation.
48
49// Simple calling convention for 64-bit ELF PowerPC fast isel.
50// Only handle ints and floats.  All ints are promoted to i64.
51// Vector types and quadword ints are not handled.
52def CC_PPC64_ELF_FIS : CallingConv<[
53  CCIfType<[i1],  CCPromoteToType<i64>>,
54  CCIfType<[i8],  CCPromoteToType<i64>>,
55  CCIfType<[i16], CCPromoteToType<i64>>,
56  CCIfType<[i32], CCPromoteToType<i64>>,
57  CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
58  CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>
59]>;
60
61// Simple return-value convention for 64-bit ELF PowerPC fast isel.
62// All small ints are promoted to i64.  Vector types, quadword ints,
63// and multiple register returns are "supported" to avoid compile
64// errors, but none are handled by the fast selector.
65def RetCC_PPC64_ELF_FIS : CallingConv<[
66  CCIfType<[i1],   CCPromoteToType<i64>>,
67  CCIfType<[i8],   CCPromoteToType<i64>>,
68  CCIfType<[i16],  CCPromoteToType<i64>>,
69  CCIfType<[i32],  CCPromoteToType<i64>>,
70  CCIfType<[i64],  CCAssignToReg<[X3, X4]>>,
71  CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
72  CCIfType<[f32],  CCAssignToReg<[F1, F2]>>,
73  CCIfType<[f64],  CCAssignToReg<[F1, F2, F3, F4]>>,
74  CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>,
75  CCIfType<[v2f64, v2i64], CCAssignToReg<[VSH2]>>
76]>;
77
78//===----------------------------------------------------------------------===//
79// PowerPC System V Release 4 32-bit ABI
80//===----------------------------------------------------------------------===//
81
82def CC_PPC32_SVR4_Common : CallingConv<[
83  CCIfType<[i1], CCPromoteToType<i32>>,
84
85  // The ABI requires i64 to be passed in two adjacent registers with the first
86  // register having an odd register number.
87  CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,
88
89  // The first 8 integer arguments are passed in integer registers.
90  CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
91
92  // Make sure the i64 words from a long double are either both passed in
93  // registers or both passed on the stack.
94  CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,
95  
96  // FP values are passed in F1 - F8.
97  CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
98
99  // Split arguments have an alignment of 8 bytes on the stack.
100  CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
101  
102  CCIfType<[i32], CCAssignToStack<4, 4>>,
103  
104  // Floats are stored in double precision format, thus they have the same
105  // alignment and size as doubles.
106  CCIfType<[f32,f64], CCAssignToStack<8, 8>>,  
107
108  // Vectors get 16-byte stack slots that are 16-byte aligned.
109  CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>
110]>;
111
112// This calling convention puts vector arguments always on the stack. It is used
113// to assign vector arguments which belong to the variable portion of the
114// parameter list of a variable argument function.
115def CC_PPC32_SVR4_VarArg : CallingConv<[
116  CCDelegateTo<CC_PPC32_SVR4_Common>
117]>;
118
119// In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to
120// put vector arguments in vector registers before putting them on the stack.
121def CC_PPC32_SVR4 : CallingConv<[
122  // The first 12 Vector arguments are passed in AltiVec registers.
123  CCIfType<[v16i8, v8i16, v4i32, v4f32],
124           CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
125  CCIfType<[v2f64, v2i64],
126           CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9,
127                          VSH10, VSH11, VSH12, VSH13]>>,
128           
129  CCDelegateTo<CC_PPC32_SVR4_Common>
130]>;  
131
132// Helper "calling convention" to handle aggregate by value arguments.
133// Aggregate by value arguments are always placed in the local variable space
134// of the caller. This calling convention is only used to assign those stack
135// offsets in the callers stack frame.
136//
137// Still, the address of the aggregate copy in the callers stack frame is passed
138// in a GPR (or in the parameter list area if all GPRs are allocated) from the
139// caller to the callee. The location for the address argument is assigned by
140// the CC_PPC32_SVR4 calling convention.
141//
142// The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are
143// not passed by value.
144 
145def CC_PPC32_SVR4_ByVal : CallingConv<[
146  CCIfByVal<CCPassByVal<4, 4>>,
147  
148  CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
149]>;
150
151def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
152                                       V28, V29, V30, V31)>;
153
154def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
155                                        R21, R22, R23, R24, R25, R26, R27, R28,
156                                        R29, R30, R31, F14, F15, F16, F17, F18,
157                                        F19, F20, F21, F22, F23, F24, F25, F26,
158                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
159                                   )>;
160
161def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
162
163def CSR_SVR432   : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
164                                        R21, R22, R23, R24, R25, R26, R27, R28,
165                                        R29, R30, R31, F14, F15, F16, F17, F18,
166                                        F19, F20, F21, F22, F23, F24, F25, F26,
167                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
168                                   )>;
169
170def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
171
172def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
173                                        X21, X22, X23, X24, X25, X26, X27, X28,
174                                        X29, X30, X31, F14, F15, F16, F17, F18,
175                                        F19, F20, F21, F22, F23, F24, F25, F26,
176                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
177                                   )>;
178
179def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
180
181def CSR_SVR464   : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
182                                        X21, X22, X23, X24, X25, X26, X27, X28,
183                                        X29, X30, X31, F14, F15, F16, F17, F18,
184                                        F19, F20, F21, F22, F23, F24, F25, F26,
185                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
186                                   )>;
187
188
189def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
190
191def CSR_NoRegs : CalleeSavedRegs<(add)>;
192
193