PPCCodeEmitter.cpp revision 34da72645a82e11bc7008bc567d63426ec4c5949
1//===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC32 -------*- C++ -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the PowerPC 32-bit CodeEmitter and associated machinery to 11// JIT-compile bytecode to native PowerPC. 12// 13//===----------------------------------------------------------------------===// 14 15#include "PPCTargetMachine.h" 16#include "PPCRelocations.h" 17#include "PPC.h" 18#include "llvm/Module.h" 19#include "llvm/PassManager.h" 20#include "llvm/CodeGen/MachineCodeEmitter.h" 21#include "llvm/CodeGen/MachineFunctionPass.h" 22#include "llvm/CodeGen/MachineInstrBuilder.h" 23#include "llvm/CodeGen/Passes.h" 24#include "llvm/Support/Debug.h" 25#include "llvm/Support/Compiler.h" 26#include "llvm/Target/TargetOptions.h" 27using namespace llvm; 28 29namespace { 30 class VISIBILITY_HIDDEN PPCCodeEmitter : public MachineFunctionPass { 31 TargetMachine &TM; 32 MachineCodeEmitter &MCE; 33 34 /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record 35 /// its address in the function into this pointer. 36 void *MovePCtoLROffset; 37 38 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr 39 /// 40 int getMachineOpValue(MachineInstr &MI, MachineOperand &MO); 41 42 public: 43 PPCCodeEmitter(TargetMachine &T, MachineCodeEmitter &M) 44 : TM(T), MCE(M) {} 45 46 const char *getPassName() const { return "PowerPC Machine Code Emitter"; } 47 48 /// runOnMachineFunction - emits the given MachineFunction to memory 49 /// 50 bool runOnMachineFunction(MachineFunction &MF); 51 52 /// emitBasicBlock - emits the given MachineBasicBlock to memory 53 /// 54 void emitBasicBlock(MachineBasicBlock &MBB); 55 56 /// getValueBit - return the particular bit of Val 57 /// 58 unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; } 59 60 /// getBinaryCodeForInstr - This function, generated by the 61 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 62 /// machine instructions. 63 /// 64 unsigned getBinaryCodeForInstr(MachineInstr &MI); 65 }; 66} 67 68/// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code 69/// to the specified MCE object. 70FunctionPass *llvm::createPPCCodeEmitterPass(PPCTargetMachine &TM, 71 MachineCodeEmitter &MCE) { 72 return new PPCCodeEmitter(TM, MCE); 73} 74 75#ifdef __APPLE__ 76extern "C" void sys_icache_invalidate(const void *Addr, size_t len); 77#endif 78 79bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 80 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 81 MF.getTarget().getRelocationModel() != Reloc::Static) && 82 "JIT relocation model must be set to static or default!"); 83 do { 84 MovePCtoLROffset = 0; 85 MCE.startFunction(MF); 86 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) 87 emitBasicBlock(*BB); 88 } while (MCE.finishFunction(MF)); 89 90 return false; 91} 92 93void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { 94 MCE.StartMachineBasicBlock(&MBB); 95 96 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){ 97 MachineInstr &MI = *I; 98 switch (MI.getOpcode()) { 99 default: 100 MCE.emitWordBE(getBinaryCodeForInstr(*I)); 101 break; 102 case PPC::IMPLICIT_DEF_GPRC: 103 case PPC::IMPLICIT_DEF_G8RC: 104 case PPC::IMPLICIT_DEF_F8: 105 case PPC::IMPLICIT_DEF_F4: 106 case PPC::IMPLICIT_DEF_VRRC: 107 break; // pseudo opcode, no side effects 108 case PPC::MovePCtoLR: 109 case PPC::MovePCtoLR8: 110 assert(TM.getRelocationModel() == Reloc::PIC_); 111 MovePCtoLROffset = (void*)MCE.getCurrentPCValue(); 112 MCE.emitWordBE(0x48000005); // bl 1 113 break; 114 } 115 } 116} 117 118int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) { 119 120 intptr_t rv = 0; // Return value; defaults to 0 for unhandled cases 121 // or things that get fixed up later by the JIT. 122 if (MO.isRegister()) { 123 rv = PPCRegisterInfo::getRegisterNumbering(MO.getReg()); 124 125 // Special encoding for MTCRF and MFOCRF, which uses a bit mask for the 126 // register, not the register number directly. 127 if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) && 128 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) { 129 rv = 0x80 >> rv; 130 } 131 } else if (MO.isImmediate()) { 132 rv = MO.getImmedValue(); 133 } else if (MO.isGlobalAddress() || MO.isExternalSymbol() || 134 MO.isConstantPoolIndex() || MO.isJumpTableIndex()) { 135 unsigned Reloc = 0; 136 if (MI.getOpcode() == PPC::BL || MI.getOpcode() == PPC::BL8) 137 Reloc = PPC::reloc_pcrel_bx; 138 else { 139 if (TM.getRelocationModel() == Reloc::PIC_) { 140 assert(MovePCtoLROffset && "MovePCtoLR not seen yet?"); 141 } 142 switch (MI.getOpcode()) { 143 default: MI.dump(); assert(0 && "Unknown instruction for relocation!"); 144 case PPC::LIS: 145 case PPC::LIS8: 146 case PPC::ADDIS: 147 case PPC::ADDIS8: 148 Reloc = PPC::reloc_absolute_high; // Pointer to symbol 149 break; 150 case PPC::LI: 151 case PPC::LI8: 152 case PPC::LA: 153 // Loads. 154 case PPC::LBZ: 155 case PPC::LBZ8: 156 case PPC::LHA: 157 case PPC::LHA8: 158 case PPC::LHZ: 159 case PPC::LHZ8: 160 case PPC::LWZ: 161 case PPC::LWZ8: 162 case PPC::LFS: 163 case PPC::LFD: 164 165 // Stores. 166 case PPC::STB: 167 case PPC::STB8: 168 case PPC::STH: 169 case PPC::STH8: 170 case PPC::STW: 171 case PPC::STW8: 172 case PPC::STFS: 173 case PPC::STFD: 174 Reloc = PPC::reloc_absolute_low; 175 break; 176 177 case PPC::LWA: 178 case PPC::LD: 179 case PPC::STD: 180 case PPC::STD_32: 181 Reloc = PPC::reloc_absolute_low_ix; 182 break; 183 } 184 } 185 186 MachineRelocation R; 187 if (MO.isGlobalAddress()) { 188 R = MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 189 MO.getGlobal(), 0); 190 } else if (MO.isExternalSymbol()) { 191 R = MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 192 Reloc, MO.getSymbolName(), 0); 193 } else if (MO.isConstantPoolIndex()) { 194 R = MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 195 Reloc, MO.getConstantPoolIndex(), 0); 196 } else { 197 assert(MO.isJumpTableIndex()); 198 R = MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 199 Reloc, MO.getJumpTableIndex(), 0); 200 } 201 202 // If in PIC mode, we need to encode the negated address of the 203 // 'movepctolr' into the unrelocated field. After relocation, we'll have 204 // &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm 205 // field, we get &gv. This doesn't happen for branch relocations, which are 206 // always implicitly pc relative. 207 if (TM.getRelocationModel() == Reloc::PIC_ && Reloc != PPC::reloc_pcrel_bx){ 208 assert(MovePCtoLROffset && "MovePCtoLR not seen yet?"); 209 R.setConstantVal(-(intptr_t)MovePCtoLROffset - 4); 210 } 211 MCE.addRelocation(R); 212 213 } else if (MO.isMachineBasicBlock()) { 214 unsigned Reloc = 0; 215 unsigned Opcode = MI.getOpcode(); 216 if (Opcode == PPC::B || Opcode == PPC::BL || Opcode == PPC::BLA) 217 Reloc = PPC::reloc_pcrel_bx; 218 else // BCC instruction 219 Reloc = PPC::reloc_pcrel_bcx; 220 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 221 Reloc, 222 MO.getMachineBasicBlock())); 223 } else { 224 cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; 225 abort(); 226 } 227 228 return rv; 229} 230 231#include "PPCGenCodeEmitter.inc" 232 233