PPCCodeEmitter.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
11// JIT-compile bitcode to native PowerPC.
12//
13//===----------------------------------------------------------------------===//
14
15#include "PPC.h"
16#include "PPCRelocations.h"
17#include "PPCTargetMachine.h"
18#include "llvm/CodeGen/JITCodeEmitter.h"
19#include "llvm/CodeGen/MachineFunctionPass.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineModuleInfo.h"
22#include "llvm/IR/Module.h"
23#include "llvm/PassManager.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/raw_ostream.h"
26#include "llvm/Target/TargetOptions.h"
27using namespace llvm;
28
29namespace {
30  class PPCCodeEmitter : public MachineFunctionPass {
31    TargetMachine &TM;
32    JITCodeEmitter &MCE;
33    MachineModuleInfo *MMI;
34
35    void getAnalysisUsage(AnalysisUsage &AU) const {
36      AU.addRequired<MachineModuleInfo>();
37      MachineFunctionPass::getAnalysisUsage(AU);
38    }
39
40    static char ID;
41
42    /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
43    /// its address in the function into this pointer.
44    void *MovePCtoLROffset;
45  public:
46
47    PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
48      : MachineFunctionPass(ID), TM(tm), MCE(mce) {}
49
50    /// getBinaryCodeForInstr - This function, generated by the
51    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
52    /// machine instructions.
53    uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
54
55
56    MachineRelocation GetRelocation(const MachineOperand &MO,
57                                    unsigned RelocID) const;
58
59    /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
60    unsigned getMachineOpValue(const MachineInstr &MI,
61                               const MachineOperand &MO) const;
62
63    unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
64    unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
65    unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
66    unsigned getAbsDirectBrEncoding(const MachineInstr &MI,
67                                    unsigned OpNo) const;
68    unsigned getAbsCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
69
70    unsigned getImm16Encoding(const MachineInstr &MI, unsigned OpNo) const;
71    unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
72    unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
73    unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const;
74    unsigned getTLSCallEncoding(const MachineInstr &MI, unsigned OpNo) const;
75
76    const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
77
78    /// runOnMachineFunction - emits the given MachineFunction to memory
79    ///
80    bool runOnMachineFunction(MachineFunction &MF);
81
82    /// emitBasicBlock - emits the given MachineBasicBlock to memory
83    ///
84    void emitBasicBlock(MachineBasicBlock &MBB);
85  };
86}
87
88char PPCCodeEmitter::ID = 0;
89
90/// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
91/// to the specified MCE object.
92FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
93                                                JITCodeEmitter &JCE) {
94  return new PPCCodeEmitter(TM, JCE);
95}
96
97bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
98  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
99          MF.getTarget().getRelocationModel() != Reloc::Static) &&
100         "JIT relocation model must be set to static or default!");
101
102  MMI = &getAnalysis<MachineModuleInfo>();
103  MCE.setModuleInfo(MMI);
104  do {
105    MovePCtoLROffset = 0;
106    MCE.startFunction(MF);
107    for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
108      emitBasicBlock(*BB);
109  } while (MCE.finishFunction(MF));
110
111  return false;
112}
113
114void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
115  MCE.StartMachineBasicBlock(&MBB);
116
117  for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
118    const MachineInstr &MI = *I;
119    MCE.processDebugLoc(MI.getDebugLoc(), true);
120    switch (MI.getOpcode()) {
121    default:
122      MCE.emitWordBE(getBinaryCodeForInstr(MI));
123      break;
124    case TargetOpcode::CFI_INSTRUCTION:
125      break;
126    case TargetOpcode::EH_LABEL:
127      MCE.emitLabel(MI.getOperand(0).getMCSymbol());
128      break;
129    case TargetOpcode::IMPLICIT_DEF:
130    case TargetOpcode::KILL:
131      break; // pseudo opcode, no side effects
132    case PPC::MovePCtoLR:
133    case PPC::MovePCtoLR8:
134      assert(TM.getRelocationModel() == Reloc::PIC_);
135      MovePCtoLROffset = (void*)MCE.getCurrentPCValue();
136      MCE.emitWordBE(0x48000005);   // bl 1
137      break;
138    }
139    MCE.processDebugLoc(MI.getDebugLoc(), false);
140  }
141}
142
143unsigned PPCCodeEmitter::get_crbitm_encoding(const MachineInstr &MI,
144                                             unsigned OpNo) const {
145  const MachineOperand &MO = MI.getOperand(OpNo);
146  assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
147          MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
148         (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
149  return 0x80 >> TM.getRegisterInfo()->getEncodingValue(MO.getReg());
150}
151
152MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO,
153                                                unsigned RelocID) const {
154  // If in PIC mode, we need to encode the negated address of the
155  // 'movepctolr' into the unrelocated field.  After relocation, we'll have
156  // &gv-&movepctolr-4 in the imm field.  Once &movepctolr is added to the imm
157  // field, we get &gv.  This doesn't happen for branch relocations, which are
158  // always implicitly pc relative.
159  intptr_t Cst = 0;
160  if (TM.getRelocationModel() == Reloc::PIC_) {
161    assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
162    Cst = -(intptr_t)MovePCtoLROffset - 4;
163  }
164
165  if (MO.isGlobal())
166    return MachineRelocation::getGV(MCE.getCurrentPCOffset(), RelocID,
167                                    const_cast<GlobalValue *>(MO.getGlobal()),
168                                    Cst, isa<Function>(MO.getGlobal()));
169  if (MO.isSymbol())
170    return MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
171                                        RelocID, MO.getSymbolName(), Cst);
172  if (MO.isCPI())
173    return MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
174                                           RelocID, MO.getIndex(), Cst);
175
176  if (MO.isMBB())
177    return MachineRelocation::getBB(MCE.getCurrentPCOffset(),
178                                    RelocID, MO.getMBB());
179
180  assert(MO.isJTI());
181  return MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
182                                         RelocID, MO.getIndex(), Cst);
183}
184
185unsigned PPCCodeEmitter::getDirectBrEncoding(const MachineInstr &MI,
186                                             unsigned OpNo) const {
187  const MachineOperand &MO = MI.getOperand(OpNo);
188  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
189
190  MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bx));
191  return 0;
192}
193
194unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI,
195                                           unsigned OpNo) const {
196  const MachineOperand &MO = MI.getOperand(OpNo);
197  MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bcx));
198  return 0;
199}
200
201unsigned PPCCodeEmitter::getAbsDirectBrEncoding(const MachineInstr &MI,
202                                                unsigned OpNo) const {
203  const MachineOperand &MO = MI.getOperand(OpNo);
204  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
205
206  llvm_unreachable("Absolute branch relocations unsupported on the old JIT.");
207}
208
209unsigned PPCCodeEmitter::getAbsCondBrEncoding(const MachineInstr &MI,
210                                              unsigned OpNo) const {
211  llvm_unreachable("Absolute branch relocations unsupported on the old JIT.");
212}
213
214unsigned PPCCodeEmitter::getImm16Encoding(const MachineInstr &MI,
215                                          unsigned OpNo) const {
216  const MachineOperand &MO = MI.getOperand(OpNo);
217  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
218
219  unsigned RelocID;
220  switch (MO.getTargetFlags() & PPCII::MO_ACCESS_MASK) {
221    default: llvm_unreachable("Unsupported target operand flags!");
222    case PPCII::MO_LO: RelocID = PPC::reloc_absolute_low; break;
223    case PPCII::MO_HA: RelocID = PPC::reloc_absolute_high; break;
224  }
225
226  MCE.addRelocation(GetRelocation(MO, RelocID));
227  return 0;
228}
229
230unsigned PPCCodeEmitter::getMemRIEncoding(const MachineInstr &MI,
231                                          unsigned OpNo) const {
232  // Encode (imm, reg) as a memri, which has the low 16-bits as the
233  // displacement and the next 5 bits as the register #.
234  assert(MI.getOperand(OpNo+1).isReg());
235  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16;
236
237  const MachineOperand &MO = MI.getOperand(OpNo);
238  if (MO.isImm())
239    return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits;
240
241  // Add a fixup for the displacement field.
242  MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low));
243  return RegBits;
244}
245
246unsigned PPCCodeEmitter::getMemRIXEncoding(const MachineInstr &MI,
247                                           unsigned OpNo) const {
248  // Encode (imm, reg) as a memrix, which has the low 14-bits as the
249  // displacement and the next 5 bits as the register #.
250  assert(MI.getOperand(OpNo+1).isReg());
251  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14;
252
253  const MachineOperand &MO = MI.getOperand(OpNo);
254  if (MO.isImm())
255    return ((getMachineOpValue(MI, MO) >> 2) & 0x3FFF) | RegBits;
256
257  MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low_ix));
258  return RegBits;
259}
260
261
262unsigned PPCCodeEmitter::getTLSRegEncoding(const MachineInstr &MI,
263                                           unsigned OpNo) const {
264  llvm_unreachable("TLS not supported on the old JIT.");
265  return 0;
266}
267
268unsigned PPCCodeEmitter::getTLSCallEncoding(const MachineInstr &MI,
269                                            unsigned OpNo) const {
270  llvm_unreachable("TLS not supported on the old JIT.");
271  return 0;
272}
273
274unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
275                                           const MachineOperand &MO) const {
276
277  if (MO.isReg()) {
278    // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
279    // The GPR operand should come through here though.
280    assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
281            MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
282           MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
283    return TM.getRegisterInfo()->getEncodingValue(MO.getReg());
284  }
285
286  assert(MO.isImm() &&
287         "Relocation required in an instruction that we cannot encode!");
288  return MO.getImm();
289}
290
291#include "PPCGenCodeEmitter.inc"
292