PPCISelLowering.cpp revision 0c9b559bfd0b476c2dde787285a1195f3142c423
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPerfectShuffle.h" 17#include "PPCPredicates.h" 18#include "PPCTargetMachine.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 29#include "llvm/CallingConv.h" 30#include "llvm/Constants.h" 31#include "llvm/Function.h" 32#include "llvm/Intrinsics.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/DerivedTypes.h" 39using namespace llvm; 40 41static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 42 CCValAssign::LocInfo &LocInfo, 43 ISD::ArgFlagsTy &ArgFlags, 44 CCState &State); 45static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 46 MVT &LocVT, 47 CCValAssign::LocInfo &LocInfo, 48 ISD::ArgFlagsTy &ArgFlags, 49 CCState &State); 50static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 51 MVT &LocVT, 52 CCValAssign::LocInfo &LocInfo, 53 ISD::ArgFlagsTy &ArgFlags, 54 CCState &State); 55 56static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 57cl::desc("enable preincrement load/store generation on PPC (experimental)"), 58 cl::Hidden); 59 60static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 61 if (TM.getSubtargetImpl()->isDarwin()) 62 return new TargetLoweringObjectFileMachO(); 63 64 return new TargetLoweringObjectFileELF(); 65} 66 67PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 69 70 setPow2DivIsCheap(); 71 72 // Use _setjmp/_longjmp instead of setjmp/longjmp. 73 setUseUnderscoreSetJmp(true); 74 setUseUnderscoreLongJmp(true); 75 76 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all 77 // arguments are at least 4/8 bytes aligned. 78 setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4); 79 80 // Set up the register classes. 81 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 82 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 83 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 84 85 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 86 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 87 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 88 89 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 90 91 // PowerPC has pre-inc load and store's. 92 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 93 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 94 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 95 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 96 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 97 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 98 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 99 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 100 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 101 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 102 103 // This is used in the ppcf128->int sequence. Note it has different semantics 104 // from FP_ROUND: that rounds to nearest, this rounds to zero. 105 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 106 107 // PowerPC has no SREM/UREM instructions 108 setOperationAction(ISD::SREM, MVT::i32, Expand); 109 setOperationAction(ISD::UREM, MVT::i32, Expand); 110 setOperationAction(ISD::SREM, MVT::i64, Expand); 111 setOperationAction(ISD::UREM, MVT::i64, Expand); 112 113 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 114 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 115 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 116 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 117 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 118 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 119 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 120 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 121 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 122 123 // We don't support sin/cos/sqrt/fmod/pow 124 setOperationAction(ISD::FSIN , MVT::f64, Expand); 125 setOperationAction(ISD::FCOS , MVT::f64, Expand); 126 setOperationAction(ISD::FREM , MVT::f64, Expand); 127 setOperationAction(ISD::FPOW , MVT::f64, Expand); 128 setOperationAction(ISD::FSIN , MVT::f32, Expand); 129 setOperationAction(ISD::FCOS , MVT::f32, Expand); 130 setOperationAction(ISD::FREM , MVT::f32, Expand); 131 setOperationAction(ISD::FPOW , MVT::f32, Expand); 132 133 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 134 135 // If we're enabling GP optimizations, use hardware square root 136 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 137 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 138 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 139 } 140 141 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 142 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 143 144 // PowerPC does not have BSWAP, CTPOP or CTTZ 145 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 146 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 147 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 148 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 149 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 150 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 151 152 // PowerPC does not have ROTR 153 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 154 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 155 156 // PowerPC does not have Select 157 setOperationAction(ISD::SELECT, MVT::i32, Expand); 158 setOperationAction(ISD::SELECT, MVT::i64, Expand); 159 setOperationAction(ISD::SELECT, MVT::f32, Expand); 160 setOperationAction(ISD::SELECT, MVT::f64, Expand); 161 162 // PowerPC wants to turn select_cc of FP into fsel when possible. 163 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 164 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 165 166 // PowerPC wants to optimize integer setcc a bit 167 setOperationAction(ISD::SETCC, MVT::i32, Custom); 168 169 // PowerPC does not have BRCOND which requires SetCC 170 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 171 172 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 173 174 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 175 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 176 177 // PowerPC does not have [U|S]INT_TO_FP 178 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 179 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 180 181 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 182 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 183 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 184 setOperationAction(ISD::BITCAST, MVT::f64, Expand); 185 186 // We cannot sextinreg(i1). Expand to shifts. 187 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 188 189 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 190 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 191 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 192 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 193 194 195 // We want to legalize GlobalAddress and ConstantPool nodes into the 196 // appropriate instructions to materialize the address. 197 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 199 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 200 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 201 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 202 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 203 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 204 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 205 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 206 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 207 208 // TRAP is legal. 209 setOperationAction(ISD::TRAP, MVT::Other, Legal); 210 211 // TRAMPOLINE is custom lowered. 212 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 213 214 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 215 setOperationAction(ISD::VASTART , MVT::Other, Custom); 216 217 // VAARG is custom lowered with the 32-bit SVR4 ABI. 218 if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 219 && !TM.getSubtarget<PPCSubtarget>().isPPC64()) 220 setOperationAction(ISD::VAARG, MVT::Other, Custom); 221 else 222 setOperationAction(ISD::VAARG, MVT::Other, Expand); 223 224 // Use the default implementation. 225 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 226 setOperationAction(ISD::VAEND , MVT::Other, Expand); 227 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 228 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 229 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 230 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 231 232 // We want to custom lower some of our intrinsics. 233 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 234 235 // Comparisons that require checking two conditions. 236 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 237 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 238 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 239 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 240 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 241 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 242 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 243 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 244 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 245 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 246 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 247 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 248 249 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 250 // They also have instructions for converting between i64 and fp. 251 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 252 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 253 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 254 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 255 // This is just the low 32 bits of a (signed) fp->i64 conversion. 256 // We cannot do this with Promote because i64 is not a legal type. 257 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 258 259 // FIXME: disable this lowered code. This generates 64-bit register values, 260 // and we don't model the fact that the top part is clobbered by calls. We 261 // need to flag these together so that the value isn't live across a call. 262 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 263 } else { 264 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 265 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 266 } 267 268 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 269 // 64-bit PowerPC implementations can support i64 types directly 270 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 271 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 272 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 273 // 64-bit PowerPC wants to expand i128 shifts itself. 274 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 275 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 276 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 277 } else { 278 // 32-bit PowerPC wants to expand i64 shifts itself. 279 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 280 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 281 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 282 } 283 284 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 285 // First set operation action for all vector types to expand. Then we 286 // will selectively turn on ones that can be effectively codegen'd. 287 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 288 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 289 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 290 291 // add/sub are legal for all supported vector VT's. 292 setOperationAction(ISD::ADD , VT, Legal); 293 setOperationAction(ISD::SUB , VT, Legal); 294 295 // We promote all shuffles to v16i8. 296 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 297 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 298 299 // We promote all non-typed operations to v4i32. 300 setOperationAction(ISD::AND , VT, Promote); 301 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 302 setOperationAction(ISD::OR , VT, Promote); 303 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 304 setOperationAction(ISD::XOR , VT, Promote); 305 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 306 setOperationAction(ISD::LOAD , VT, Promote); 307 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 308 setOperationAction(ISD::SELECT, VT, Promote); 309 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 310 setOperationAction(ISD::STORE, VT, Promote); 311 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 312 313 // No other operations are legal. 314 setOperationAction(ISD::MUL , VT, Expand); 315 setOperationAction(ISD::SDIV, VT, Expand); 316 setOperationAction(ISD::SREM, VT, Expand); 317 setOperationAction(ISD::UDIV, VT, Expand); 318 setOperationAction(ISD::UREM, VT, Expand); 319 setOperationAction(ISD::FDIV, VT, Expand); 320 setOperationAction(ISD::FNEG, VT, Expand); 321 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 322 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 323 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 324 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 325 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 326 setOperationAction(ISD::UDIVREM, VT, Expand); 327 setOperationAction(ISD::SDIVREM, VT, Expand); 328 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 329 setOperationAction(ISD::FPOW, VT, Expand); 330 setOperationAction(ISD::CTPOP, VT, Expand); 331 setOperationAction(ISD::CTLZ, VT, Expand); 332 setOperationAction(ISD::CTTZ, VT, Expand); 333 } 334 335 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 336 // with merges, splats, etc. 337 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 338 339 setOperationAction(ISD::AND , MVT::v4i32, Legal); 340 setOperationAction(ISD::OR , MVT::v4i32, Legal); 341 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 342 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 343 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 344 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 345 346 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 347 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 348 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 349 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 350 351 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 352 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 353 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 354 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 355 356 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 357 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 358 359 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 360 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 361 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 362 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 363 } 364 365 setBooleanContents(ZeroOrOneBooleanContent); 366 367 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 368 setStackPointerRegisterToSaveRestore(PPC::X1); 369 setExceptionPointerRegister(PPC::X3); 370 setExceptionSelectorRegister(PPC::X4); 371 } else { 372 setStackPointerRegisterToSaveRestore(PPC::R1); 373 setExceptionPointerRegister(PPC::R3); 374 setExceptionSelectorRegister(PPC::R4); 375 } 376 377 // We have target-specific dag combine patterns for the following nodes: 378 setTargetDAGCombine(ISD::SINT_TO_FP); 379 setTargetDAGCombine(ISD::STORE); 380 setTargetDAGCombine(ISD::BR_CC); 381 setTargetDAGCombine(ISD::BSWAP); 382 383 // Darwin long double math library functions have $LDBL128 appended. 384 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 385 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 386 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 387 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 388 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 389 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 390 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 391 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 392 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 393 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 394 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 395 } 396 397 setMinFunctionAlignment(2); 398 if (PPCSubTarget.isDarwin()) 399 setPrefFunctionAlignment(4); 400 401 computeRegisterProperties(); 402} 403 404/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 405/// function arguments in the caller parameter area. 406unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const { 407 const TargetMachine &TM = getTargetMachine(); 408 // Darwin passes everything on 4 byte boundary. 409 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 410 return 4; 411 // FIXME SVR4 TBD 412 return 4; 413} 414 415const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 416 switch (Opcode) { 417 default: return 0; 418 case PPCISD::FSEL: return "PPCISD::FSEL"; 419 case PPCISD::FCFID: return "PPCISD::FCFID"; 420 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 421 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 422 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 423 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 424 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 425 case PPCISD::VPERM: return "PPCISD::VPERM"; 426 case PPCISD::Hi: return "PPCISD::Hi"; 427 case PPCISD::Lo: return "PPCISD::Lo"; 428 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 429 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 430 case PPCISD::LOAD: return "PPCISD::LOAD"; 431 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 432 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 433 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 434 case PPCISD::SRL: return "PPCISD::SRL"; 435 case PPCISD::SRA: return "PPCISD::SRA"; 436 case PPCISD::SHL: return "PPCISD::SHL"; 437 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 438 case PPCISD::STD_32: return "PPCISD::STD_32"; 439 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4"; 440 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin"; 441 case PPCISD::NOP: return "PPCISD::NOP"; 442 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 443 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin"; 444 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4"; 445 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 446 case PPCISD::MFCR: return "PPCISD::MFCR"; 447 case PPCISD::VCMP: return "PPCISD::VCMP"; 448 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 449 case PPCISD::LBRX: return "PPCISD::LBRX"; 450 case PPCISD::STBRX: return "PPCISD::STBRX"; 451 case PPCISD::LARX: return "PPCISD::LARX"; 452 case PPCISD::STCX: return "PPCISD::STCX"; 453 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 454 case PPCISD::MFFS: return "PPCISD::MFFS"; 455 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 456 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 457 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 458 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 459 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 460 } 461} 462 463MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const { 464 return MVT::i32; 465} 466 467//===----------------------------------------------------------------------===// 468// Node matching predicates, for use by the tblgen matching code. 469//===----------------------------------------------------------------------===// 470 471/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 472static bool isFloatingPointZero(SDValue Op) { 473 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 474 return CFP->getValueAPF().isZero(); 475 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 476 // Maybe this has already been legalized into the constant pool? 477 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 478 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 479 return CFP->getValueAPF().isZero(); 480 } 481 return false; 482} 483 484/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 485/// true if Op is undef or if it matches the specified value. 486static bool isConstantOrUndef(int Op, int Val) { 487 return Op < 0 || Op == Val; 488} 489 490/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 491/// VPKUHUM instruction. 492bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 493 if (!isUnary) { 494 for (unsigned i = 0; i != 16; ++i) 495 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 496 return false; 497 } else { 498 for (unsigned i = 0; i != 8; ++i) 499 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 500 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 501 return false; 502 } 503 return true; 504} 505 506/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 507/// VPKUWUM instruction. 508bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 509 if (!isUnary) { 510 for (unsigned i = 0; i != 16; i += 2) 511 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 512 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 513 return false; 514 } else { 515 for (unsigned i = 0; i != 8; i += 2) 516 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 517 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 518 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 519 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 520 return false; 521 } 522 return true; 523} 524 525/// isVMerge - Common function, used to match vmrg* shuffles. 526/// 527static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 528 unsigned LHSStart, unsigned RHSStart) { 529 assert(N->getValueType(0) == MVT::v16i8 && 530 "PPC only supports shuffles by bytes!"); 531 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 532 "Unsupported merge size!"); 533 534 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 535 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 536 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 537 LHSStart+j+i*UnitSize) || 538 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 539 RHSStart+j+i*UnitSize)) 540 return false; 541 } 542 return true; 543} 544 545/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 546/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 547bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 548 bool isUnary) { 549 if (!isUnary) 550 return isVMerge(N, UnitSize, 8, 24); 551 return isVMerge(N, UnitSize, 8, 8); 552} 553 554/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 555/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 556bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 557 bool isUnary) { 558 if (!isUnary) 559 return isVMerge(N, UnitSize, 0, 16); 560 return isVMerge(N, UnitSize, 0, 0); 561} 562 563 564/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 565/// amount, otherwise return -1. 566int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 567 assert(N->getValueType(0) == MVT::v16i8 && 568 "PPC only supports shuffles by bytes!"); 569 570 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 571 572 // Find the first non-undef value in the shuffle mask. 573 unsigned i; 574 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 575 /*search*/; 576 577 if (i == 16) return -1; // all undef. 578 579 // Otherwise, check to see if the rest of the elements are consecutively 580 // numbered from this value. 581 unsigned ShiftAmt = SVOp->getMaskElt(i); 582 if (ShiftAmt < i) return -1; 583 ShiftAmt -= i; 584 585 if (!isUnary) { 586 // Check the rest of the elements to see if they are consecutive. 587 for (++i; i != 16; ++i) 588 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 589 return -1; 590 } else { 591 // Check the rest of the elements to see if they are consecutive. 592 for (++i; i != 16; ++i) 593 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 594 return -1; 595 } 596 return ShiftAmt; 597} 598 599/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 600/// specifies a splat of a single element that is suitable for input to 601/// VSPLTB/VSPLTH/VSPLTW. 602bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 603 assert(N->getValueType(0) == MVT::v16i8 && 604 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 605 606 // This is a splat operation if each element of the permute is the same, and 607 // if the value doesn't reference the second vector. 608 unsigned ElementBase = N->getMaskElt(0); 609 610 // FIXME: Handle UNDEF elements too! 611 if (ElementBase >= 16) 612 return false; 613 614 // Check that the indices are consecutive, in the case of a multi-byte element 615 // splatted with a v16i8 mask. 616 for (unsigned i = 1; i != EltSize; ++i) 617 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 618 return false; 619 620 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 621 if (N->getMaskElt(i) < 0) continue; 622 for (unsigned j = 0; j != EltSize; ++j) 623 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 624 return false; 625 } 626 return true; 627} 628 629/// isAllNegativeZeroVector - Returns true if all elements of build_vector 630/// are -0.0. 631bool PPC::isAllNegativeZeroVector(SDNode *N) { 632 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 633 634 APInt APVal, APUndef; 635 unsigned BitSize; 636 bool HasAnyUndefs; 637 638 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 639 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 640 return CFP->getValueAPF().isNegZero(); 641 642 return false; 643} 644 645/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 646/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 647unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 648 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 649 assert(isSplatShuffleMask(SVOp, EltSize)); 650 return SVOp->getMaskElt(0) / EltSize; 651} 652 653/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 654/// by using a vspltis[bhw] instruction of the specified element size, return 655/// the constant being splatted. The ByteSize field indicates the number of 656/// bytes of each element [124] -> [bhw]. 657SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 658 SDValue OpVal(0, 0); 659 660 // If ByteSize of the splat is bigger than the element size of the 661 // build_vector, then we have a case where we are checking for a splat where 662 // multiple elements of the buildvector are folded together into a single 663 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 664 unsigned EltSize = 16/N->getNumOperands(); 665 if (EltSize < ByteSize) { 666 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 667 SDValue UniquedVals[4]; 668 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 669 670 // See if all of the elements in the buildvector agree across. 671 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 672 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 673 // If the element isn't a constant, bail fully out. 674 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 675 676 677 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 678 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 679 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 680 return SDValue(); // no match. 681 } 682 683 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 684 // either constant or undef values that are identical for each chunk. See 685 // if these chunks can form into a larger vspltis*. 686 687 // Check to see if all of the leading entries are either 0 or -1. If 688 // neither, then this won't fit into the immediate field. 689 bool LeadingZero = true; 690 bool LeadingOnes = true; 691 for (unsigned i = 0; i != Multiple-1; ++i) { 692 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 693 694 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 695 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 696 } 697 // Finally, check the least significant entry. 698 if (LeadingZero) { 699 if (UniquedVals[Multiple-1].getNode() == 0) 700 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 701 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 702 if (Val < 16) 703 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 704 } 705 if (LeadingOnes) { 706 if (UniquedVals[Multiple-1].getNode() == 0) 707 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 708 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 709 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 710 return DAG.getTargetConstant(Val, MVT::i32); 711 } 712 713 return SDValue(); 714 } 715 716 // Check to see if this buildvec has a single non-undef value in its elements. 717 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 718 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 719 if (OpVal.getNode() == 0) 720 OpVal = N->getOperand(i); 721 else if (OpVal != N->getOperand(i)) 722 return SDValue(); 723 } 724 725 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 726 727 unsigned ValSizeInBytes = EltSize; 728 uint64_t Value = 0; 729 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 730 Value = CN->getZExtValue(); 731 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 732 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 733 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 734 } 735 736 // If the splat value is larger than the element value, then we can never do 737 // this splat. The only case that we could fit the replicated bits into our 738 // immediate field for would be zero, and we prefer to use vxor for it. 739 if (ValSizeInBytes < ByteSize) return SDValue(); 740 741 // If the element value is larger than the splat value, cut it in half and 742 // check to see if the two halves are equal. Continue doing this until we 743 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 744 while (ValSizeInBytes > ByteSize) { 745 ValSizeInBytes >>= 1; 746 747 // If the top half equals the bottom half, we're still ok. 748 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 749 (Value & ((1 << (8*ValSizeInBytes))-1))) 750 return SDValue(); 751 } 752 753 // Properly sign extend the value. 754 int ShAmt = (4-ByteSize)*8; 755 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 756 757 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 758 if (MaskVal == 0) return SDValue(); 759 760 // Finally, if this value fits in a 5 bit sext field, return it 761 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 762 return DAG.getTargetConstant(MaskVal, MVT::i32); 763 return SDValue(); 764} 765 766//===----------------------------------------------------------------------===// 767// Addressing Mode Selection 768//===----------------------------------------------------------------------===// 769 770/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 771/// or 64-bit immediate, and if the value can be accurately represented as a 772/// sign extension from a 16-bit value. If so, this returns true and the 773/// immediate. 774static bool isIntS16Immediate(SDNode *N, short &Imm) { 775 if (N->getOpcode() != ISD::Constant) 776 return false; 777 778 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 779 if (N->getValueType(0) == MVT::i32) 780 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 781 else 782 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 783} 784static bool isIntS16Immediate(SDValue Op, short &Imm) { 785 return isIntS16Immediate(Op.getNode(), Imm); 786} 787 788 789/// SelectAddressRegReg - Given the specified addressed, check to see if it 790/// can be represented as an indexed [r+r] operation. Returns false if it 791/// can be more efficiently represented with [r+imm]. 792bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 793 SDValue &Index, 794 SelectionDAG &DAG) const { 795 short imm = 0; 796 if (N.getOpcode() == ISD::ADD) { 797 if (isIntS16Immediate(N.getOperand(1), imm)) 798 return false; // r+i 799 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 800 return false; // r+i 801 802 Base = N.getOperand(0); 803 Index = N.getOperand(1); 804 return true; 805 } else if (N.getOpcode() == ISD::OR) { 806 if (isIntS16Immediate(N.getOperand(1), imm)) 807 return false; // r+i can fold it if we can. 808 809 // If this is an or of disjoint bitfields, we can codegen this as an add 810 // (for better address arithmetic) if the LHS and RHS of the OR are provably 811 // disjoint. 812 APInt LHSKnownZero, LHSKnownOne; 813 APInt RHSKnownZero, RHSKnownOne; 814 DAG.ComputeMaskedBits(N.getOperand(0), 815 APInt::getAllOnesValue(N.getOperand(0) 816 .getValueSizeInBits()), 817 LHSKnownZero, LHSKnownOne); 818 819 if (LHSKnownZero.getBoolValue()) { 820 DAG.ComputeMaskedBits(N.getOperand(1), 821 APInt::getAllOnesValue(N.getOperand(1) 822 .getValueSizeInBits()), 823 RHSKnownZero, RHSKnownOne); 824 // If all of the bits are known zero on the LHS or RHS, the add won't 825 // carry. 826 if (~(LHSKnownZero | RHSKnownZero) == 0) { 827 Base = N.getOperand(0); 828 Index = N.getOperand(1); 829 return true; 830 } 831 } 832 } 833 834 return false; 835} 836 837/// Returns true if the address N can be represented by a base register plus 838/// a signed 16-bit displacement [r+imm], and if it is not better 839/// represented as reg+reg. 840bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 841 SDValue &Base, 842 SelectionDAG &DAG) const { 843 // FIXME dl should come from parent load or store, not from address 844 DebugLoc dl = N.getDebugLoc(); 845 // If this can be more profitably realized as r+r, fail. 846 if (SelectAddressRegReg(N, Disp, Base, DAG)) 847 return false; 848 849 if (N.getOpcode() == ISD::ADD) { 850 short imm = 0; 851 if (isIntS16Immediate(N.getOperand(1), imm)) { 852 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 853 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 854 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 855 } else { 856 Base = N.getOperand(0); 857 } 858 return true; // [r+i] 859 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 860 // Match LOAD (ADD (X, Lo(G))). 861 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 862 && "Cannot handle constant offsets yet!"); 863 Disp = N.getOperand(1).getOperand(0); // The global address. 864 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 865 Disp.getOpcode() == ISD::TargetConstantPool || 866 Disp.getOpcode() == ISD::TargetJumpTable); 867 Base = N.getOperand(0); 868 return true; // [&g+r] 869 } 870 } else if (N.getOpcode() == ISD::OR) { 871 short imm = 0; 872 if (isIntS16Immediate(N.getOperand(1), imm)) { 873 // If this is an or of disjoint bitfields, we can codegen this as an add 874 // (for better address arithmetic) if the LHS and RHS of the OR are 875 // provably disjoint. 876 APInt LHSKnownZero, LHSKnownOne; 877 DAG.ComputeMaskedBits(N.getOperand(0), 878 APInt::getAllOnesValue(N.getOperand(0) 879 .getValueSizeInBits()), 880 LHSKnownZero, LHSKnownOne); 881 882 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 883 // If all of the bits are known zero on the LHS or RHS, the add won't 884 // carry. 885 Base = N.getOperand(0); 886 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 887 return true; 888 } 889 } 890 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 891 // Loading from a constant address. 892 893 // If this address fits entirely in a 16-bit sext immediate field, codegen 894 // this as "d, 0" 895 short Imm; 896 if (isIntS16Immediate(CN, Imm)) { 897 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 898 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 899 CN->getValueType(0)); 900 return true; 901 } 902 903 // Handle 32-bit sext immediates with LIS + addr mode. 904 if (CN->getValueType(0) == MVT::i32 || 905 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 906 int Addr = (int)CN->getZExtValue(); 907 908 // Otherwise, break this down into an LIS + disp. 909 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 910 911 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 912 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 913 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 914 return true; 915 } 916 } 917 918 Disp = DAG.getTargetConstant(0, getPointerTy()); 919 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 920 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 921 else 922 Base = N; 923 return true; // [r+0] 924} 925 926/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 927/// represented as an indexed [r+r] operation. 928bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 929 SDValue &Index, 930 SelectionDAG &DAG) const { 931 // Check to see if we can easily represent this as an [r+r] address. This 932 // will fail if it thinks that the address is more profitably represented as 933 // reg+imm, e.g. where imm = 0. 934 if (SelectAddressRegReg(N, Base, Index, DAG)) 935 return true; 936 937 // If the operand is an addition, always emit this as [r+r], since this is 938 // better (for code size, and execution, as the memop does the add for free) 939 // than emitting an explicit add. 940 if (N.getOpcode() == ISD::ADD) { 941 Base = N.getOperand(0); 942 Index = N.getOperand(1); 943 return true; 944 } 945 946 // Otherwise, do it the hard way, using R0 as the base register. 947 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 948 N.getValueType()); 949 Index = N; 950 return true; 951} 952 953/// SelectAddressRegImmShift - Returns true if the address N can be 954/// represented by a base register plus a signed 14-bit displacement 955/// [r+imm*4]. Suitable for use by STD and friends. 956bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 957 SDValue &Base, 958 SelectionDAG &DAG) const { 959 // FIXME dl should come from the parent load or store, not the address 960 DebugLoc dl = N.getDebugLoc(); 961 // If this can be more profitably realized as r+r, fail. 962 if (SelectAddressRegReg(N, Disp, Base, DAG)) 963 return false; 964 965 if (N.getOpcode() == ISD::ADD) { 966 short imm = 0; 967 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 968 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 969 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 970 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 971 } else { 972 Base = N.getOperand(0); 973 } 974 return true; // [r+i] 975 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 976 // Match LOAD (ADD (X, Lo(G))). 977 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 978 && "Cannot handle constant offsets yet!"); 979 Disp = N.getOperand(1).getOperand(0); // The global address. 980 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 981 Disp.getOpcode() == ISD::TargetConstantPool || 982 Disp.getOpcode() == ISD::TargetJumpTable); 983 Base = N.getOperand(0); 984 return true; // [&g+r] 985 } 986 } else if (N.getOpcode() == ISD::OR) { 987 short imm = 0; 988 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 989 // If this is an or of disjoint bitfields, we can codegen this as an add 990 // (for better address arithmetic) if the LHS and RHS of the OR are 991 // provably disjoint. 992 APInt LHSKnownZero, LHSKnownOne; 993 DAG.ComputeMaskedBits(N.getOperand(0), 994 APInt::getAllOnesValue(N.getOperand(0) 995 .getValueSizeInBits()), 996 LHSKnownZero, LHSKnownOne); 997 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 998 // If all of the bits are known zero on the LHS or RHS, the add won't 999 // carry. 1000 Base = N.getOperand(0); 1001 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1002 return true; 1003 } 1004 } 1005 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1006 // Loading from a constant address. Verify low two bits are clear. 1007 if ((CN->getZExtValue() & 3) == 0) { 1008 // If this address fits entirely in a 14-bit sext immediate field, codegen 1009 // this as "d, 0" 1010 short Imm; 1011 if (isIntS16Immediate(CN, Imm)) { 1012 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 1013 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1014 CN->getValueType(0)); 1015 return true; 1016 } 1017 1018 // Fold the low-part of 32-bit absolute addresses into addr mode. 1019 if (CN->getValueType(0) == MVT::i32 || 1020 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1021 int Addr = (int)CN->getZExtValue(); 1022 1023 // Otherwise, break this down into an LIS + disp. 1024 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 1025 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 1026 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1027 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); 1028 return true; 1029 } 1030 } 1031 } 1032 1033 Disp = DAG.getTargetConstant(0, getPointerTy()); 1034 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1035 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1036 else 1037 Base = N; 1038 return true; // [r+0] 1039} 1040 1041 1042/// getPreIndexedAddressParts - returns true by value, base pointer and 1043/// offset pointer and addressing mode by reference if the node's address 1044/// can be legally represented as pre-indexed load / store address. 1045bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1046 SDValue &Offset, 1047 ISD::MemIndexedMode &AM, 1048 SelectionDAG &DAG) const { 1049 // Disabled by default for now. 1050 if (!EnablePPCPreinc) return false; 1051 1052 SDValue Ptr; 1053 EVT VT; 1054 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1055 Ptr = LD->getBasePtr(); 1056 VT = LD->getMemoryVT(); 1057 1058 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1059 Ptr = ST->getBasePtr(); 1060 VT = ST->getMemoryVT(); 1061 } else 1062 return false; 1063 1064 // PowerPC doesn't have preinc load/store instructions for vectors. 1065 if (VT.isVector()) 1066 return false; 1067 1068 // TODO: Check reg+reg first. 1069 1070 // LDU/STU use reg+imm*4, others use reg+imm. 1071 if (VT != MVT::i64) { 1072 // reg + imm 1073 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1074 return false; 1075 } else { 1076 // reg + imm * 4. 1077 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1078 return false; 1079 } 1080 1081 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1082 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1083 // sext i32 to i64 when addr mode is r+i. 1084 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1085 LD->getExtensionType() == ISD::SEXTLOAD && 1086 isa<ConstantSDNode>(Offset)) 1087 return false; 1088 } 1089 1090 AM = ISD::PRE_INC; 1091 return true; 1092} 1093 1094//===----------------------------------------------------------------------===// 1095// LowerOperation implementation 1096//===----------------------------------------------------------------------===// 1097 1098/// GetLabelAccessInfo - Return true if we should reference labels using a 1099/// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. 1100static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, 1101 unsigned &LoOpFlags, const GlobalValue *GV = 0) { 1102 HiOpFlags = PPCII::MO_HA16; 1103 LoOpFlags = PPCII::MO_LO16; 1104 1105 // Don't use the pic base if not in PIC relocation model. Or if we are on a 1106 // non-darwin platform. We don't support PIC on other platforms yet. 1107 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ && 1108 TM.getSubtarget<PPCSubtarget>().isDarwin(); 1109 if (isPIC) { 1110 HiOpFlags |= PPCII::MO_PIC_FLAG; 1111 LoOpFlags |= PPCII::MO_PIC_FLAG; 1112 } 1113 1114 // If this is a reference to a global value that requires a non-lazy-ptr, make 1115 // sure that instruction lowering adds it. 1116 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) { 1117 HiOpFlags |= PPCII::MO_NLP_FLAG; 1118 LoOpFlags |= PPCII::MO_NLP_FLAG; 1119 1120 if (GV->hasHiddenVisibility()) { 1121 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1122 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1123 } 1124 } 1125 1126 return isPIC; 1127} 1128 1129static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, 1130 SelectionDAG &DAG) { 1131 EVT PtrVT = HiPart.getValueType(); 1132 SDValue Zero = DAG.getConstant(0, PtrVT); 1133 DebugLoc DL = HiPart.getDebugLoc(); 1134 1135 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero); 1136 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero); 1137 1138 // With PIC, the first instruction is actually "GR+hi(&G)". 1139 if (isPIC) 1140 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1141 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi); 1142 1143 // Generate non-pic code that has direct accesses to the constant pool. 1144 // The address of the global is just (hi(&g)+lo(&g)). 1145 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1146} 1147 1148SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1149 SelectionDAG &DAG) const { 1150 EVT PtrVT = Op.getValueType(); 1151 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1152 const Constant *C = CP->getConstVal(); 1153 1154 unsigned MOHiFlag, MOLoFlag; 1155 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1156 SDValue CPIHi = 1157 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag); 1158 SDValue CPILo = 1159 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag); 1160 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG); 1161} 1162 1163SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 1164 EVT PtrVT = Op.getValueType(); 1165 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1166 1167 unsigned MOHiFlag, MOLoFlag; 1168 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1169 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag); 1170 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag); 1171 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG); 1172} 1173 1174SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, 1175 SelectionDAG &DAG) const { 1176 EVT PtrVT = Op.getValueType(); 1177 1178 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1179 1180 unsigned MOHiFlag, MOLoFlag; 1181 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1182 SDValue TgtBAHi = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOHiFlag); 1183 SDValue TgtBALo = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOLoFlag); 1184 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG); 1185} 1186 1187SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1188 SelectionDAG &DAG) const { 1189 EVT PtrVT = Op.getValueType(); 1190 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1191 DebugLoc DL = GSDN->getDebugLoc(); 1192 const GlobalValue *GV = GSDN->getGlobal(); 1193 1194 // 64-bit SVR4 ABI code is always position-independent. 1195 // The actual address of the GlobalValue is stored in the TOC. 1196 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1197 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset()); 1198 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA, 1199 DAG.getRegister(PPC::X2, MVT::i64)); 1200 } 1201 1202 unsigned MOHiFlag, MOLoFlag; 1203 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV); 1204 1205 SDValue GAHi = 1206 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag); 1207 SDValue GALo = 1208 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag); 1209 1210 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG); 1211 1212 // If the global reference is actually to a non-lazy-pointer, we have to do an 1213 // extra load to get the address of the global. 1214 if (MOHiFlag & PPCII::MO_NLP_FLAG) 1215 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(), 1216 false, false, 0); 1217 return Ptr; 1218} 1219 1220SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1221 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1222 DebugLoc dl = Op.getDebugLoc(); 1223 1224 // If we're comparing for equality to zero, expose the fact that this is 1225 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1226 // fold the new nodes. 1227 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1228 if (C->isNullValue() && CC == ISD::SETEQ) { 1229 EVT VT = Op.getOperand(0).getValueType(); 1230 SDValue Zext = Op.getOperand(0); 1231 if (VT.bitsLT(MVT::i32)) { 1232 VT = MVT::i32; 1233 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1234 } 1235 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1236 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1237 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1238 DAG.getConstant(Log2b, MVT::i32)); 1239 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1240 } 1241 // Leave comparisons against 0 and -1 alone for now, since they're usually 1242 // optimized. FIXME: revisit this when we can custom lower all setcc 1243 // optimizations. 1244 if (C->isAllOnesValue() || C->isNullValue()) 1245 return SDValue(); 1246 } 1247 1248 // If we have an integer seteq/setne, turn it into a compare against zero 1249 // by xor'ing the rhs with the lhs, which is faster than setting a 1250 // condition register, reading it back out, and masking the correct bit. The 1251 // normal approach here uses sub to do this instead of xor. Using xor exposes 1252 // the result to other bit-twiddling opportunities. 1253 EVT LHSVT = Op.getOperand(0).getValueType(); 1254 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1255 EVT VT = Op.getValueType(); 1256 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1257 Op.getOperand(1)); 1258 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1259 } 1260 return SDValue(); 1261} 1262 1263SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1264 const PPCSubtarget &Subtarget) const { 1265 1266 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!"); 1267 return SDValue(); // Not reached 1268} 1269 1270SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, 1271 SelectionDAG &DAG) const { 1272 SDValue Chain = Op.getOperand(0); 1273 SDValue Trmp = Op.getOperand(1); // trampoline 1274 SDValue FPtr = Op.getOperand(2); // nested function 1275 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1276 DebugLoc dl = Op.getDebugLoc(); 1277 1278 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1279 bool isPPC64 = (PtrVT == MVT::i64); 1280 const Type *IntPtrTy = 1281 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType( 1282 *DAG.getContext()); 1283 1284 TargetLowering::ArgListTy Args; 1285 TargetLowering::ArgListEntry Entry; 1286 1287 Entry.Ty = IntPtrTy; 1288 Entry.Node = Trmp; Args.push_back(Entry); 1289 1290 // TrampSize == (isPPC64 ? 48 : 40); 1291 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1292 isPPC64 ? MVT::i64 : MVT::i32); 1293 Args.push_back(Entry); 1294 1295 Entry.Node = FPtr; Args.push_back(Entry); 1296 Entry.Node = Nest; Args.push_back(Entry); 1297 1298 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1299 std::pair<SDValue, SDValue> CallResult = 1300 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()), 1301 false, false, false, false, 0, CallingConv::C, false, 1302 /*isReturnValueUsed=*/true, 1303 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1304 Args, DAG, dl); 1305 1306 SDValue Ops[] = 1307 { CallResult.first, CallResult.second }; 1308 1309 return DAG.getMergeValues(Ops, 2, dl); 1310} 1311 1312SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1313 const PPCSubtarget &Subtarget) const { 1314 MachineFunction &MF = DAG.getMachineFunction(); 1315 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1316 1317 DebugLoc dl = Op.getDebugLoc(); 1318 1319 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1320 // vastart just stores the address of the VarArgsFrameIndex slot into the 1321 // memory location argument. 1322 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1323 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1324 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1325 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 1326 MachinePointerInfo(SV), 1327 false, false, 0); 1328 } 1329 1330 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1331 // We suppose the given va_list is already allocated. 1332 // 1333 // typedef struct { 1334 // char gpr; /* index into the array of 8 GPRs 1335 // * stored in the register save area 1336 // * gpr=0 corresponds to r3, 1337 // * gpr=1 to r4, etc. 1338 // */ 1339 // char fpr; /* index into the array of 8 FPRs 1340 // * stored in the register save area 1341 // * fpr=0 corresponds to f1, 1342 // * fpr=1 to f2, etc. 1343 // */ 1344 // char *overflow_arg_area; 1345 // /* location on stack that holds 1346 // * the next overflow argument 1347 // */ 1348 // char *reg_save_area; 1349 // /* where r3:r10 and f1:f8 (if saved) 1350 // * are stored 1351 // */ 1352 // } va_list[1]; 1353 1354 1355 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32); 1356 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32); 1357 1358 1359 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1360 1361 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), 1362 PtrVT); 1363 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1364 PtrVT); 1365 1366 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1367 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1368 1369 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1370 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1371 1372 uint64_t FPROffset = 1; 1373 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1374 1375 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1376 1377 // Store first byte : number of int regs 1378 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1379 Op.getOperand(1), 1380 MachinePointerInfo(SV), 1381 MVT::i8, false, false, 0); 1382 uint64_t nextOffset = FPROffset; 1383 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1384 ConstFPROffset); 1385 1386 // Store second byte : number of float regs 1387 SDValue secondStore = 1388 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, 1389 MachinePointerInfo(SV, nextOffset), MVT::i8, 1390 false, false, 0); 1391 nextOffset += StackOffset; 1392 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1393 1394 // Store second word : arguments given on stack 1395 SDValue thirdStore = 1396 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, 1397 MachinePointerInfo(SV, nextOffset), 1398 false, false, 0); 1399 nextOffset += FrameOffset; 1400 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1401 1402 // Store third word : arguments given in registers 1403 return DAG.getStore(thirdStore, dl, FR, nextPtr, 1404 MachinePointerInfo(SV, nextOffset), 1405 false, false, 0); 1406 1407} 1408 1409#include "PPCGenCallingConv.inc" 1410 1411static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 1412 CCValAssign::LocInfo &LocInfo, 1413 ISD::ArgFlagsTy &ArgFlags, 1414 CCState &State) { 1415 return true; 1416} 1417 1418static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 1419 MVT &LocVT, 1420 CCValAssign::LocInfo &LocInfo, 1421 ISD::ArgFlagsTy &ArgFlags, 1422 CCState &State) { 1423 static const unsigned ArgRegs[] = { 1424 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1425 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1426 }; 1427 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1428 1429 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1430 1431 // Skip one register if the first unallocated register has an even register 1432 // number and there are still argument registers available which have not been 1433 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1434 // need to skip a register if RegNum is odd. 1435 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1436 State.AllocateReg(ArgRegs[RegNum]); 1437 } 1438 1439 // Always return false here, as this function only makes sure that the first 1440 // unallocated register has an odd register number and does not actually 1441 // allocate a register for the current argument. 1442 return false; 1443} 1444 1445static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 1446 MVT &LocVT, 1447 CCValAssign::LocInfo &LocInfo, 1448 ISD::ArgFlagsTy &ArgFlags, 1449 CCState &State) { 1450 static const unsigned ArgRegs[] = { 1451 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1452 PPC::F8 1453 }; 1454 1455 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1456 1457 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1458 1459 // If there is only one Floating-point register left we need to put both f64 1460 // values of a split ppc_fp128 value on the stack. 1461 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1462 State.AllocateReg(ArgRegs[RegNum]); 1463 } 1464 1465 // Always return false here, as this function only makes sure that the two f64 1466 // values a ppc_fp128 value is split into are both passed in registers or both 1467 // passed on the stack and does not actually allocate a register for the 1468 // current argument. 1469 return false; 1470} 1471 1472/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1473/// on Darwin. 1474static const unsigned *GetFPR() { 1475 static const unsigned FPR[] = { 1476 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1477 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1478 }; 1479 1480 return FPR; 1481} 1482 1483/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1484/// the stack. 1485static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1486 unsigned PtrByteSize) { 1487 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1488 if (Flags.isByVal()) 1489 ArgSize = Flags.getByValSize(); 1490 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1491 1492 return ArgSize; 1493} 1494 1495SDValue 1496PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1497 CallingConv::ID CallConv, bool isVarArg, 1498 const SmallVectorImpl<ISD::InputArg> 1499 &Ins, 1500 DebugLoc dl, SelectionDAG &DAG, 1501 SmallVectorImpl<SDValue> &InVals) 1502 const { 1503 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 1504 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins, 1505 dl, DAG, InVals); 1506 } else { 1507 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1508 dl, DAG, InVals); 1509 } 1510} 1511 1512SDValue 1513PPCTargetLowering::LowerFormalArguments_SVR4( 1514 SDValue Chain, 1515 CallingConv::ID CallConv, bool isVarArg, 1516 const SmallVectorImpl<ISD::InputArg> 1517 &Ins, 1518 DebugLoc dl, SelectionDAG &DAG, 1519 SmallVectorImpl<SDValue> &InVals) const { 1520 1521 // 32-bit SVR4 ABI Stack Frame Layout: 1522 // +-----------------------------------+ 1523 // +--> | Back chain | 1524 // | +-----------------------------------+ 1525 // | | Floating-point register save area | 1526 // | +-----------------------------------+ 1527 // | | General register save area | 1528 // | +-----------------------------------+ 1529 // | | CR save word | 1530 // | +-----------------------------------+ 1531 // | | VRSAVE save word | 1532 // | +-----------------------------------+ 1533 // | | Alignment padding | 1534 // | +-----------------------------------+ 1535 // | | Vector register save area | 1536 // | +-----------------------------------+ 1537 // | | Local variable space | 1538 // | +-----------------------------------+ 1539 // | | Parameter list area | 1540 // | +-----------------------------------+ 1541 // | | LR save word | 1542 // | +-----------------------------------+ 1543 // SP--> +--- | Back chain | 1544 // +-----------------------------------+ 1545 // 1546 // Specifications: 1547 // System V Application Binary Interface PowerPC Processor Supplement 1548 // AltiVec Technology Programming Interface Manual 1549 1550 MachineFunction &MF = DAG.getMachineFunction(); 1551 MachineFrameInfo *MFI = MF.getFrameInfo(); 1552 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1553 1554 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1555 // Potential tail calls could cause overwriting of argument stack slots. 1556 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1557 unsigned PtrByteSize = 4; 1558 1559 // Assign locations to all of the incoming arguments. 1560 SmallVector<CCValAssign, 16> ArgLocs; 1561 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 1562 *DAG.getContext()); 1563 1564 // Reserve space for the linkage area on the stack. 1565 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 1566 1567 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4); 1568 1569 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1570 CCValAssign &VA = ArgLocs[i]; 1571 1572 // Arguments stored in registers. 1573 if (VA.isRegLoc()) { 1574 TargetRegisterClass *RC; 1575 EVT ValVT = VA.getValVT(); 1576 1577 switch (ValVT.getSimpleVT().SimpleTy) { 1578 default: 1579 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1580 case MVT::i32: 1581 RC = PPC::GPRCRegisterClass; 1582 break; 1583 case MVT::f32: 1584 RC = PPC::F4RCRegisterClass; 1585 break; 1586 case MVT::f64: 1587 RC = PPC::F8RCRegisterClass; 1588 break; 1589 case MVT::v16i8: 1590 case MVT::v8i16: 1591 case MVT::v4i32: 1592 case MVT::v4f32: 1593 RC = PPC::VRRCRegisterClass; 1594 break; 1595 } 1596 1597 // Transform the arguments stored in physical registers into virtual ones. 1598 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1599 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 1600 1601 InVals.push_back(ArgValue); 1602 } else { 1603 // Argument stored in memory. 1604 assert(VA.isMemLoc()); 1605 1606 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1607 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1608 isImmutable); 1609 1610 // Create load nodes to retrieve arguments from the stack. 1611 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1612 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1613 MachinePointerInfo(), 1614 false, false, 0)); 1615 } 1616 } 1617 1618 // Assign locations to all of the incoming aggregate by value arguments. 1619 // Aggregates passed by value are stored in the local variable space of the 1620 // caller's stack frame, right above the parameter list area. 1621 SmallVector<CCValAssign, 16> ByValArgLocs; 1622 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), 1623 ByValArgLocs, *DAG.getContext()); 1624 1625 // Reserve stack space for the allocations in CCInfo. 1626 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 1627 1628 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal); 1629 1630 // Area that is at least reserved in the caller of this function. 1631 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 1632 1633 // Set the size that is at least reserved in caller of this function. Tail 1634 // call optimized function's reserved stack space needs to be aligned so that 1635 // taking the difference between two stack areas will result in an aligned 1636 // stack. 1637 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1638 1639 MinReservedArea = 1640 std::max(MinReservedArea, 1641 PPCFrameLowering::getMinCallFrameSize(false, false)); 1642 1643 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 1644 getStackAlignment(); 1645 unsigned AlignMask = TargetAlign-1; 1646 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1647 1648 FI->setMinReservedArea(MinReservedArea); 1649 1650 SmallVector<SDValue, 8> MemOps; 1651 1652 // If the function takes variable number of arguments, make a frame index for 1653 // the start of the first vararg value... for expansion of llvm.va_start. 1654 if (isVarArg) { 1655 static const unsigned GPArgRegs[] = { 1656 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1657 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1658 }; 1659 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 1660 1661 static const unsigned FPArgRegs[] = { 1662 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1663 PPC::F8 1664 }; 1665 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 1666 1667 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs, 1668 NumGPArgRegs)); 1669 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs, 1670 NumFPArgRegs)); 1671 1672 // Make room for NumGPArgRegs and NumFPArgRegs. 1673 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 1674 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 1675 1676 FuncInfo->setVarArgsStackOffset( 1677 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1678 CCInfo.getNextStackOffset(), true)); 1679 1680 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false)); 1681 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1682 1683 // The fixed integer arguments of a variadic function are stored to the 1684 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing 1685 // the result of va_next. 1686 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) { 1687 // Get an existing live-in vreg, or add a new one. 1688 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); 1689 if (!VReg) 1690 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 1691 1692 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1693 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1694 MachinePointerInfo(), false, false, 0); 1695 MemOps.push_back(Store); 1696 // Increment the address by four for the next argument to store 1697 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1698 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1699 } 1700 1701 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 1702 // is set. 1703 // The double arguments are stored to the VarArgsFrameIndex 1704 // on the stack. 1705 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) { 1706 // Get an existing live-in vreg, or add a new one. 1707 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); 1708 if (!VReg) 1709 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 1710 1711 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 1712 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1713 MachinePointerInfo(), false, false, 0); 1714 MemOps.push_back(Store); 1715 // Increment the address by eight for the next argument to store 1716 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 1717 PtrVT); 1718 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1719 } 1720 } 1721 1722 if (!MemOps.empty()) 1723 Chain = DAG.getNode(ISD::TokenFactor, dl, 1724 MVT::Other, &MemOps[0], MemOps.size()); 1725 1726 return Chain; 1727} 1728 1729SDValue 1730PPCTargetLowering::LowerFormalArguments_Darwin( 1731 SDValue Chain, 1732 CallingConv::ID CallConv, bool isVarArg, 1733 const SmallVectorImpl<ISD::InputArg> 1734 &Ins, 1735 DebugLoc dl, SelectionDAG &DAG, 1736 SmallVectorImpl<SDValue> &InVals) const { 1737 // TODO: add description of PPC stack frame format, or at least some docs. 1738 // 1739 MachineFunction &MF = DAG.getMachineFunction(); 1740 MachineFrameInfo *MFI = MF.getFrameInfo(); 1741 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1742 1743 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1744 bool isPPC64 = PtrVT == MVT::i64; 1745 // Potential tail calls could cause overwriting of argument stack slots. 1746 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1747 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1748 1749 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 1750 // Area that is at least reserved in caller of this function. 1751 unsigned MinReservedArea = ArgOffset; 1752 1753 static const unsigned GPR_32[] = { // 32-bit registers. 1754 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1755 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1756 }; 1757 static const unsigned GPR_64[] = { // 64-bit registers. 1758 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1759 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1760 }; 1761 1762 static const unsigned *FPR = GetFPR(); 1763 1764 static const unsigned VR[] = { 1765 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1766 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1767 }; 1768 1769 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1770 const unsigned Num_FPR_Regs = 13; 1771 const unsigned Num_VR_Regs = array_lengthof( VR); 1772 1773 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1774 1775 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1776 1777 // In 32-bit non-varargs functions, the stack space for vectors is after the 1778 // stack space for non-vectors. We do not use this space unless we have 1779 // too many vectors to fit in registers, something that only occurs in 1780 // constructed examples:), but we have to walk the arglist to figure 1781 // that out...for the pathological case, compute VecArgOffset as the 1782 // start of the vector parameter area. Computing VecArgOffset is the 1783 // entire point of the following loop. 1784 unsigned VecArgOffset = ArgOffset; 1785 if (!isVarArg && !isPPC64) { 1786 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 1787 ++ArgNo) { 1788 EVT ObjectVT = Ins[ArgNo].VT; 1789 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1790 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1791 1792 if (Flags.isByVal()) { 1793 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 1794 ObjSize = Flags.getByValSize(); 1795 unsigned ArgSize = 1796 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1797 VecArgOffset += ArgSize; 1798 continue; 1799 } 1800 1801 switch(ObjectVT.getSimpleVT().SimpleTy) { 1802 default: llvm_unreachable("Unhandled argument type!"); 1803 case MVT::i32: 1804 case MVT::f32: 1805 VecArgOffset += isPPC64 ? 8 : 4; 1806 break; 1807 case MVT::i64: // PPC64 1808 case MVT::f64: 1809 VecArgOffset += 8; 1810 break; 1811 case MVT::v4f32: 1812 case MVT::v4i32: 1813 case MVT::v8i16: 1814 case MVT::v16i8: 1815 // Nothing to do, we're only looking at Nonvector args here. 1816 break; 1817 } 1818 } 1819 } 1820 // We've found where the vector parameter area in memory is. Skip the 1821 // first 12 parameters; these don't use that memory. 1822 VecArgOffset = ((VecArgOffset+15)/16)*16; 1823 VecArgOffset += 12*16; 1824 1825 // Add DAG nodes to load the arguments or copy them out of registers. On 1826 // entry to a function on PPC, the arguments start after the linkage area, 1827 // although the first ones are often in registers. 1828 1829 SmallVector<SDValue, 8> MemOps; 1830 unsigned nAltivecParamsAtEnd = 0; 1831 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { 1832 SDValue ArgVal; 1833 bool needsLoad = false; 1834 EVT ObjectVT = Ins[ArgNo].VT; 1835 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1836 unsigned ArgSize = ObjSize; 1837 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1838 1839 unsigned CurArgOffset = ArgOffset; 1840 1841 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 1842 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 1843 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 1844 if (isVarArg || isPPC64) { 1845 MinReservedArea = ((MinReservedArea+15)/16)*16; 1846 MinReservedArea += CalculateStackSlotSize(ObjectVT, 1847 Flags, 1848 PtrByteSize); 1849 } else nAltivecParamsAtEnd++; 1850 } else 1851 // Calculate min reserved area. 1852 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 1853 Flags, 1854 PtrByteSize); 1855 1856 // FIXME the codegen can be much improved in some cases. 1857 // We do not have to keep everything in memory. 1858 if (Flags.isByVal()) { 1859 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 1860 ObjSize = Flags.getByValSize(); 1861 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1862 // Objects of size 1 and 2 are right justified, everything else is 1863 // left justified. This means the memory address is adjusted forwards. 1864 if (ObjSize==1 || ObjSize==2) { 1865 CurArgOffset = CurArgOffset + (4 - ObjSize); 1866 } 1867 // The value of the object is its address. 1868 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 1869 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1870 InVals.push_back(FIN); 1871 if (ObjSize==1 || ObjSize==2) { 1872 if (GPR_idx != Num_GPR_Regs) { 1873 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1874 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1875 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 1876 MachinePointerInfo(), 1877 ObjSize==1 ? MVT::i8 : MVT::i16, 1878 false, false, 0); 1879 MemOps.push_back(Store); 1880 ++GPR_idx; 1881 } 1882 1883 ArgOffset += PtrByteSize; 1884 1885 continue; 1886 } 1887 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 1888 // Store whatever pieces of the object are in registers 1889 // to memory. ArgVal will be address of the beginning of 1890 // the object. 1891 if (GPR_idx != Num_GPR_Regs) { 1892 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1893 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 1894 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1895 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1896 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1897 MachinePointerInfo(), 1898 false, false, 0); 1899 MemOps.push_back(Store); 1900 ++GPR_idx; 1901 ArgOffset += PtrByteSize; 1902 } else { 1903 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 1904 break; 1905 } 1906 } 1907 continue; 1908 } 1909 1910 switch (ObjectVT.getSimpleVT().SimpleTy) { 1911 default: llvm_unreachable("Unhandled argument type!"); 1912 case MVT::i32: 1913 if (!isPPC64) { 1914 if (GPR_idx != Num_GPR_Regs) { 1915 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1916 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 1917 ++GPR_idx; 1918 } else { 1919 needsLoad = true; 1920 ArgSize = PtrByteSize; 1921 } 1922 // All int arguments reserve stack space in the Darwin ABI. 1923 ArgOffset += PtrByteSize; 1924 break; 1925 } 1926 // FALLTHROUGH 1927 case MVT::i64: // PPC64 1928 if (GPR_idx != Num_GPR_Regs) { 1929 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 1930 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1931 1932 if (ObjectVT == MVT::i32) { 1933 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 1934 // value to MVT::i64 and then truncate to the correct register size. 1935 if (Flags.isSExt()) 1936 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 1937 DAG.getValueType(ObjectVT)); 1938 else if (Flags.isZExt()) 1939 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 1940 DAG.getValueType(ObjectVT)); 1941 1942 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 1943 } 1944 1945 ++GPR_idx; 1946 } else { 1947 needsLoad = true; 1948 ArgSize = PtrByteSize; 1949 } 1950 // All int arguments reserve stack space in the Darwin ABI. 1951 ArgOffset += 8; 1952 break; 1953 1954 case MVT::f32: 1955 case MVT::f64: 1956 // Every 4 bytes of argument space consumes one of the GPRs available for 1957 // argument passing. 1958 if (GPR_idx != Num_GPR_Regs) { 1959 ++GPR_idx; 1960 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1961 ++GPR_idx; 1962 } 1963 if (FPR_idx != Num_FPR_Regs) { 1964 unsigned VReg; 1965 1966 if (ObjectVT == MVT::f32) 1967 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 1968 else 1969 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 1970 1971 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 1972 ++FPR_idx; 1973 } else { 1974 needsLoad = true; 1975 } 1976 1977 // All FP arguments reserve stack space in the Darwin ABI. 1978 ArgOffset += isPPC64 ? 8 : ObjSize; 1979 break; 1980 case MVT::v4f32: 1981 case MVT::v4i32: 1982 case MVT::v8i16: 1983 case MVT::v16i8: 1984 // Note that vector arguments in registers don't reserve stack space, 1985 // except in varargs functions. 1986 if (VR_idx != Num_VR_Regs) { 1987 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 1988 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 1989 if (isVarArg) { 1990 while ((ArgOffset % 16) != 0) { 1991 ArgOffset += PtrByteSize; 1992 if (GPR_idx != Num_GPR_Regs) 1993 GPR_idx++; 1994 } 1995 ArgOffset += 16; 1996 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 1997 } 1998 ++VR_idx; 1999 } else { 2000 if (!isVarArg && !isPPC64) { 2001 // Vectors go after all the nonvectors. 2002 CurArgOffset = VecArgOffset; 2003 VecArgOffset += 16; 2004 } else { 2005 // Vectors are aligned. 2006 ArgOffset = ((ArgOffset+15)/16)*16; 2007 CurArgOffset = ArgOffset; 2008 ArgOffset += 16; 2009 } 2010 needsLoad = true; 2011 } 2012 break; 2013 } 2014 2015 // We need to load the argument to a virtual register if we determined above 2016 // that we ran out of physical registers of the appropriate type. 2017 if (needsLoad) { 2018 int FI = MFI->CreateFixedObject(ObjSize, 2019 CurArgOffset + (ArgSize - ObjSize), 2020 isImmutable); 2021 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2022 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2023 false, false, 0); 2024 } 2025 2026 InVals.push_back(ArgVal); 2027 } 2028 2029 // Set the size that is at least reserved in caller of this function. Tail 2030 // call optimized function's reserved stack space needs to be aligned so that 2031 // taking the difference between two stack areas will result in an aligned 2032 // stack. 2033 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2034 // Add the Altivec parameters at the end, if needed. 2035 if (nAltivecParamsAtEnd) { 2036 MinReservedArea = ((MinReservedArea+15)/16)*16; 2037 MinReservedArea += 16*nAltivecParamsAtEnd; 2038 } 2039 MinReservedArea = 2040 std::max(MinReservedArea, 2041 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2042 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2043 getStackAlignment(); 2044 unsigned AlignMask = TargetAlign-1; 2045 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2046 FI->setMinReservedArea(MinReservedArea); 2047 2048 // If the function takes variable number of arguments, make a frame index for 2049 // the start of the first vararg value... for expansion of llvm.va_start. 2050 if (isVarArg) { 2051 int Depth = ArgOffset; 2052 2053 FuncInfo->setVarArgsFrameIndex( 2054 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2055 Depth, true)); 2056 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2057 2058 // If this function is vararg, store any remaining integer argument regs 2059 // to their spots on the stack so that they may be loaded by deferencing the 2060 // result of va_next. 2061 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2062 unsigned VReg; 2063 2064 if (isPPC64) 2065 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2066 else 2067 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2068 2069 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2070 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2071 MachinePointerInfo(), false, false, 0); 2072 MemOps.push_back(Store); 2073 // Increment the address by four for the next argument to store 2074 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2075 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2076 } 2077 } 2078 2079 if (!MemOps.empty()) 2080 Chain = DAG.getNode(ISD::TokenFactor, dl, 2081 MVT::Other, &MemOps[0], MemOps.size()); 2082 2083 return Chain; 2084} 2085 2086/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus 2087/// linkage area for the Darwin ABI. 2088static unsigned 2089CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2090 bool isPPC64, 2091 bool isVarArg, 2092 unsigned CC, 2093 const SmallVectorImpl<ISD::OutputArg> 2094 &Outs, 2095 const SmallVectorImpl<SDValue> &OutVals, 2096 unsigned &nAltivecParamsAtEnd) { 2097 // Count how many bytes are to be pushed on the stack, including the linkage 2098 // area, and parameter passing area. We start with 24/48 bytes, which is 2099 // prereserved space for [SP][CR][LR][3 x unused]. 2100 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true); 2101 unsigned NumOps = Outs.size(); 2102 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2103 2104 // Add up all the space actually used. 2105 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2106 // they all go in registers, but we must reserve stack space for them for 2107 // possible use by the caller. In varargs or 64-bit calls, parameters are 2108 // assigned stack space in order, with padding so Altivec parameters are 2109 // 16-byte aligned. 2110 nAltivecParamsAtEnd = 0; 2111 for (unsigned i = 0; i != NumOps; ++i) { 2112 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2113 EVT ArgVT = Outs[i].VT; 2114 // Varargs Altivec parameters are padded to a 16 byte boundary. 2115 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2116 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2117 if (!isVarArg && !isPPC64) { 2118 // Non-varargs Altivec parameters go after all the non-Altivec 2119 // parameters; handle those later so we know how much padding we need. 2120 nAltivecParamsAtEnd++; 2121 continue; 2122 } 2123 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2124 NumBytes = ((NumBytes+15)/16)*16; 2125 } 2126 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2127 } 2128 2129 // Allow for Altivec parameters at the end, if needed. 2130 if (nAltivecParamsAtEnd) { 2131 NumBytes = ((NumBytes+15)/16)*16; 2132 NumBytes += 16*nAltivecParamsAtEnd; 2133 } 2134 2135 // The prolog code of the callee may store up to 8 GPR argument registers to 2136 // the stack, allowing va_start to index over them in memory if its varargs. 2137 // Because we cannot tell if this is needed on the caller side, we have to 2138 // conservatively assume that it is needed. As such, make sure we have at 2139 // least enough stack space for the caller to store the 8 GPRs. 2140 NumBytes = std::max(NumBytes, 2141 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2142 2143 // Tail call needs the stack to be aligned. 2144 if (CC==CallingConv::Fast && GuaranteedTailCallOpt) { 2145 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2146 getStackAlignment(); 2147 unsigned AlignMask = TargetAlign-1; 2148 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2149 } 2150 2151 return NumBytes; 2152} 2153 2154/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2155/// adjusted to accommodate the arguments for the tailcall. 2156static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2157 unsigned ParamSize) { 2158 2159 if (!isTailCall) return 0; 2160 2161 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2162 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2163 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2164 // Remember only if the new adjustement is bigger. 2165 if (SPDiff < FI->getTailCallSPDelta()) 2166 FI->setTailCallSPDelta(SPDiff); 2167 2168 return SPDiff; 2169} 2170 2171/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2172/// for tail call optimization. Targets which want to do tail call 2173/// optimization should implement this function. 2174bool 2175PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2176 CallingConv::ID CalleeCC, 2177 bool isVarArg, 2178 const SmallVectorImpl<ISD::InputArg> &Ins, 2179 SelectionDAG& DAG) const { 2180 if (!GuaranteedTailCallOpt) 2181 return false; 2182 2183 // Variable argument functions are not supported. 2184 if (isVarArg) 2185 return false; 2186 2187 MachineFunction &MF = DAG.getMachineFunction(); 2188 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2189 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2190 // Functions containing by val parameters are not supported. 2191 for (unsigned i = 0; i != Ins.size(); i++) { 2192 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2193 if (Flags.isByVal()) return false; 2194 } 2195 2196 // Non PIC/GOT tail calls are supported. 2197 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2198 return true; 2199 2200 // At the moment we can only do local tail calls (in same module, hidden 2201 // or protected) if we are generating PIC. 2202 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2203 return G->getGlobal()->hasHiddenVisibility() 2204 || G->getGlobal()->hasProtectedVisibility(); 2205 } 2206 2207 return false; 2208} 2209 2210/// isCallCompatibleAddress - Return the immediate to use if the specified 2211/// 32-bit value is representable in the immediate field of a BxA instruction. 2212static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2213 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2214 if (!C) return 0; 2215 2216 int Addr = C->getZExtValue(); 2217 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2218 (Addr << 6 >> 6) != Addr) 2219 return 0; // Top 6 bits have to be sext of immediate. 2220 2221 return DAG.getConstant((int)C->getZExtValue() >> 2, 2222 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2223} 2224 2225namespace { 2226 2227struct TailCallArgumentInfo { 2228 SDValue Arg; 2229 SDValue FrameIdxOp; 2230 int FrameIdx; 2231 2232 TailCallArgumentInfo() : FrameIdx(0) {} 2233}; 2234 2235} 2236 2237/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2238static void 2239StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2240 SDValue Chain, 2241 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2242 SmallVector<SDValue, 8> &MemOpChains, 2243 DebugLoc dl) { 2244 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2245 SDValue Arg = TailCallArgs[i].Arg; 2246 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2247 int FI = TailCallArgs[i].FrameIdx; 2248 // Store relative to framepointer. 2249 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2250 MachinePointerInfo::getFixedStack(FI), 2251 false, false, 0)); 2252 } 2253} 2254 2255/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2256/// the appropriate stack slot for the tail call optimized function call. 2257static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2258 MachineFunction &MF, 2259 SDValue Chain, 2260 SDValue OldRetAddr, 2261 SDValue OldFP, 2262 int SPDiff, 2263 bool isPPC64, 2264 bool isDarwinABI, 2265 DebugLoc dl) { 2266 if (SPDiff) { 2267 // Calculate the new stack slot for the return address. 2268 int SlotSize = isPPC64 ? 8 : 4; 2269 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64, 2270 isDarwinABI); 2271 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2272 NewRetAddrLoc, true); 2273 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2274 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2275 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2276 MachinePointerInfo::getFixedStack(NewRetAddr), 2277 false, false, 0); 2278 2279 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2280 // slot as the FP is never overwritten. 2281 if (isDarwinABI) { 2282 int NewFPLoc = 2283 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 2284 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 2285 true); 2286 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2287 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2288 MachinePointerInfo::getFixedStack(NewFPIdx), 2289 false, false, 0); 2290 } 2291 } 2292 return Chain; 2293} 2294 2295/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2296/// the position of the argument. 2297static void 2298CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2299 SDValue Arg, int SPDiff, unsigned ArgOffset, 2300 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2301 int Offset = ArgOffset + SPDiff; 2302 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2303 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2304 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2305 SDValue FIN = DAG.getFrameIndex(FI, VT); 2306 TailCallArgumentInfo Info; 2307 Info.Arg = Arg; 2308 Info.FrameIdxOp = FIN; 2309 Info.FrameIdx = FI; 2310 TailCallArguments.push_back(Info); 2311} 2312 2313/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2314/// stack slot. Returns the chain as result and the loaded frame pointers in 2315/// LROpOut/FPOpout. Used when tail calling. 2316SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2317 int SPDiff, 2318 SDValue Chain, 2319 SDValue &LROpOut, 2320 SDValue &FPOpOut, 2321 bool isDarwinABI, 2322 DebugLoc dl) const { 2323 if (SPDiff) { 2324 // Load the LR and FP stack slot for later adjusting. 2325 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2326 LROpOut = getReturnAddrFrameIndex(DAG); 2327 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(), 2328 false, false, 0); 2329 Chain = SDValue(LROpOut.getNode(), 1); 2330 2331 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 2332 // slot as the FP is never overwritten. 2333 if (isDarwinABI) { 2334 FPOpOut = getFramePointerFrameIndex(DAG); 2335 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(), 2336 false, false, 0); 2337 Chain = SDValue(FPOpOut.getNode(), 1); 2338 } 2339 } 2340 return Chain; 2341} 2342 2343/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 2344/// by "Src" to address "Dst" of size "Size". Alignment information is 2345/// specified by the specific parameter attribute. The copy will be passed as 2346/// a byval function parameter. 2347/// Sometimes what we are copying is the end of a larger object, the part that 2348/// does not fit in registers. 2349static SDValue 2350CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 2351 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 2352 DebugLoc dl) { 2353 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 2354 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 2355 false, false, MachinePointerInfo(0), 2356 MachinePointerInfo(0)); 2357} 2358 2359/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 2360/// tail calls. 2361static void 2362LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 2363 SDValue Arg, SDValue PtrOff, int SPDiff, 2364 unsigned ArgOffset, bool isPPC64, bool isTailCall, 2365 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 2366 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments, 2367 DebugLoc dl) { 2368 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2369 if (!isTailCall) { 2370 if (isVector) { 2371 SDValue StackPtr; 2372 if (isPPC64) 2373 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2374 else 2375 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2376 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 2377 DAG.getConstant(ArgOffset, PtrVT)); 2378 } 2379 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2380 MachinePointerInfo(), false, false, 0)); 2381 // Calculate and remember argument location. 2382 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 2383 TailCallArguments); 2384} 2385 2386static 2387void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 2388 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 2389 SDValue LROp, SDValue FPOp, bool isDarwinABI, 2390 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 2391 MachineFunction &MF = DAG.getMachineFunction(); 2392 2393 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 2394 // might overwrite each other in case of tail call optimization. 2395 SmallVector<SDValue, 8> MemOpChains2; 2396 // Do not flag preceding copytoreg stuff together with the following stuff. 2397 InFlag = SDValue(); 2398 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 2399 MemOpChains2, dl); 2400 if (!MemOpChains2.empty()) 2401 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2402 &MemOpChains2[0], MemOpChains2.size()); 2403 2404 // Store the return address to the appropriate stack slot. 2405 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 2406 isPPC64, isDarwinABI, dl); 2407 2408 // Emit callseq_end just before tailcall node. 2409 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2410 DAG.getIntPtrConstant(0, true), InFlag); 2411 InFlag = Chain.getValue(1); 2412} 2413 2414static 2415unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 2416 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, 2417 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 2418 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 2419 const PPCSubtarget &PPCSubTarget) { 2420 2421 bool isPPC64 = PPCSubTarget.isPPC64(); 2422 bool isSVR4ABI = PPCSubTarget.isSVR4ABI(); 2423 2424 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2425 NodeTys.push_back(MVT::Other); // Returns a chain 2426 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use. 2427 2428 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin; 2429 2430 bool needIndirectCall = true; 2431 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { 2432 // If this is an absolute destination address, use the munged value. 2433 Callee = SDValue(Dest, 0); 2434 needIndirectCall = false; 2435 } 2436 2437 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2438 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201 2439 // Use indirect calls for ALL functions calls in JIT mode, since the 2440 // far-call stubs may be outside relocation limits for a BL instruction. 2441 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) { 2442 unsigned OpFlags = 0; 2443 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 2444 (!PPCSubTarget.getTargetTriple().isMacOSX() || 2445 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) && 2446 (G->getGlobal()->isDeclaration() || 2447 G->getGlobal()->isWeakForLinker())) { 2448 // PC-relative references to external symbols should go through $stub, 2449 // unless we're building with the leopard linker or later, which 2450 // automatically synthesizes these stubs. 2451 OpFlags = PPCII::MO_DARWIN_STUB; 2452 } 2453 2454 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, 2455 // every direct call is) turn it into a TargetGlobalAddress / 2456 // TargetExternalSymbol node so that legalize doesn't hack it. 2457 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2458 Callee.getValueType(), 2459 0, OpFlags); 2460 needIndirectCall = false; 2461 } 2462 } 2463 2464 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2465 unsigned char OpFlags = 0; 2466 2467 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 2468 (!PPCSubTarget.getTargetTriple().isMacOSX() || 2469 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) { 2470 // PC-relative references to external symbols should go through $stub, 2471 // unless we're building with the leopard linker or later, which 2472 // automatically synthesizes these stubs. 2473 OpFlags = PPCII::MO_DARWIN_STUB; 2474 } 2475 2476 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(), 2477 OpFlags); 2478 needIndirectCall = false; 2479 } 2480 2481 if (needIndirectCall) { 2482 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 2483 // to do the call, we can't use PPCISD::CALL. 2484 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 2485 2486 if (isSVR4ABI && isPPC64) { 2487 // Function pointers in the 64-bit SVR4 ABI do not point to the function 2488 // entry point, but to the function descriptor (the function entry point 2489 // address is part of the function descriptor though). 2490 // The function descriptor is a three doubleword structure with the 2491 // following fields: function entry point, TOC base address and 2492 // environment pointer. 2493 // Thus for a call through a function pointer, the following actions need 2494 // to be performed: 2495 // 1. Save the TOC of the caller in the TOC save area of its stack 2496 // frame (this is done in LowerCall_Darwin()). 2497 // 2. Load the address of the function entry point from the function 2498 // descriptor. 2499 // 3. Load the TOC of the callee from the function descriptor into r2. 2500 // 4. Load the environment pointer from the function descriptor into 2501 // r11. 2502 // 5. Branch to the function entry point address. 2503 // 6. On return of the callee, the TOC of the caller needs to be 2504 // restored (this is done in FinishCall()). 2505 // 2506 // All those operations are flagged together to ensure that no other 2507 // operations can be scheduled in between. E.g. without flagging the 2508 // operations together, a TOC access in the caller could be scheduled 2509 // between the load of the callee TOC and the branch to the callee, which 2510 // results in the TOC access going through the TOC of the callee instead 2511 // of going through the TOC of the caller, which leads to incorrect code. 2512 2513 // Load the address of the function entry point from the function 2514 // descriptor. 2515 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue); 2516 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 2517 InFlag.getNode() ? 3 : 2); 2518 Chain = LoadFuncPtr.getValue(1); 2519 InFlag = LoadFuncPtr.getValue(2); 2520 2521 // Load environment pointer into r11. 2522 // Offset of the environment pointer within the function descriptor. 2523 SDValue PtrOff = DAG.getIntPtrConstant(16); 2524 2525 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 2526 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 2527 InFlag); 2528 Chain = LoadEnvPtr.getValue(1); 2529 InFlag = LoadEnvPtr.getValue(2); 2530 2531 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 2532 InFlag); 2533 Chain = EnvVal.getValue(0); 2534 InFlag = EnvVal.getValue(1); 2535 2536 // Load TOC of the callee into r2. We are using a target-specific load 2537 // with r2 hard coded, because the result of a target-independent load 2538 // would never go directly into r2, since r2 is a reserved register (which 2539 // prevents the register allocator from allocating it), resulting in an 2540 // additional register being allocated and an unnecessary move instruction 2541 // being generated. 2542 VTs = DAG.getVTList(MVT::Other, MVT::Glue); 2543 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 2544 Callee, InFlag); 2545 Chain = LoadTOCPtr.getValue(0); 2546 InFlag = LoadTOCPtr.getValue(1); 2547 2548 MTCTROps[0] = Chain; 2549 MTCTROps[1] = LoadFuncPtr; 2550 MTCTROps[2] = InFlag; 2551 } 2552 2553 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 2554 2 + (InFlag.getNode() != 0)); 2555 InFlag = Chain.getValue(1); 2556 2557 NodeTys.clear(); 2558 NodeTys.push_back(MVT::Other); 2559 NodeTys.push_back(MVT::Glue); 2560 Ops.push_back(Chain); 2561 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin; 2562 Callee.setNode(0); 2563 // Add CTR register as callee so a bctr can be emitted later. 2564 if (isTailCall) 2565 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT)); 2566 } 2567 2568 // If this is a direct call, pass the chain and the callee. 2569 if (Callee.getNode()) { 2570 Ops.push_back(Chain); 2571 Ops.push_back(Callee); 2572 } 2573 // If this is a tail call add stack pointer delta. 2574 if (isTailCall) 2575 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 2576 2577 // Add argument registers to the end of the list so that they are known live 2578 // into the call. 2579 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2580 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2581 RegsToPass[i].second.getValueType())); 2582 2583 return CallOpc; 2584} 2585 2586SDValue 2587PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2588 CallingConv::ID CallConv, bool isVarArg, 2589 const SmallVectorImpl<ISD::InputArg> &Ins, 2590 DebugLoc dl, SelectionDAG &DAG, 2591 SmallVectorImpl<SDValue> &InVals) const { 2592 2593 SmallVector<CCValAssign, 16> RVLocs; 2594 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(), 2595 RVLocs, *DAG.getContext()); 2596 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2597 2598 // Copy all of the result registers out of their specified physreg. 2599 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2600 CCValAssign &VA = RVLocs[i]; 2601 EVT VT = VA.getValVT(); 2602 assert(VA.isRegLoc() && "Can only return in registers!"); 2603 Chain = DAG.getCopyFromReg(Chain, dl, 2604 VA.getLocReg(), VT, InFlag).getValue(1); 2605 InVals.push_back(Chain.getValue(0)); 2606 InFlag = Chain.getValue(2); 2607 } 2608 2609 return Chain; 2610} 2611 2612SDValue 2613PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, 2614 bool isTailCall, bool isVarArg, 2615 SelectionDAG &DAG, 2616 SmallVector<std::pair<unsigned, SDValue>, 8> 2617 &RegsToPass, 2618 SDValue InFlag, SDValue Chain, 2619 SDValue &Callee, 2620 int SPDiff, unsigned NumBytes, 2621 const SmallVectorImpl<ISD::InputArg> &Ins, 2622 SmallVectorImpl<SDValue> &InVals) const { 2623 std::vector<EVT> NodeTys; 2624 SmallVector<SDValue, 8> Ops; 2625 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 2626 isTailCall, RegsToPass, Ops, NodeTys, 2627 PPCSubTarget); 2628 2629 // When performing tail call optimization the callee pops its arguments off 2630 // the stack. Account for this here so these bytes can be pushed back on in 2631 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 2632 int BytesCalleePops = 2633 (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0; 2634 2635 if (InFlag.getNode()) 2636 Ops.push_back(InFlag); 2637 2638 // Emit tail call. 2639 if (isTailCall) { 2640 // If this is the first return lowered for this function, add the regs 2641 // to the liveout set for the function. 2642 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2643 SmallVector<CCValAssign, 16> RVLocs; 2644 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 2645 *DAG.getContext()); 2646 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2647 for (unsigned i = 0; i != RVLocs.size(); ++i) 2648 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2649 } 2650 2651 assert(((Callee.getOpcode() == ISD::Register && 2652 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 2653 Callee.getOpcode() == ISD::TargetExternalSymbol || 2654 Callee.getOpcode() == ISD::TargetGlobalAddress || 2655 isa<ConstantSDNode>(Callee)) && 2656 "Expecting an global address, external symbol, absolute value or register"); 2657 2658 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 2659 } 2660 2661 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 2662 InFlag = Chain.getValue(1); 2663 2664 // Add a NOP immediately after the branch instruction when using the 64-bit 2665 // SVR4 ABI. At link time, if caller and callee are in a different module and 2666 // thus have a different TOC, the call will be replaced with a call to a stub 2667 // function which saves the current TOC, loads the TOC of the callee and 2668 // branches to the callee. The NOP will be replaced with a load instruction 2669 // which restores the TOC of the caller from the TOC save slot of the current 2670 // stack frame. If caller and callee belong to the same module (and have the 2671 // same TOC), the NOP will remain unchanged. 2672 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 2673 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 2674 if (CallOpc == PPCISD::BCTRL_SVR4) { 2675 // This is a call through a function pointer. 2676 // Restore the caller TOC from the save area into R2. 2677 // See PrepareCall() for more information about calls through function 2678 // pointers in the 64-bit SVR4 ABI. 2679 // We are using a target-specific load with r2 hard coded, because the 2680 // result of a target-independent load would never go directly into r2, 2681 // since r2 is a reserved register (which prevents the register allocator 2682 // from allocating it), resulting in an additional register being 2683 // allocated and an unnecessary move instruction being generated. 2684 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 2685 InFlag = Chain.getValue(1); 2686 } else { 2687 // Otherwise insert NOP. 2688 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Glue, InFlag); 2689 } 2690 } 2691 2692 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2693 DAG.getIntPtrConstant(BytesCalleePops, true), 2694 InFlag); 2695 if (!Ins.empty()) 2696 InFlag = Chain.getValue(1); 2697 2698 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2699 Ins, dl, DAG, InVals); 2700} 2701 2702SDValue 2703PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2704 CallingConv::ID CallConv, bool isVarArg, 2705 bool &isTailCall, 2706 const SmallVectorImpl<ISD::OutputArg> &Outs, 2707 const SmallVectorImpl<SDValue> &OutVals, 2708 const SmallVectorImpl<ISD::InputArg> &Ins, 2709 DebugLoc dl, SelectionDAG &DAG, 2710 SmallVectorImpl<SDValue> &InVals) const { 2711 if (isTailCall) 2712 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 2713 Ins, DAG); 2714 2715 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) 2716 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg, 2717 isTailCall, Outs, OutVals, Ins, 2718 dl, DAG, InVals); 2719 2720 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg, 2721 isTailCall, Outs, OutVals, Ins, 2722 dl, DAG, InVals); 2723} 2724 2725SDValue 2726PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, 2727 CallingConv::ID CallConv, bool isVarArg, 2728 bool isTailCall, 2729 const SmallVectorImpl<ISD::OutputArg> &Outs, 2730 const SmallVectorImpl<SDValue> &OutVals, 2731 const SmallVectorImpl<ISD::InputArg> &Ins, 2732 DebugLoc dl, SelectionDAG &DAG, 2733 SmallVectorImpl<SDValue> &InVals) const { 2734 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description 2735 // of the 32-bit SVR4 ABI stack frame layout. 2736 2737 assert((CallConv == CallingConv::C || 2738 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 2739 2740 unsigned PtrByteSize = 4; 2741 2742 MachineFunction &MF = DAG.getMachineFunction(); 2743 2744 // Mark this function as potentially containing a function that contains a 2745 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2746 // and restoring the callers stack pointer in this functions epilog. This is 2747 // done because by tail calling the called function might overwrite the value 2748 // in this function's (MF) stack pointer stack slot 0(SP). 2749 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 2750 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2751 2752 // Count how many bytes are to be pushed on the stack, including the linkage 2753 // area, parameter list area and the part of the local variable space which 2754 // contains copies of aggregates which are passed by value. 2755 2756 // Assign locations to all of the outgoing arguments. 2757 SmallVector<CCValAssign, 16> ArgLocs; 2758 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 2759 ArgLocs, *DAG.getContext()); 2760 2761 // Reserve space for the linkage area on the stack. 2762 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 2763 2764 if (isVarArg) { 2765 // Handle fixed and variable vector arguments differently. 2766 // Fixed vector arguments go into registers as long as registers are 2767 // available. Variable vector arguments always go into memory. 2768 unsigned NumArgs = Outs.size(); 2769 2770 for (unsigned i = 0; i != NumArgs; ++i) { 2771 MVT ArgVT = Outs[i].VT; 2772 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2773 bool Result; 2774 2775 if (Outs[i].IsFixed) { 2776 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 2777 CCInfo); 2778 } else { 2779 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 2780 ArgFlags, CCInfo); 2781 } 2782 2783 if (Result) { 2784#ifndef NDEBUG 2785 errs() << "Call operand #" << i << " has unhandled type " 2786 << EVT(ArgVT).getEVTString() << "\n"; 2787#endif 2788 llvm_unreachable(0); 2789 } 2790 } 2791 } else { 2792 // All arguments are treated the same. 2793 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4); 2794 } 2795 2796 // Assign locations to all of the outgoing aggregate by value arguments. 2797 SmallVector<CCValAssign, 16> ByValArgLocs; 2798 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs, 2799 *DAG.getContext()); 2800 2801 // Reserve stack space for the allocations in CCInfo. 2802 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 2803 2804 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal); 2805 2806 // Size of the linkage area, parameter list area and the part of the local 2807 // space variable where copies of aggregates which are passed by value are 2808 // stored. 2809 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 2810 2811 // Calculate by how many bytes the stack has to be adjusted in case of tail 2812 // call optimization. 2813 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2814 2815 // Adjust the stack pointer for the new arguments... 2816 // These operations are automatically eliminated by the prolog/epilog pass 2817 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2818 SDValue CallSeqStart = Chain; 2819 2820 // Load the return address and frame pointer so it can be moved somewhere else 2821 // later. 2822 SDValue LROp, FPOp; 2823 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 2824 dl); 2825 2826 // Set up a copy of the stack pointer for use loading and storing any 2827 // arguments that may not fit in the registers available for argument 2828 // passing. 2829 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2830 2831 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2832 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 2833 SmallVector<SDValue, 8> MemOpChains; 2834 2835 // Walk the register/memloc assignments, inserting copies/loads. 2836 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 2837 i != e; 2838 ++i) { 2839 CCValAssign &VA = ArgLocs[i]; 2840 SDValue Arg = OutVals[i]; 2841 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2842 2843 if (Flags.isByVal()) { 2844 // Argument is an aggregate which is passed by value, thus we need to 2845 // create a copy of it in the local variable space of the current stack 2846 // frame (which is the stack frame of the caller) and pass the address of 2847 // this copy to the callee. 2848 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 2849 CCValAssign &ByValVA = ByValArgLocs[j++]; 2850 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 2851 2852 // Memory reserved in the local variable space of the callers stack frame. 2853 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 2854 2855 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2856 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2857 2858 // Create a copy of the argument in the local area of the current 2859 // stack frame. 2860 SDValue MemcpyCall = 2861 CreateCopyOfByValArgument(Arg, PtrOff, 2862 CallSeqStart.getNode()->getOperand(0), 2863 Flags, DAG, dl); 2864 2865 // This must go outside the CALLSEQ_START..END. 2866 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2867 CallSeqStart.getNode()->getOperand(1)); 2868 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 2869 NewCallSeqStart.getNode()); 2870 Chain = CallSeqStart = NewCallSeqStart; 2871 2872 // Pass the address of the aggregate copy on the stack either in a 2873 // physical register or in the parameter list area of the current stack 2874 // frame to the callee. 2875 Arg = PtrOff; 2876 } 2877 2878 if (VA.isRegLoc()) { 2879 // Put argument in a physical register. 2880 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2881 } else { 2882 // Put argument in the parameter list area of the current stack frame. 2883 assert(VA.isMemLoc()); 2884 unsigned LocMemOffset = VA.getLocMemOffset(); 2885 2886 if (!isTailCall) { 2887 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2888 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2889 2890 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2891 MachinePointerInfo(), 2892 false, false, 0)); 2893 } else { 2894 // Calculate and remember argument location. 2895 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 2896 TailCallArguments); 2897 } 2898 } 2899 } 2900 2901 if (!MemOpChains.empty()) 2902 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2903 &MemOpChains[0], MemOpChains.size()); 2904 2905 // Build a sequence of copy-to-reg nodes chained together with token chain 2906 // and flag operands which copy the outgoing args into the appropriate regs. 2907 SDValue InFlag; 2908 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2909 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2910 RegsToPass[i].second, InFlag); 2911 InFlag = Chain.getValue(1); 2912 } 2913 2914 // Set CR6 to true if this is a vararg call. 2915 if (isVarArg) { 2916 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0); 2917 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag); 2918 InFlag = Chain.getValue(1); 2919 } 2920 2921 if (isTailCall) 2922 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 2923 false, TailCallArguments); 2924 2925 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 2926 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 2927 Ins, InVals); 2928} 2929 2930SDValue 2931PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, 2932 CallingConv::ID CallConv, bool isVarArg, 2933 bool isTailCall, 2934 const SmallVectorImpl<ISD::OutputArg> &Outs, 2935 const SmallVectorImpl<SDValue> &OutVals, 2936 const SmallVectorImpl<ISD::InputArg> &Ins, 2937 DebugLoc dl, SelectionDAG &DAG, 2938 SmallVectorImpl<SDValue> &InVals) const { 2939 2940 unsigned NumOps = Outs.size(); 2941 2942 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2943 bool isPPC64 = PtrVT == MVT::i64; 2944 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2945 2946 MachineFunction &MF = DAG.getMachineFunction(); 2947 2948 // Mark this function as potentially containing a function that contains a 2949 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2950 // and restoring the callers stack pointer in this functions epilog. This is 2951 // done because by tail calling the called function might overwrite the value 2952 // in this function's (MF) stack pointer stack slot 0(SP). 2953 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 2954 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2955 2956 unsigned nAltivecParamsAtEnd = 0; 2957 2958 // Count how many bytes are to be pushed on the stack, including the linkage 2959 // area, and parameter passing area. We start with 24/48 bytes, which is 2960 // prereserved space for [SP][CR][LR][3 x unused]. 2961 unsigned NumBytes = 2962 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 2963 Outs, OutVals, 2964 nAltivecParamsAtEnd); 2965 2966 // Calculate by how many bytes the stack has to be adjusted in case of tail 2967 // call optimization. 2968 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2969 2970 // To protect arguments on the stack from being clobbered in a tail call, 2971 // force all the loads to happen before doing any other lowering. 2972 if (isTailCall) 2973 Chain = DAG.getStackArgumentTokenFactor(Chain); 2974 2975 // Adjust the stack pointer for the new arguments... 2976 // These operations are automatically eliminated by the prolog/epilog pass 2977 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2978 SDValue CallSeqStart = Chain; 2979 2980 // Load the return address and frame pointer so it can be move somewhere else 2981 // later. 2982 SDValue LROp, FPOp; 2983 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 2984 dl); 2985 2986 // Set up a copy of the stack pointer for use loading and storing any 2987 // arguments that may not fit in the registers available for argument 2988 // passing. 2989 SDValue StackPtr; 2990 if (isPPC64) 2991 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2992 else 2993 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2994 2995 // Figure out which arguments are going to go in registers, and which in 2996 // memory. Also, if this is a vararg function, floating point operations 2997 // must be stored to our stack, and loaded into integer regs as well, if 2998 // any integer regs are available for argument passing. 2999 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 3000 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 3001 3002 static const unsigned GPR_32[] = { // 32-bit registers. 3003 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 3004 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 3005 }; 3006 static const unsigned GPR_64[] = { // 64-bit registers. 3007 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 3008 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 3009 }; 3010 static const unsigned *FPR = GetFPR(); 3011 3012 static const unsigned VR[] = { 3013 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 3014 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 3015 }; 3016 const unsigned NumGPRs = array_lengthof(GPR_32); 3017 const unsigned NumFPRs = 13; 3018 const unsigned NumVRs = array_lengthof(VR); 3019 3020 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 3021 3022 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3023 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3024 3025 SmallVector<SDValue, 8> MemOpChains; 3026 for (unsigned i = 0; i != NumOps; ++i) { 3027 SDValue Arg = OutVals[i]; 3028 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3029 3030 // PtrOff will be used to store the current argument to the stack if a 3031 // register cannot be found for it. 3032 SDValue PtrOff; 3033 3034 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3035 3036 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3037 3038 // On PPC64, promote integers to 64-bit values. 3039 if (isPPC64 && Arg.getValueType() == MVT::i32) { 3040 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3041 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3042 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3043 } 3044 3045 // FIXME memcpy is used way more than necessary. Correctness first. 3046 if (Flags.isByVal()) { 3047 unsigned Size = Flags.getByValSize(); 3048 if (Size==1 || Size==2) { 3049 // Very small objects are passed right-justified. 3050 // Everything else is passed left-justified. 3051 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; 3052 if (GPR_idx != NumGPRs) { 3053 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 3054 MachinePointerInfo(), VT, 3055 false, false, 0); 3056 MemOpChains.push_back(Load.getValue(1)); 3057 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3058 3059 ArgOffset += PtrByteSize; 3060 } else { 3061 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); 3062 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3063 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 3064 CallSeqStart.getNode()->getOperand(0), 3065 Flags, DAG, dl); 3066 // This must go outside the CALLSEQ_START..END. 3067 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3068 CallSeqStart.getNode()->getOperand(1)); 3069 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3070 NewCallSeqStart.getNode()); 3071 Chain = CallSeqStart = NewCallSeqStart; 3072 ArgOffset += PtrByteSize; 3073 } 3074 continue; 3075 } 3076 // Copy entire object into memory. There are cases where gcc-generated 3077 // code assumes it is there, even if it could be put entirely into 3078 // registers. (This is not what the doc says.) 3079 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3080 CallSeqStart.getNode()->getOperand(0), 3081 Flags, DAG, dl); 3082 // This must go outside the CALLSEQ_START..END. 3083 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3084 CallSeqStart.getNode()->getOperand(1)); 3085 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode()); 3086 Chain = CallSeqStart = NewCallSeqStart; 3087 // And copy the pieces of it that fit into registers. 3088 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3089 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3090 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3091 if (GPR_idx != NumGPRs) { 3092 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 3093 MachinePointerInfo(), 3094 false, false, 0); 3095 MemOpChains.push_back(Load.getValue(1)); 3096 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3097 ArgOffset += PtrByteSize; 3098 } else { 3099 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3100 break; 3101 } 3102 } 3103 continue; 3104 } 3105 3106 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3107 default: llvm_unreachable("Unexpected ValueType for argument!"); 3108 case MVT::i32: 3109 case MVT::i64: 3110 if (GPR_idx != NumGPRs) { 3111 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3112 } else { 3113 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3114 isPPC64, isTailCall, false, MemOpChains, 3115 TailCallArguments, dl); 3116 } 3117 ArgOffset += PtrByteSize; 3118 break; 3119 case MVT::f32: 3120 case MVT::f64: 3121 if (FPR_idx != NumFPRs) { 3122 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3123 3124 if (isVarArg) { 3125 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3126 MachinePointerInfo(), false, false, 0); 3127 MemOpChains.push_back(Store); 3128 3129 // Float varargs are always shadowed in available integer registers 3130 if (GPR_idx != NumGPRs) { 3131 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3132 MachinePointerInfo(), false, false, 0); 3133 MemOpChains.push_back(Load.getValue(1)); 3134 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3135 } 3136 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 3137 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3138 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3139 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3140 MachinePointerInfo(), 3141 false, false, 0); 3142 MemOpChains.push_back(Load.getValue(1)); 3143 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3144 } 3145 } else { 3146 // If we have any FPRs remaining, we may also have GPRs remaining. 3147 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 3148 // GPRs. 3149 if (GPR_idx != NumGPRs) 3150 ++GPR_idx; 3151 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 3152 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 3153 ++GPR_idx; 3154 } 3155 } else { 3156 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3157 isPPC64, isTailCall, false, MemOpChains, 3158 TailCallArguments, dl); 3159 } 3160 if (isPPC64) 3161 ArgOffset += 8; 3162 else 3163 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 3164 break; 3165 case MVT::v4f32: 3166 case MVT::v4i32: 3167 case MVT::v8i16: 3168 case MVT::v16i8: 3169 if (isVarArg) { 3170 // These go aligned on the stack, or in the corresponding R registers 3171 // when within range. The Darwin PPC ABI doc claims they also go in 3172 // V registers; in fact gcc does this only for arguments that are 3173 // prototyped, not for those that match the ... We do it for all 3174 // arguments, seems to work. 3175 while (ArgOffset % 16 !=0) { 3176 ArgOffset += PtrByteSize; 3177 if (GPR_idx != NumGPRs) 3178 GPR_idx++; 3179 } 3180 // We could elide this store in the case where the object fits 3181 // entirely in R registers. Maybe later. 3182 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3183 DAG.getConstant(ArgOffset, PtrVT)); 3184 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3185 MachinePointerInfo(), false, false, 0); 3186 MemOpChains.push_back(Store); 3187 if (VR_idx != NumVRs) { 3188 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 3189 MachinePointerInfo(), 3190 false, false, 0); 3191 MemOpChains.push_back(Load.getValue(1)); 3192 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 3193 } 3194 ArgOffset += 16; 3195 for (unsigned i=0; i<16; i+=PtrByteSize) { 3196 if (GPR_idx == NumGPRs) 3197 break; 3198 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 3199 DAG.getConstant(i, PtrVT)); 3200 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 3201 false, false, 0); 3202 MemOpChains.push_back(Load.getValue(1)); 3203 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3204 } 3205 break; 3206 } 3207 3208 // Non-varargs Altivec params generally go in registers, but have 3209 // stack space allocated at the end. 3210 if (VR_idx != NumVRs) { 3211 // Doesn't have GPR space allocated. 3212 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 3213 } else if (nAltivecParamsAtEnd==0) { 3214 // We are emitting Altivec params in order. 3215 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3216 isPPC64, isTailCall, true, MemOpChains, 3217 TailCallArguments, dl); 3218 ArgOffset += 16; 3219 } 3220 break; 3221 } 3222 } 3223 // If all Altivec parameters fit in registers, as they usually do, 3224 // they get stack space following the non-Altivec parameters. We 3225 // don't track this here because nobody below needs it. 3226 // If there are more Altivec parameters than fit in registers emit 3227 // the stores here. 3228 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 3229 unsigned j = 0; 3230 // Offset is aligned; skip 1st 12 params which go in V registers. 3231 ArgOffset = ((ArgOffset+15)/16)*16; 3232 ArgOffset += 12*16; 3233 for (unsigned i = 0; i != NumOps; ++i) { 3234 SDValue Arg = OutVals[i]; 3235 EVT ArgType = Outs[i].VT; 3236 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 3237 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 3238 if (++j > NumVRs) { 3239 SDValue PtrOff; 3240 // We are emitting Altivec params in order. 3241 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3242 isPPC64, isTailCall, true, MemOpChains, 3243 TailCallArguments, dl); 3244 ArgOffset += 16; 3245 } 3246 } 3247 } 3248 } 3249 3250 if (!MemOpChains.empty()) 3251 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3252 &MemOpChains[0], MemOpChains.size()); 3253 3254 // Check if this is an indirect call (MTCTR/BCTRL). 3255 // See PrepareCall() for more information about calls through function 3256 // pointers in the 64-bit SVR4 ABI. 3257 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() && 3258 !dyn_cast<GlobalAddressSDNode>(Callee) && 3259 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3260 !isBLACompatibleAddress(Callee, DAG)) { 3261 // Load r2 into a virtual register and store it to the TOC save area. 3262 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 3263 // TOC save area offset. 3264 SDValue PtrOff = DAG.getIntPtrConstant(40); 3265 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3266 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(), 3267 false, false, 0); 3268 } 3269 3270 // On Darwin, R12 must contain the address of an indirect callee. This does 3271 // not mean the MTCTR instruction must use R12; it's easier to model this as 3272 // an extra parameter, so do that. 3273 if (!isTailCall && 3274 !dyn_cast<GlobalAddressSDNode>(Callee) && 3275 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3276 !isBLACompatibleAddress(Callee, DAG)) 3277 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : 3278 PPC::R12), Callee)); 3279 3280 // Build a sequence of copy-to-reg nodes chained together with token chain 3281 // and flag operands which copy the outgoing args into the appropriate regs. 3282 SDValue InFlag; 3283 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3284 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3285 RegsToPass[i].second, InFlag); 3286 InFlag = Chain.getValue(1); 3287 } 3288 3289 if (isTailCall) 3290 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 3291 FPOp, true, TailCallArguments); 3292 3293 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3294 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3295 Ins, InVals); 3296} 3297 3298SDValue 3299PPCTargetLowering::LowerReturn(SDValue Chain, 3300 CallingConv::ID CallConv, bool isVarArg, 3301 const SmallVectorImpl<ISD::OutputArg> &Outs, 3302 const SmallVectorImpl<SDValue> &OutVals, 3303 DebugLoc dl, SelectionDAG &DAG) const { 3304 3305 SmallVector<CCValAssign, 16> RVLocs; 3306 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 3307 RVLocs, *DAG.getContext()); 3308 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 3309 3310 // If this is the first return lowered for this function, add the regs to the 3311 // liveout set for the function. 3312 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3313 for (unsigned i = 0; i != RVLocs.size(); ++i) 3314 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3315 } 3316 3317 SDValue Flag; 3318 3319 // Copy the result values into the output registers. 3320 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3321 CCValAssign &VA = RVLocs[i]; 3322 assert(VA.isRegLoc() && "Can only return in registers!"); 3323 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 3324 OutVals[i], Flag); 3325 Flag = Chain.getValue(1); 3326 } 3327 3328 if (Flag.getNode()) 3329 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 3330 else 3331 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); 3332} 3333 3334SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 3335 const PPCSubtarget &Subtarget) const { 3336 // When we pop the dynamic allocation we need to restore the SP link. 3337 DebugLoc dl = Op.getDebugLoc(); 3338 3339 // Get the corect type for pointers. 3340 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3341 3342 // Construct the stack pointer operand. 3343 bool isPPC64 = Subtarget.isPPC64(); 3344 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 3345 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 3346 3347 // Get the operands for the STACKRESTORE. 3348 SDValue Chain = Op.getOperand(0); 3349 SDValue SaveSP = Op.getOperand(1); 3350 3351 // Load the old link SP. 3352 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, 3353 MachinePointerInfo(), 3354 false, false, 0); 3355 3356 // Restore the stack pointer. 3357 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 3358 3359 // Store the old link SP. 3360 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(), 3361 false, false, 0); 3362} 3363 3364 3365 3366SDValue 3367PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 3368 MachineFunction &MF = DAG.getMachineFunction(); 3369 bool isPPC64 = PPCSubTarget.isPPC64(); 3370 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3371 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3372 3373 // Get current frame pointer save index. The users of this index will be 3374 // primarily DYNALLOC instructions. 3375 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3376 int RASI = FI->getReturnAddrSaveIndex(); 3377 3378 // If the frame pointer save index hasn't been defined yet. 3379 if (!RASI) { 3380 // Find out what the fix offset of the frame pointer save area. 3381 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 3382 // Allocate the frame index for frame pointer save area. 3383 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true); 3384 // Save the result. 3385 FI->setReturnAddrSaveIndex(RASI); 3386 } 3387 return DAG.getFrameIndex(RASI, PtrVT); 3388} 3389 3390SDValue 3391PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 3392 MachineFunction &MF = DAG.getMachineFunction(); 3393 bool isPPC64 = PPCSubTarget.isPPC64(); 3394 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3395 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3396 3397 // Get current frame pointer save index. The users of this index will be 3398 // primarily DYNALLOC instructions. 3399 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3400 int FPSI = FI->getFramePointerSaveIndex(); 3401 3402 // If the frame pointer save index hasn't been defined yet. 3403 if (!FPSI) { 3404 // Find out what the fix offset of the frame pointer save area. 3405 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, 3406 isDarwinABI); 3407 3408 // Allocate the frame index for frame pointer save area. 3409 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 3410 // Save the result. 3411 FI->setFramePointerSaveIndex(FPSI); 3412 } 3413 return DAG.getFrameIndex(FPSI, PtrVT); 3414} 3415 3416SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 3417 SelectionDAG &DAG, 3418 const PPCSubtarget &Subtarget) const { 3419 // Get the inputs. 3420 SDValue Chain = Op.getOperand(0); 3421 SDValue Size = Op.getOperand(1); 3422 DebugLoc dl = Op.getDebugLoc(); 3423 3424 // Get the corect type for pointers. 3425 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3426 // Negate the size. 3427 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 3428 DAG.getConstant(0, PtrVT), Size); 3429 // Construct a node for the frame pointer save index. 3430 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 3431 // Build a DYNALLOC node. 3432 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 3433 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 3434 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 3435} 3436 3437/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 3438/// possible. 3439SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 3440 // Not FP? Not a fsel. 3441 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 3442 !Op.getOperand(2).getValueType().isFloatingPoint()) 3443 return Op; 3444 3445 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 3446 3447 // Cannot handle SETEQ/SETNE. 3448 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 3449 3450 EVT ResVT = Op.getValueType(); 3451 EVT CmpVT = Op.getOperand(0).getValueType(); 3452 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3453 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 3454 DebugLoc dl = Op.getDebugLoc(); 3455 3456 // If the RHS of the comparison is a 0.0, we don't need to do the 3457 // subtraction at all. 3458 if (isFloatingPointZero(RHS)) 3459 switch (CC) { 3460 default: break; // SETUO etc aren't handled by fsel. 3461 case ISD::SETULT: 3462 case ISD::SETLT: 3463 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3464 case ISD::SETOGE: 3465 case ISD::SETGE: 3466 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3467 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3468 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 3469 case ISD::SETUGT: 3470 case ISD::SETGT: 3471 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3472 case ISD::SETOLE: 3473 case ISD::SETLE: 3474 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3475 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3476 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 3477 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 3478 } 3479 3480 SDValue Cmp; 3481 switch (CC) { 3482 default: break; // SETUO etc aren't handled by fsel. 3483 case ISD::SETULT: 3484 case ISD::SETLT: 3485 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3486 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3487 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3488 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3489 case ISD::SETOGE: 3490 case ISD::SETGE: 3491 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3492 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3493 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3494 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3495 case ISD::SETUGT: 3496 case ISD::SETGT: 3497 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3498 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3499 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3500 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3501 case ISD::SETOLE: 3502 case ISD::SETLE: 3503 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3504 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3505 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3506 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3507 } 3508 return Op; 3509} 3510 3511// FIXME: Split this code up when LegalizeDAGTypes lands. 3512SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 3513 DebugLoc dl) const { 3514 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 3515 SDValue Src = Op.getOperand(0); 3516 if (Src.getValueType() == MVT::f32) 3517 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 3518 3519 SDValue Tmp; 3520 switch (Op.getValueType().getSimpleVT().SimpleTy) { 3521 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 3522 case MVT::i32: 3523 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 3524 PPCISD::FCTIDZ, 3525 dl, MVT::f64, Src); 3526 break; 3527 case MVT::i64: 3528 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 3529 break; 3530 } 3531 3532 // Convert the FP value to an int value through memory. 3533 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 3534 3535 // Emit a store to the stack slot. 3536 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, 3537 MachinePointerInfo(), false, false, 0); 3538 3539 // Result is a load from the stack slot. If loading 4 bytes, make sure to 3540 // add in a bias. 3541 if (Op.getValueType() == MVT::i32) 3542 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 3543 DAG.getConstant(4, FIPtr.getValueType())); 3544 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(), 3545 false, false, 0); 3546} 3547 3548SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, 3549 SelectionDAG &DAG) const { 3550 DebugLoc dl = Op.getDebugLoc(); 3551 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 3552 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 3553 return SDValue(); 3554 3555 if (Op.getOperand(0).getValueType() == MVT::i64) { 3556 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0)); 3557 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 3558 if (Op.getValueType() == MVT::f32) 3559 FP = DAG.getNode(ISD::FP_ROUND, dl, 3560 MVT::f32, FP, DAG.getIntPtrConstant(0)); 3561 return FP; 3562 } 3563 3564 assert(Op.getOperand(0).getValueType() == MVT::i32 && 3565 "Unhandled SINT_TO_FP type in custom expander!"); 3566 // Since we only generate this in 64-bit mode, we can take advantage of 3567 // 64-bit registers. In particular, sign extend the input value into the 3568 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 3569 // then lfd it and fcfid it. 3570 MachineFunction &MF = DAG.getMachineFunction(); 3571 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 3572 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 3573 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3574 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 3575 3576 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 3577 Op.getOperand(0)); 3578 3579 // STD the extended value into the stack slot. 3580 MachineMemOperand *MMO = 3581 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 3582 MachineMemOperand::MOStore, 8, 8); 3583 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx }; 3584 SDValue Store = 3585 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other), 3586 Ops, 4, MVT::i64, MMO); 3587 // Load the value as a double. 3588 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(), 3589 false, false, 0); 3590 3591 // FCFID it and return it. 3592 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 3593 if (Op.getValueType() == MVT::f32) 3594 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 3595 return FP; 3596} 3597 3598SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3599 SelectionDAG &DAG) const { 3600 DebugLoc dl = Op.getDebugLoc(); 3601 /* 3602 The rounding mode is in bits 30:31 of FPSR, and has the following 3603 settings: 3604 00 Round to nearest 3605 01 Round to 0 3606 10 Round to +inf 3607 11 Round to -inf 3608 3609 FLT_ROUNDS, on the other hand, expects the following: 3610 -1 Undefined 3611 0 Round to 0 3612 1 Round to nearest 3613 2 Round to +inf 3614 3 Round to -inf 3615 3616 To perform the conversion, we do: 3617 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 3618 */ 3619 3620 MachineFunction &MF = DAG.getMachineFunction(); 3621 EVT VT = Op.getValueType(); 3622 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3623 std::vector<EVT> NodeTys; 3624 SDValue MFFSreg, InFlag; 3625 3626 // Save FP Control Word to register 3627 NodeTys.push_back(MVT::f64); // return register 3628 NodeTys.push_back(MVT::Glue); // unused in this context 3629 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 3630 3631 // Save FP register to stack slot 3632 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 3633 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 3634 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 3635 StackSlot, MachinePointerInfo(), false, false,0); 3636 3637 // Load FP Control Word from low 32 bits of stack slot. 3638 SDValue Four = DAG.getConstant(4, PtrVT); 3639 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 3640 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), 3641 false, false, 0); 3642 3643 // Transform as necessary 3644 SDValue CWD1 = 3645 DAG.getNode(ISD::AND, dl, MVT::i32, 3646 CWD, DAG.getConstant(3, MVT::i32)); 3647 SDValue CWD2 = 3648 DAG.getNode(ISD::SRL, dl, MVT::i32, 3649 DAG.getNode(ISD::AND, dl, MVT::i32, 3650 DAG.getNode(ISD::XOR, dl, MVT::i32, 3651 CWD, DAG.getConstant(3, MVT::i32)), 3652 DAG.getConstant(3, MVT::i32)), 3653 DAG.getConstant(1, MVT::i32)); 3654 3655 SDValue RetVal = 3656 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 3657 3658 return DAG.getNode((VT.getSizeInBits() < 16 ? 3659 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 3660} 3661 3662SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const { 3663 EVT VT = Op.getValueType(); 3664 unsigned BitWidth = VT.getSizeInBits(); 3665 DebugLoc dl = Op.getDebugLoc(); 3666 assert(Op.getNumOperands() == 3 && 3667 VT == Op.getOperand(1).getValueType() && 3668 "Unexpected SHL!"); 3669 3670 // Expand into a bunch of logical ops. Note that these ops 3671 // depend on the PPC behavior for oversized shift amounts. 3672 SDValue Lo = Op.getOperand(0); 3673 SDValue Hi = Op.getOperand(1); 3674 SDValue Amt = Op.getOperand(2); 3675 EVT AmtVT = Amt.getValueType(); 3676 3677 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3678 DAG.getConstant(BitWidth, AmtVT), Amt); 3679 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 3680 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 3681 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 3682 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3683 DAG.getConstant(-BitWidth, AmtVT)); 3684 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 3685 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3686 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 3687 SDValue OutOps[] = { OutLo, OutHi }; 3688 return DAG.getMergeValues(OutOps, 2, dl); 3689} 3690 3691SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const { 3692 EVT VT = Op.getValueType(); 3693 DebugLoc dl = Op.getDebugLoc(); 3694 unsigned BitWidth = VT.getSizeInBits(); 3695 assert(Op.getNumOperands() == 3 && 3696 VT == Op.getOperand(1).getValueType() && 3697 "Unexpected SRL!"); 3698 3699 // Expand into a bunch of logical ops. Note that these ops 3700 // depend on the PPC behavior for oversized shift amounts. 3701 SDValue Lo = Op.getOperand(0); 3702 SDValue Hi = Op.getOperand(1); 3703 SDValue Amt = Op.getOperand(2); 3704 EVT AmtVT = Amt.getValueType(); 3705 3706 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3707 DAG.getConstant(BitWidth, AmtVT), Amt); 3708 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3709 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3710 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3711 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3712 DAG.getConstant(-BitWidth, AmtVT)); 3713 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 3714 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3715 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 3716 SDValue OutOps[] = { OutLo, OutHi }; 3717 return DAG.getMergeValues(OutOps, 2, dl); 3718} 3719 3720SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const { 3721 DebugLoc dl = Op.getDebugLoc(); 3722 EVT VT = Op.getValueType(); 3723 unsigned BitWidth = VT.getSizeInBits(); 3724 assert(Op.getNumOperands() == 3 && 3725 VT == Op.getOperand(1).getValueType() && 3726 "Unexpected SRA!"); 3727 3728 // Expand into a bunch of logical ops, followed by a select_cc. 3729 SDValue Lo = Op.getOperand(0); 3730 SDValue Hi = Op.getOperand(1); 3731 SDValue Amt = Op.getOperand(2); 3732 EVT AmtVT = Amt.getValueType(); 3733 3734 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3735 DAG.getConstant(BitWidth, AmtVT), Amt); 3736 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3737 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3738 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3739 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3740 DAG.getConstant(-BitWidth, AmtVT)); 3741 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 3742 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 3743 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 3744 Tmp4, Tmp6, ISD::SETLE); 3745 SDValue OutOps[] = { OutLo, OutHi }; 3746 return DAG.getMergeValues(OutOps, 2, dl); 3747} 3748 3749//===----------------------------------------------------------------------===// 3750// Vector related lowering. 3751// 3752 3753/// BuildSplatI - Build a canonical splati of Val with an element size of 3754/// SplatSize. Cast the result to VT. 3755static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 3756 SelectionDAG &DAG, DebugLoc dl) { 3757 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 3758 3759 static const EVT VTys[] = { // canonical VT to use for each size. 3760 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 3761 }; 3762 3763 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 3764 3765 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 3766 if (Val == -1) 3767 SplatSize = 1; 3768 3769 EVT CanonicalVT = VTys[SplatSize-1]; 3770 3771 // Build a canonical splat for this value. 3772 SDValue Elt = DAG.getConstant(Val, MVT::i32); 3773 SmallVector<SDValue, 8> Ops; 3774 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 3775 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 3776 &Ops[0], Ops.size()); 3777 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res); 3778} 3779 3780/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 3781/// specified intrinsic ID. 3782static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 3783 SelectionDAG &DAG, DebugLoc dl, 3784 EVT DestVT = MVT::Other) { 3785 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 3786 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3787 DAG.getConstant(IID, MVT::i32), LHS, RHS); 3788} 3789 3790/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 3791/// specified intrinsic ID. 3792static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 3793 SDValue Op2, SelectionDAG &DAG, 3794 DebugLoc dl, EVT DestVT = MVT::Other) { 3795 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 3796 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3797 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 3798} 3799 3800 3801/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 3802/// amount. The result has the specified value type. 3803static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 3804 EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3805 // Force LHS/RHS to be the right type. 3806 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); 3807 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); 3808 3809 int Ops[16]; 3810 for (unsigned i = 0; i != 16; ++i) 3811 Ops[i] = i + Amt; 3812 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 3813 return DAG.getNode(ISD::BITCAST, dl, VT, T); 3814} 3815 3816// If this is a case we can't handle, return null and let the default 3817// expansion code take care of it. If we CAN select this case, and if it 3818// selects to a single instruction, return Op. Otherwise, if we can codegen 3819// this case more efficiently than a constant pool load, lower it to the 3820// sequence of ops that should be used. 3821SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 3822 SelectionDAG &DAG) const { 3823 DebugLoc dl = Op.getDebugLoc(); 3824 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 3825 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 3826 3827 // Check if this is a splat of a constant value. 3828 APInt APSplatBits, APSplatUndef; 3829 unsigned SplatBitSize; 3830 bool HasAnyUndefs; 3831 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 3832 HasAnyUndefs, 0, true) || SplatBitSize > 32) 3833 return SDValue(); 3834 3835 unsigned SplatBits = APSplatBits.getZExtValue(); 3836 unsigned SplatUndef = APSplatUndef.getZExtValue(); 3837 unsigned SplatSize = SplatBitSize / 8; 3838 3839 // First, handle single instruction cases. 3840 3841 // All zeros? 3842 if (SplatBits == 0) { 3843 // Canonicalize all zero vectors to be v4i32. 3844 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 3845 SDValue Z = DAG.getConstant(0, MVT::i32); 3846 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 3847 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z); 3848 } 3849 return Op; 3850 } 3851 3852 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 3853 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 3854 (32-SplatBitSize)); 3855 if (SextVal >= -16 && SextVal <= 15) 3856 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 3857 3858 3859 // Two instruction sequences. 3860 3861 // If this value is in the range [-32,30] and is even, use: 3862 // tmp = VSPLTI[bhw], result = add tmp, tmp 3863 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 3864 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); 3865 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); 3866 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 3867 } 3868 3869 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 3870 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 3871 // for fneg/fabs. 3872 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 3873 // Make -1 and vspltisw -1: 3874 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 3875 3876 // Make the VSLW intrinsic, computing 0x8000_0000. 3877 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 3878 OnesV, DAG, dl); 3879 3880 // xor by OnesV to invert it. 3881 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 3882 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 3883 } 3884 3885 // Check to see if this is a wide variety of vsplti*, binop self cases. 3886 static const signed char SplatCsts[] = { 3887 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 3888 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 3889 }; 3890 3891 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 3892 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 3893 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 3894 int i = SplatCsts[idx]; 3895 3896 // Figure out what shift amount will be used by altivec if shifted by i in 3897 // this splat size. 3898 unsigned TypeShiftAmt = i & (SplatBitSize-1); 3899 3900 // vsplti + shl self. 3901 if (SextVal == (i << (int)TypeShiftAmt)) { 3902 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3903 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3904 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 3905 Intrinsic::ppc_altivec_vslw 3906 }; 3907 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3908 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 3909 } 3910 3911 // vsplti + srl self. 3912 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3913 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3914 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3915 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 3916 Intrinsic::ppc_altivec_vsrw 3917 }; 3918 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3919 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 3920 } 3921 3922 // vsplti + sra self. 3923 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3924 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3925 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3926 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 3927 Intrinsic::ppc_altivec_vsraw 3928 }; 3929 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3930 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 3931 } 3932 3933 // vsplti + rol self. 3934 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 3935 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 3936 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3937 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3938 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 3939 Intrinsic::ppc_altivec_vrlw 3940 }; 3941 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3942 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 3943 } 3944 3945 // t = vsplti c, result = vsldoi t, t, 1 3946 if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) { 3947 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3948 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 3949 } 3950 // t = vsplti c, result = vsldoi t, t, 2 3951 if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) { 3952 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3953 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 3954 } 3955 // t = vsplti c, result = vsldoi t, t, 3 3956 if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) { 3957 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3958 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 3959 } 3960 } 3961 3962 // Three instruction sequences. 3963 3964 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 3965 if (SextVal >= 0 && SextVal <= 31) { 3966 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); 3967 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3968 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); 3969 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS); 3970 } 3971 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 3972 if (SextVal >= -31 && SextVal <= 0) { 3973 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); 3974 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3975 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); 3976 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS); 3977 } 3978 3979 return SDValue(); 3980} 3981 3982/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 3983/// the specified operations to build the shuffle. 3984static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 3985 SDValue RHS, SelectionDAG &DAG, 3986 DebugLoc dl) { 3987 unsigned OpNum = (PFEntry >> 26) & 0x0F; 3988 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 3989 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 3990 3991 enum { 3992 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 3993 OP_VMRGHW, 3994 OP_VMRGLW, 3995 OP_VSPLTISW0, 3996 OP_VSPLTISW1, 3997 OP_VSPLTISW2, 3998 OP_VSPLTISW3, 3999 OP_VSLDOI4, 4000 OP_VSLDOI8, 4001 OP_VSLDOI12 4002 }; 4003 4004 if (OpNum == OP_COPY) { 4005 if (LHSID == (1*9+2)*9+3) return LHS; 4006 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4007 return RHS; 4008 } 4009 4010 SDValue OpLHS, OpRHS; 4011 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4012 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4013 4014 int ShufIdxs[16]; 4015 switch (OpNum) { 4016 default: llvm_unreachable("Unknown i32 permute!"); 4017 case OP_VMRGHW: 4018 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 4019 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 4020 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 4021 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 4022 break; 4023 case OP_VMRGLW: 4024 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 4025 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 4026 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 4027 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 4028 break; 4029 case OP_VSPLTISW0: 4030 for (unsigned i = 0; i != 16; ++i) 4031 ShufIdxs[i] = (i&3)+0; 4032 break; 4033 case OP_VSPLTISW1: 4034 for (unsigned i = 0; i != 16; ++i) 4035 ShufIdxs[i] = (i&3)+4; 4036 break; 4037 case OP_VSPLTISW2: 4038 for (unsigned i = 0; i != 16; ++i) 4039 ShufIdxs[i] = (i&3)+8; 4040 break; 4041 case OP_VSPLTISW3: 4042 for (unsigned i = 0; i != 16; ++i) 4043 ShufIdxs[i] = (i&3)+12; 4044 break; 4045 case OP_VSLDOI4: 4046 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 4047 case OP_VSLDOI8: 4048 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 4049 case OP_VSLDOI12: 4050 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 4051 } 4052 EVT VT = OpLHS.getValueType(); 4053 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); 4054 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); 4055 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 4056 return DAG.getNode(ISD::BITCAST, dl, VT, T); 4057} 4058 4059/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 4060/// is a shuffle we can handle in a single instruction, return it. Otherwise, 4061/// return the code it can be lowered into. Worst case, it can always be 4062/// lowered into a vperm. 4063SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 4064 SelectionDAG &DAG) const { 4065 DebugLoc dl = Op.getDebugLoc(); 4066 SDValue V1 = Op.getOperand(0); 4067 SDValue V2 = Op.getOperand(1); 4068 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4069 EVT VT = Op.getValueType(); 4070 4071 // Cases that are handled by instructions that take permute immediates 4072 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 4073 // selected by the instruction selector. 4074 if (V2.getOpcode() == ISD::UNDEF) { 4075 if (PPC::isSplatShuffleMask(SVOp, 1) || 4076 PPC::isSplatShuffleMask(SVOp, 2) || 4077 PPC::isSplatShuffleMask(SVOp, 4) || 4078 PPC::isVPKUWUMShuffleMask(SVOp, true) || 4079 PPC::isVPKUHUMShuffleMask(SVOp, true) || 4080 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 4081 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 4082 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 4083 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 4084 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 4085 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 4086 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 4087 return Op; 4088 } 4089 } 4090 4091 // Altivec has a variety of "shuffle immediates" that take two vector inputs 4092 // and produce a fixed permutation. If any of these match, do not lower to 4093 // VPERM. 4094 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 4095 PPC::isVPKUHUMShuffleMask(SVOp, false) || 4096 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 4097 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 4098 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 4099 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 4100 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 4101 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 4102 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 4103 return Op; 4104 4105 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 4106 // perfect shuffle table to emit an optimal matching sequence. 4107 SmallVector<int, 16> PermMask; 4108 SVOp->getMask(PermMask); 4109 4110 unsigned PFIndexes[4]; 4111 bool isFourElementShuffle = true; 4112 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 4113 unsigned EltNo = 8; // Start out undef. 4114 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 4115 if (PermMask[i*4+j] < 0) 4116 continue; // Undef, ignore it. 4117 4118 unsigned ByteSource = PermMask[i*4+j]; 4119 if ((ByteSource & 3) != j) { 4120 isFourElementShuffle = false; 4121 break; 4122 } 4123 4124 if (EltNo == 8) { 4125 EltNo = ByteSource/4; 4126 } else if (EltNo != ByteSource/4) { 4127 isFourElementShuffle = false; 4128 break; 4129 } 4130 } 4131 PFIndexes[i] = EltNo; 4132 } 4133 4134 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 4135 // perfect shuffle vector to determine if it is cost effective to do this as 4136 // discrete instructions, or whether we should use a vperm. 4137 if (isFourElementShuffle) { 4138 // Compute the index in the perfect shuffle table. 4139 unsigned PFTableIndex = 4140 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4141 4142 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4143 unsigned Cost = (PFEntry >> 30); 4144 4145 // Determining when to avoid vperm is tricky. Many things affect the cost 4146 // of vperm, particularly how many times the perm mask needs to be computed. 4147 // For example, if the perm mask can be hoisted out of a loop or is already 4148 // used (perhaps because there are multiple permutes with the same shuffle 4149 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 4150 // the loop requires an extra register. 4151 // 4152 // As a compromise, we only emit discrete instructions if the shuffle can be 4153 // generated in 3 or fewer operations. When we have loop information 4154 // available, if this block is within a loop, we should avoid using vperm 4155 // for 3-operation perms and use a constant pool load instead. 4156 if (Cost < 3) 4157 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4158 } 4159 4160 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 4161 // vector that will get spilled to the constant pool. 4162 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 4163 4164 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 4165 // that it is in input element units, not in bytes. Convert now. 4166 EVT EltVT = V1.getValueType().getVectorElementType(); 4167 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 4168 4169 SmallVector<SDValue, 16> ResultMask; 4170 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 4171 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 4172 4173 for (unsigned j = 0; j != BytesPerElement; ++j) 4174 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 4175 MVT::i32)); 4176 } 4177 4178 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 4179 &ResultMask[0], ResultMask.size()); 4180 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 4181} 4182 4183/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 4184/// altivec comparison. If it is, return true and fill in Opc/isDot with 4185/// information about the intrinsic. 4186static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 4187 bool &isDot) { 4188 unsigned IntrinsicID = 4189 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 4190 CompareOpc = -1; 4191 isDot = false; 4192 switch (IntrinsicID) { 4193 default: return false; 4194 // Comparison predicates. 4195 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 4196 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 4197 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 4198 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 4199 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 4200 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 4201 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 4202 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 4203 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 4204 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 4205 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 4206 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 4207 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 4208 4209 // Normal Comparisons. 4210 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 4211 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 4212 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 4213 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 4214 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 4215 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 4216 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 4217 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 4218 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 4219 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 4220 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 4221 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 4222 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 4223 } 4224 return true; 4225} 4226 4227/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 4228/// lower, do it, otherwise return null. 4229SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 4230 SelectionDAG &DAG) const { 4231 // If this is a lowered altivec predicate compare, CompareOpc is set to the 4232 // opcode number of the comparison. 4233 DebugLoc dl = Op.getDebugLoc(); 4234 int CompareOpc; 4235 bool isDot; 4236 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 4237 return SDValue(); // Don't custom lower most intrinsics. 4238 4239 // If this is a non-dot comparison, make the VCMP node and we are done. 4240 if (!isDot) { 4241 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 4242 Op.getOperand(1), Op.getOperand(2), 4243 DAG.getConstant(CompareOpc, MVT::i32)); 4244 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp); 4245 } 4246 4247 // Create the PPCISD altivec 'dot' comparison node. 4248 SDValue Ops[] = { 4249 Op.getOperand(2), // LHS 4250 Op.getOperand(3), // RHS 4251 DAG.getConstant(CompareOpc, MVT::i32) 4252 }; 4253 std::vector<EVT> VTs; 4254 VTs.push_back(Op.getOperand(2).getValueType()); 4255 VTs.push_back(MVT::Glue); 4256 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 4257 4258 // Now that we have the comparison, emit a copy from the CR to a GPR. 4259 // This is flagged to the above dot comparison. 4260 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 4261 DAG.getRegister(PPC::CR6, MVT::i32), 4262 CompNode.getValue(1)); 4263 4264 // Unpack the result based on how the target uses it. 4265 unsigned BitNo; // Bit # of CR6. 4266 bool InvertBit; // Invert result? 4267 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 4268 default: // Can't happen, don't crash on invalid number though. 4269 case 0: // Return the value of the EQ bit of CR6. 4270 BitNo = 0; InvertBit = false; 4271 break; 4272 case 1: // Return the inverted value of the EQ bit of CR6. 4273 BitNo = 0; InvertBit = true; 4274 break; 4275 case 2: // Return the value of the LT bit of CR6. 4276 BitNo = 2; InvertBit = false; 4277 break; 4278 case 3: // Return the inverted value of the LT bit of CR6. 4279 BitNo = 2; InvertBit = true; 4280 break; 4281 } 4282 4283 // Shift the bit into the low position. 4284 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 4285 DAG.getConstant(8-(3-BitNo), MVT::i32)); 4286 // Isolate the bit. 4287 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 4288 DAG.getConstant(1, MVT::i32)); 4289 4290 // If we are supposed to, toggle the bit. 4291 if (InvertBit) 4292 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 4293 DAG.getConstant(1, MVT::i32)); 4294 return Flags; 4295} 4296 4297SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 4298 SelectionDAG &DAG) const { 4299 DebugLoc dl = Op.getDebugLoc(); 4300 // Create a stack slot that is 16-byte aligned. 4301 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4302 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 4303 EVT PtrVT = getPointerTy(); 4304 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4305 4306 // Store the input value into Value#0 of the stack slot. 4307 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 4308 Op.getOperand(0), FIdx, MachinePointerInfo(), 4309 false, false, 0); 4310 // Load it out. 4311 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(), 4312 false, false, 0); 4313} 4314 4315SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 4316 DebugLoc dl = Op.getDebugLoc(); 4317 if (Op.getValueType() == MVT::v4i32) { 4318 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4319 4320 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 4321 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 4322 4323 SDValue RHSSwap = // = vrlw RHS, 16 4324 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 4325 4326 // Shrinkify inputs to v8i16. 4327 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); 4328 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); 4329 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); 4330 4331 // Low parts multiplied together, generating 32-bit results (we ignore the 4332 // top parts). 4333 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 4334 LHS, RHS, DAG, dl, MVT::v4i32); 4335 4336 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 4337 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 4338 // Shift the high parts up 16 bits. 4339 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 4340 Neg16, DAG, dl); 4341 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 4342 } else if (Op.getValueType() == MVT::v8i16) { 4343 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4344 4345 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 4346 4347 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 4348 LHS, RHS, Zero, DAG, dl); 4349 } else if (Op.getValueType() == MVT::v16i8) { 4350 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4351 4352 // Multiply the even 8-bit parts, producing 16-bit sums. 4353 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 4354 LHS, RHS, DAG, dl, MVT::v8i16); 4355 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); 4356 4357 // Multiply the odd 8-bit parts, producing 16-bit sums. 4358 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 4359 LHS, RHS, DAG, dl, MVT::v8i16); 4360 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); 4361 4362 // Merge the results together. 4363 int Ops[16]; 4364 for (unsigned i = 0; i != 8; ++i) { 4365 Ops[i*2 ] = 2*i+1; 4366 Ops[i*2+1] = 2*i+1+16; 4367 } 4368 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 4369 } else { 4370 llvm_unreachable("Unknown mul to lower!"); 4371 } 4372} 4373 4374/// LowerOperation - Provide custom lowering hooks for some operations. 4375/// 4376SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 4377 switch (Op.getOpcode()) { 4378 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 4379 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4380 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4381 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 4382 case ISD::GlobalTLSAddress: llvm_unreachable("TLS not implemented for PPC"); 4383 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 4384 case ISD::SETCC: return LowerSETCC(Op, DAG); 4385 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 4386 case ISD::VASTART: 4387 return LowerVASTART(Op, DAG, PPCSubTarget); 4388 4389 case ISD::VAARG: 4390 return LowerVAARG(Op, DAG, PPCSubTarget); 4391 4392 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 4393 case ISD::DYNAMIC_STACKALLOC: 4394 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 4395 4396 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4397 case ISD::FP_TO_UINT: 4398 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 4399 Op.getDebugLoc()); 4400 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 4401 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4402 4403 // Lower 64-bit shifts. 4404 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 4405 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 4406 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 4407 4408 // Vector-related lowering. 4409 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 4410 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4411 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 4412 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 4413 case ISD::MUL: return LowerMUL(Op, DAG); 4414 4415 // Frame & Return address. 4416 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4417 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4418 } 4419 return SDValue(); 4420} 4421 4422void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 4423 SmallVectorImpl<SDValue>&Results, 4424 SelectionDAG &DAG) const { 4425 DebugLoc dl = N->getDebugLoc(); 4426 switch (N->getOpcode()) { 4427 default: 4428 assert(false && "Do not know how to custom type legalize this operation!"); 4429 return; 4430 case ISD::FP_ROUND_INREG: { 4431 assert(N->getValueType(0) == MVT::ppcf128); 4432 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 4433 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4434 MVT::f64, N->getOperand(0), 4435 DAG.getIntPtrConstant(0)); 4436 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4437 MVT::f64, N->getOperand(0), 4438 DAG.getIntPtrConstant(1)); 4439 4440 // This sequence changes FPSCR to do round-to-zero, adds the two halves 4441 // of the long double, and puts FPSCR back the way it was. We do not 4442 // actually model FPSCR. 4443 std::vector<EVT> NodeTys; 4444 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 4445 4446 NodeTys.push_back(MVT::f64); // Return register 4447 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns 4448 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4449 MFFSreg = Result.getValue(0); 4450 InFlag = Result.getValue(1); 4451 4452 NodeTys.clear(); 4453 NodeTys.push_back(MVT::Glue); // Returns a flag 4454 Ops[0] = DAG.getConstant(31, MVT::i32); 4455 Ops[1] = InFlag; 4456 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); 4457 InFlag = Result.getValue(0); 4458 4459 NodeTys.clear(); 4460 NodeTys.push_back(MVT::Glue); // Returns a flag 4461 Ops[0] = DAG.getConstant(30, MVT::i32); 4462 Ops[1] = InFlag; 4463 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); 4464 InFlag = Result.getValue(0); 4465 4466 NodeTys.clear(); 4467 NodeTys.push_back(MVT::f64); // result of add 4468 NodeTys.push_back(MVT::Glue); // Returns a flag 4469 Ops[0] = Lo; 4470 Ops[1] = Hi; 4471 Ops[2] = InFlag; 4472 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); 4473 FPreg = Result.getValue(0); 4474 InFlag = Result.getValue(1); 4475 4476 NodeTys.clear(); 4477 NodeTys.push_back(MVT::f64); 4478 Ops[0] = DAG.getConstant(1, MVT::i32); 4479 Ops[1] = MFFSreg; 4480 Ops[2] = FPreg; 4481 Ops[3] = InFlag; 4482 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); 4483 FPreg = Result.getValue(0); 4484 4485 // We know the low half is about to be thrown away, so just use something 4486 // convenient. 4487 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 4488 FPreg, FPreg)); 4489 return; 4490 } 4491 case ISD::FP_TO_SINT: 4492 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 4493 return; 4494 } 4495} 4496 4497 4498//===----------------------------------------------------------------------===// 4499// Other Lowering Code 4500//===----------------------------------------------------------------------===// 4501 4502MachineBasicBlock * 4503PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 4504 bool is64bit, unsigned BinOpcode) const { 4505 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4506 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4507 4508 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4509 MachineFunction *F = BB->getParent(); 4510 MachineFunction::iterator It = BB; 4511 ++It; 4512 4513 unsigned dest = MI->getOperand(0).getReg(); 4514 unsigned ptrA = MI->getOperand(1).getReg(); 4515 unsigned ptrB = MI->getOperand(2).getReg(); 4516 unsigned incr = MI->getOperand(3).getReg(); 4517 DebugLoc dl = MI->getDebugLoc(); 4518 4519 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4520 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4521 F->insert(It, loopMBB); 4522 F->insert(It, exitMBB); 4523 exitMBB->splice(exitMBB->begin(), BB, 4524 llvm::next(MachineBasicBlock::iterator(MI)), 4525 BB->end()); 4526 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4527 4528 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4529 unsigned TmpReg = (!BinOpcode) ? incr : 4530 RegInfo.createVirtualRegister( 4531 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4532 (const TargetRegisterClass *) &PPC::GPRCRegClass); 4533 4534 // thisMBB: 4535 // ... 4536 // fallthrough --> loopMBB 4537 BB->addSuccessor(loopMBB); 4538 4539 // loopMBB: 4540 // l[wd]arx dest, ptr 4541 // add r0, dest, incr 4542 // st[wd]cx. r0, ptr 4543 // bne- loopMBB 4544 // fallthrough --> exitMBB 4545 BB = loopMBB; 4546 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4547 .addReg(ptrA).addReg(ptrB); 4548 if (BinOpcode) 4549 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 4550 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4551 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 4552 BuildMI(BB, dl, TII->get(PPC::BCC)) 4553 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4554 BB->addSuccessor(loopMBB); 4555 BB->addSuccessor(exitMBB); 4556 4557 // exitMBB: 4558 // ... 4559 BB = exitMBB; 4560 return BB; 4561} 4562 4563MachineBasicBlock * 4564PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 4565 MachineBasicBlock *BB, 4566 bool is8bit, // operation 4567 unsigned BinOpcode) const { 4568 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4569 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4570 // In 64 bit mode we have to use 64 bits for addresses, even though the 4571 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 4572 // registers without caring whether they're 32 or 64, but here we're 4573 // doing actual arithmetic on the addresses. 4574 bool is64bit = PPCSubTarget.isPPC64(); 4575 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 4576 4577 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4578 MachineFunction *F = BB->getParent(); 4579 MachineFunction::iterator It = BB; 4580 ++It; 4581 4582 unsigned dest = MI->getOperand(0).getReg(); 4583 unsigned ptrA = MI->getOperand(1).getReg(); 4584 unsigned ptrB = MI->getOperand(2).getReg(); 4585 unsigned incr = MI->getOperand(3).getReg(); 4586 DebugLoc dl = MI->getDebugLoc(); 4587 4588 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4589 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4590 F->insert(It, loopMBB); 4591 F->insert(It, exitMBB); 4592 exitMBB->splice(exitMBB->begin(), BB, 4593 llvm::next(MachineBasicBlock::iterator(MI)), 4594 BB->end()); 4595 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4596 4597 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4598 const TargetRegisterClass *RC = 4599 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4600 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4601 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4602 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4603 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4604 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 4605 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4606 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4607 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4608 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4609 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 4610 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4611 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4612 unsigned Ptr1Reg; 4613 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 4614 4615 // thisMBB: 4616 // ... 4617 // fallthrough --> loopMBB 4618 BB->addSuccessor(loopMBB); 4619 4620 // The 4-byte load must be aligned, while a char or short may be 4621 // anywhere in the word. Hence all this nasty bookkeeping code. 4622 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4623 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4624 // xori shift, shift1, 24 [16] 4625 // rlwinm ptr, ptr1, 0, 0, 29 4626 // slw incr2, incr, shift 4627 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4628 // slw mask, mask2, shift 4629 // loopMBB: 4630 // lwarx tmpDest, ptr 4631 // add tmp, tmpDest, incr2 4632 // andc tmp2, tmpDest, mask 4633 // and tmp3, tmp, mask 4634 // or tmp4, tmp3, tmp2 4635 // stwcx. tmp4, ptr 4636 // bne- loopMBB 4637 // fallthrough --> exitMBB 4638 // srw dest, tmpDest, shift 4639 if (ptrA != ZeroReg) { 4640 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4641 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4642 .addReg(ptrA).addReg(ptrB); 4643 } else { 4644 Ptr1Reg = ptrB; 4645 } 4646 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4647 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4648 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4649 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4650 if (is64bit) 4651 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4652 .addReg(Ptr1Reg).addImm(0).addImm(61); 4653 else 4654 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4655 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4656 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 4657 .addReg(incr).addReg(ShiftReg); 4658 if (is8bit) 4659 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 4660 else { 4661 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 4662 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 4663 } 4664 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 4665 .addReg(Mask2Reg).addReg(ShiftReg); 4666 4667 BB = loopMBB; 4668 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 4669 .addReg(ZeroReg).addReg(PtrReg); 4670 if (BinOpcode) 4671 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 4672 .addReg(Incr2Reg).addReg(TmpDestReg); 4673 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 4674 .addReg(TmpDestReg).addReg(MaskReg); 4675 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 4676 .addReg(TmpReg).addReg(MaskReg); 4677 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 4678 .addReg(Tmp3Reg).addReg(Tmp2Reg); 4679 BuildMI(BB, dl, TII->get(PPC::STWCX)) 4680 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg); 4681 BuildMI(BB, dl, TII->get(PPC::BCC)) 4682 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4683 BB->addSuccessor(loopMBB); 4684 BB->addSuccessor(exitMBB); 4685 4686 // exitMBB: 4687 // ... 4688 BB = exitMBB; 4689 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg) 4690 .addReg(ShiftReg); 4691 return BB; 4692} 4693 4694MachineBasicBlock * 4695PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4696 MachineBasicBlock *BB) const { 4697 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4698 4699 // To "insert" these instructions we actually have to insert their 4700 // control-flow patterns. 4701 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4702 MachineFunction::iterator It = BB; 4703 ++It; 4704 4705 MachineFunction *F = BB->getParent(); 4706 4707 if (MI->getOpcode() == PPC::SELECT_CC_I4 || 4708 MI->getOpcode() == PPC::SELECT_CC_I8 || 4709 MI->getOpcode() == PPC::SELECT_CC_F4 || 4710 MI->getOpcode() == PPC::SELECT_CC_F8 || 4711 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 4712 4713 // The incoming instruction knows the destination vreg to set, the 4714 // condition code register to branch on, the true/false values to 4715 // select between, and a branch opcode to use. 4716 4717 // thisMBB: 4718 // ... 4719 // TrueVal = ... 4720 // cmpTY ccX, r1, r2 4721 // bCC copy1MBB 4722 // fallthrough --> copy0MBB 4723 MachineBasicBlock *thisMBB = BB; 4724 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4725 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4726 unsigned SelectPred = MI->getOperand(4).getImm(); 4727 DebugLoc dl = MI->getDebugLoc(); 4728 F->insert(It, copy0MBB); 4729 F->insert(It, sinkMBB); 4730 4731 // Transfer the remainder of BB and its successor edges to sinkMBB. 4732 sinkMBB->splice(sinkMBB->begin(), BB, 4733 llvm::next(MachineBasicBlock::iterator(MI)), 4734 BB->end()); 4735 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4736 4737 // Next, add the true and fallthrough blocks as its successors. 4738 BB->addSuccessor(copy0MBB); 4739 BB->addSuccessor(sinkMBB); 4740 4741 BuildMI(BB, dl, TII->get(PPC::BCC)) 4742 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 4743 4744 // copy0MBB: 4745 // %FalseValue = ... 4746 // # fallthrough to sinkMBB 4747 BB = copy0MBB; 4748 4749 // Update machine-CFG edges 4750 BB->addSuccessor(sinkMBB); 4751 4752 // sinkMBB: 4753 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 4754 // ... 4755 BB = sinkMBB; 4756 BuildMI(*BB, BB->begin(), dl, 4757 TII->get(PPC::PHI), MI->getOperand(0).getReg()) 4758 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 4759 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 4760 } 4761 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 4762 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 4763 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 4764 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 4765 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 4766 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 4767 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 4768 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 4769 4770 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 4771 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 4772 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 4773 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 4774 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 4775 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 4776 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 4777 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 4778 4779 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 4780 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 4781 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 4782 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 4783 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 4784 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 4785 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 4786 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 4787 4788 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 4789 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 4790 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 4791 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 4792 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 4793 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 4794 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 4795 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 4796 4797 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 4798 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 4799 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 4800 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 4801 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 4802 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 4803 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 4804 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 4805 4806 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 4807 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 4808 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 4809 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 4810 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 4811 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 4812 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 4813 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 4814 4815 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 4816 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 4817 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 4818 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 4819 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 4820 BB = EmitAtomicBinary(MI, BB, false, 0); 4821 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 4822 BB = EmitAtomicBinary(MI, BB, true, 0); 4823 4824 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 4825 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 4826 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 4827 4828 unsigned dest = MI->getOperand(0).getReg(); 4829 unsigned ptrA = MI->getOperand(1).getReg(); 4830 unsigned ptrB = MI->getOperand(2).getReg(); 4831 unsigned oldval = MI->getOperand(3).getReg(); 4832 unsigned newval = MI->getOperand(4).getReg(); 4833 DebugLoc dl = MI->getDebugLoc(); 4834 4835 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4836 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4837 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4838 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4839 F->insert(It, loop1MBB); 4840 F->insert(It, loop2MBB); 4841 F->insert(It, midMBB); 4842 F->insert(It, exitMBB); 4843 exitMBB->splice(exitMBB->begin(), BB, 4844 llvm::next(MachineBasicBlock::iterator(MI)), 4845 BB->end()); 4846 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4847 4848 // thisMBB: 4849 // ... 4850 // fallthrough --> loopMBB 4851 BB->addSuccessor(loop1MBB); 4852 4853 // loop1MBB: 4854 // l[wd]arx dest, ptr 4855 // cmp[wd] dest, oldval 4856 // bne- midMBB 4857 // loop2MBB: 4858 // st[wd]cx. newval, ptr 4859 // bne- loopMBB 4860 // b exitBB 4861 // midMBB: 4862 // st[wd]cx. dest, ptr 4863 // exitBB: 4864 BB = loop1MBB; 4865 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4866 .addReg(ptrA).addReg(ptrB); 4867 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 4868 .addReg(oldval).addReg(dest); 4869 BuildMI(BB, dl, TII->get(PPC::BCC)) 4870 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 4871 BB->addSuccessor(loop2MBB); 4872 BB->addSuccessor(midMBB); 4873 4874 BB = loop2MBB; 4875 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4876 .addReg(newval).addReg(ptrA).addReg(ptrB); 4877 BuildMI(BB, dl, TII->get(PPC::BCC)) 4878 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 4879 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 4880 BB->addSuccessor(loop1MBB); 4881 BB->addSuccessor(exitMBB); 4882 4883 BB = midMBB; 4884 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4885 .addReg(dest).addReg(ptrA).addReg(ptrB); 4886 BB->addSuccessor(exitMBB); 4887 4888 // exitMBB: 4889 // ... 4890 BB = exitMBB; 4891 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 4892 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 4893 // We must use 64-bit registers for addresses when targeting 64-bit, 4894 // since we're actually doing arithmetic on them. Other registers 4895 // can be 32-bit. 4896 bool is64bit = PPCSubTarget.isPPC64(); 4897 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 4898 4899 unsigned dest = MI->getOperand(0).getReg(); 4900 unsigned ptrA = MI->getOperand(1).getReg(); 4901 unsigned ptrB = MI->getOperand(2).getReg(); 4902 unsigned oldval = MI->getOperand(3).getReg(); 4903 unsigned newval = MI->getOperand(4).getReg(); 4904 DebugLoc dl = MI->getDebugLoc(); 4905 4906 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4907 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4908 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4909 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4910 F->insert(It, loop1MBB); 4911 F->insert(It, loop2MBB); 4912 F->insert(It, midMBB); 4913 F->insert(It, exitMBB); 4914 exitMBB->splice(exitMBB->begin(), BB, 4915 llvm::next(MachineBasicBlock::iterator(MI)), 4916 BB->end()); 4917 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4918 4919 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4920 const TargetRegisterClass *RC = 4921 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4922 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4923 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4924 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4925 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4926 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 4927 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 4928 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 4929 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 4930 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4931 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4932 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4933 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4934 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4935 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4936 unsigned Ptr1Reg; 4937 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 4938 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 4939 // thisMBB: 4940 // ... 4941 // fallthrough --> loopMBB 4942 BB->addSuccessor(loop1MBB); 4943 4944 // The 4-byte load must be aligned, while a char or short may be 4945 // anywhere in the word. Hence all this nasty bookkeeping code. 4946 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4947 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4948 // xori shift, shift1, 24 [16] 4949 // rlwinm ptr, ptr1, 0, 0, 29 4950 // slw newval2, newval, shift 4951 // slw oldval2, oldval,shift 4952 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4953 // slw mask, mask2, shift 4954 // and newval3, newval2, mask 4955 // and oldval3, oldval2, mask 4956 // loop1MBB: 4957 // lwarx tmpDest, ptr 4958 // and tmp, tmpDest, mask 4959 // cmpw tmp, oldval3 4960 // bne- midMBB 4961 // loop2MBB: 4962 // andc tmp2, tmpDest, mask 4963 // or tmp4, tmp2, newval3 4964 // stwcx. tmp4, ptr 4965 // bne- loop1MBB 4966 // b exitBB 4967 // midMBB: 4968 // stwcx. tmpDest, ptr 4969 // exitBB: 4970 // srw dest, tmpDest, shift 4971 if (ptrA != ZeroReg) { 4972 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4973 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4974 .addReg(ptrA).addReg(ptrB); 4975 } else { 4976 Ptr1Reg = ptrB; 4977 } 4978 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4979 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4980 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4981 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4982 if (is64bit) 4983 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4984 .addReg(Ptr1Reg).addImm(0).addImm(61); 4985 else 4986 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4987 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4988 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 4989 .addReg(newval).addReg(ShiftReg); 4990 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 4991 .addReg(oldval).addReg(ShiftReg); 4992 if (is8bit) 4993 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 4994 else { 4995 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 4996 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 4997 .addReg(Mask3Reg).addImm(65535); 4998 } 4999 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 5000 .addReg(Mask2Reg).addReg(ShiftReg); 5001 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 5002 .addReg(NewVal2Reg).addReg(MaskReg); 5003 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 5004 .addReg(OldVal2Reg).addReg(MaskReg); 5005 5006 BB = loop1MBB; 5007 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 5008 .addReg(ZeroReg).addReg(PtrReg); 5009 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 5010 .addReg(TmpDestReg).addReg(MaskReg); 5011 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 5012 .addReg(TmpReg).addReg(OldVal3Reg); 5013 BuildMI(BB, dl, TII->get(PPC::BCC)) 5014 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 5015 BB->addSuccessor(loop2MBB); 5016 BB->addSuccessor(midMBB); 5017 5018 BB = loop2MBB; 5019 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 5020 .addReg(TmpDestReg).addReg(MaskReg); 5021 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 5022 .addReg(Tmp2Reg).addReg(NewVal3Reg); 5023 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 5024 .addReg(ZeroReg).addReg(PtrReg); 5025 BuildMI(BB, dl, TII->get(PPC::BCC)) 5026 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 5027 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 5028 BB->addSuccessor(loop1MBB); 5029 BB->addSuccessor(exitMBB); 5030 5031 BB = midMBB; 5032 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 5033 .addReg(ZeroReg).addReg(PtrReg); 5034 BB->addSuccessor(exitMBB); 5035 5036 // exitMBB: 5037 // ... 5038 BB = exitMBB; 5039 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) 5040 .addReg(ShiftReg); 5041 } else { 5042 llvm_unreachable("Unexpected instr type to insert"); 5043 } 5044 5045 MI->eraseFromParent(); // The pseudo instruction is gone now. 5046 return BB; 5047} 5048 5049//===----------------------------------------------------------------------===// 5050// Target Optimization Hooks 5051//===----------------------------------------------------------------------===// 5052 5053SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 5054 DAGCombinerInfo &DCI) const { 5055 const TargetMachine &TM = getTargetMachine(); 5056 SelectionDAG &DAG = DCI.DAG; 5057 DebugLoc dl = N->getDebugLoc(); 5058 switch (N->getOpcode()) { 5059 default: break; 5060 case PPCISD::SHL: 5061 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5062 if (C->isNullValue()) // 0 << V -> 0. 5063 return N->getOperand(0); 5064 } 5065 break; 5066 case PPCISD::SRL: 5067 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5068 if (C->isNullValue()) // 0 >>u V -> 0. 5069 return N->getOperand(0); 5070 } 5071 break; 5072 case PPCISD::SRA: 5073 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5074 if (C->isNullValue() || // 0 >>s V -> 0. 5075 C->isAllOnesValue()) // -1 >>s V -> -1. 5076 return N->getOperand(0); 5077 } 5078 break; 5079 5080 case ISD::SINT_TO_FP: 5081 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 5082 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 5083 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 5084 // We allow the src/dst to be either f32/f64, but the intermediate 5085 // type must be i64. 5086 if (N->getOperand(0).getValueType() == MVT::i64 && 5087 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 5088 SDValue Val = N->getOperand(0).getOperand(0); 5089 if (Val.getValueType() == MVT::f32) { 5090 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5091 DCI.AddToWorklist(Val.getNode()); 5092 } 5093 5094 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 5095 DCI.AddToWorklist(Val.getNode()); 5096 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 5097 DCI.AddToWorklist(Val.getNode()); 5098 if (N->getValueType(0) == MVT::f32) { 5099 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 5100 DAG.getIntPtrConstant(0)); 5101 DCI.AddToWorklist(Val.getNode()); 5102 } 5103 return Val; 5104 } else if (N->getOperand(0).getValueType() == MVT::i32) { 5105 // If the intermediate type is i32, we can avoid the load/store here 5106 // too. 5107 } 5108 } 5109 } 5110 break; 5111 case ISD::STORE: 5112 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 5113 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 5114 !cast<StoreSDNode>(N)->isTruncatingStore() && 5115 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 5116 N->getOperand(1).getValueType() == MVT::i32 && 5117 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 5118 SDValue Val = N->getOperand(1).getOperand(0); 5119 if (Val.getValueType() == MVT::f32) { 5120 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5121 DCI.AddToWorklist(Val.getNode()); 5122 } 5123 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 5124 DCI.AddToWorklist(Val.getNode()); 5125 5126 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 5127 N->getOperand(2), N->getOperand(3)); 5128 DCI.AddToWorklist(Val.getNode()); 5129 return Val; 5130 } 5131 5132 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 5133 if (cast<StoreSDNode>(N)->isUnindexed() && 5134 N->getOperand(1).getOpcode() == ISD::BSWAP && 5135 N->getOperand(1).getNode()->hasOneUse() && 5136 (N->getOperand(1).getValueType() == MVT::i32 || 5137 N->getOperand(1).getValueType() == MVT::i16)) { 5138 SDValue BSwapOp = N->getOperand(1).getOperand(0); 5139 // Do an any-extend to 32-bits if this is a half-word input. 5140 if (BSwapOp.getValueType() == MVT::i16) 5141 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 5142 5143 SDValue Ops[] = { 5144 N->getOperand(0), BSwapOp, N->getOperand(2), 5145 DAG.getValueType(N->getOperand(1).getValueType()) 5146 }; 5147 return 5148 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 5149 Ops, array_lengthof(Ops), 5150 cast<StoreSDNode>(N)->getMemoryVT(), 5151 cast<StoreSDNode>(N)->getMemOperand()); 5152 } 5153 break; 5154 case ISD::BSWAP: 5155 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 5156 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 5157 N->getOperand(0).hasOneUse() && 5158 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 5159 SDValue Load = N->getOperand(0); 5160 LoadSDNode *LD = cast<LoadSDNode>(Load); 5161 // Create the byte-swapping load. 5162 SDValue Ops[] = { 5163 LD->getChain(), // Chain 5164 LD->getBasePtr(), // Ptr 5165 DAG.getValueType(N->getValueType(0)) // VT 5166 }; 5167 SDValue BSLoad = 5168 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 5169 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3, 5170 LD->getMemoryVT(), LD->getMemOperand()); 5171 5172 // If this is an i16 load, insert the truncate. 5173 SDValue ResVal = BSLoad; 5174 if (N->getValueType(0) == MVT::i16) 5175 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 5176 5177 // First, combine the bswap away. This makes the value produced by the 5178 // load dead. 5179 DCI.CombineTo(N, ResVal); 5180 5181 // Next, combine the load away, we give it a bogus result value but a real 5182 // chain result. The result value is dead because the bswap is dead. 5183 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 5184 5185 // Return N so it doesn't get rechecked! 5186 return SDValue(N, 0); 5187 } 5188 5189 break; 5190 case PPCISD::VCMP: { 5191 // If a VCMPo node already exists with exactly the same operands as this 5192 // node, use its result instead of this node (VCMPo computes both a CR6 and 5193 // a normal output). 5194 // 5195 if (!N->getOperand(0).hasOneUse() && 5196 !N->getOperand(1).hasOneUse() && 5197 !N->getOperand(2).hasOneUse()) { 5198 5199 // Scan all of the users of the LHS, looking for VCMPo's that match. 5200 SDNode *VCMPoNode = 0; 5201 5202 SDNode *LHSN = N->getOperand(0).getNode(); 5203 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 5204 UI != E; ++UI) 5205 if (UI->getOpcode() == PPCISD::VCMPo && 5206 UI->getOperand(1) == N->getOperand(1) && 5207 UI->getOperand(2) == N->getOperand(2) && 5208 UI->getOperand(0) == N->getOperand(0)) { 5209 VCMPoNode = *UI; 5210 break; 5211 } 5212 5213 // If there is no VCMPo node, or if the flag value has a single use, don't 5214 // transform this. 5215 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 5216 break; 5217 5218 // Look at the (necessarily single) use of the flag value. If it has a 5219 // chain, this transformation is more complex. Note that multiple things 5220 // could use the value result, which we should ignore. 5221 SDNode *FlagUser = 0; 5222 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 5223 FlagUser == 0; ++UI) { 5224 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 5225 SDNode *User = *UI; 5226 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 5227 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 5228 FlagUser = User; 5229 break; 5230 } 5231 } 5232 } 5233 5234 // If the user is a MFCR instruction, we know this is safe. Otherwise we 5235 // give up for right now. 5236 if (FlagUser->getOpcode() == PPCISD::MFCR) 5237 return SDValue(VCMPoNode, 0); 5238 } 5239 break; 5240 } 5241 case ISD::BR_CC: { 5242 // If this is a branch on an altivec predicate comparison, lower this so 5243 // that we don't have to do a MFCR: instead, branch directly on CR6. This 5244 // lowering is done pre-legalize, because the legalizer lowers the predicate 5245 // compare down to code that is difficult to reassemble. 5246 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 5247 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 5248 int CompareOpc; 5249 bool isDot; 5250 5251 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 5252 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 5253 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 5254 assert(isDot && "Can't compare against a vector result!"); 5255 5256 // If this is a comparison against something other than 0/1, then we know 5257 // that the condition is never/always true. 5258 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 5259 if (Val != 0 && Val != 1) { 5260 if (CC == ISD::SETEQ) // Cond never true, remove branch. 5261 return N->getOperand(0); 5262 // Always !=, turn it into an unconditional branch. 5263 return DAG.getNode(ISD::BR, dl, MVT::Other, 5264 N->getOperand(0), N->getOperand(4)); 5265 } 5266 5267 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 5268 5269 // Create the PPCISD altivec 'dot' comparison node. 5270 std::vector<EVT> VTs; 5271 SDValue Ops[] = { 5272 LHS.getOperand(2), // LHS of compare 5273 LHS.getOperand(3), // RHS of compare 5274 DAG.getConstant(CompareOpc, MVT::i32) 5275 }; 5276 VTs.push_back(LHS.getOperand(2).getValueType()); 5277 VTs.push_back(MVT::Glue); 5278 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5279 5280 // Unpack the result based on how the target uses it. 5281 PPC::Predicate CompOpc; 5282 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 5283 default: // Can't happen, don't crash on invalid number though. 5284 case 0: // Branch on the value of the EQ bit of CR6. 5285 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 5286 break; 5287 case 1: // Branch on the inverted value of the EQ bit of CR6. 5288 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 5289 break; 5290 case 2: // Branch on the value of the LT bit of CR6. 5291 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 5292 break; 5293 case 3: // Branch on the inverted value of the LT bit of CR6. 5294 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 5295 break; 5296 } 5297 5298 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 5299 DAG.getConstant(CompOpc, MVT::i32), 5300 DAG.getRegister(PPC::CR6, MVT::i32), 5301 N->getOperand(4), CompNode.getValue(1)); 5302 } 5303 break; 5304 } 5305 } 5306 5307 return SDValue(); 5308} 5309 5310//===----------------------------------------------------------------------===// 5311// Inline Assembly Support 5312//===----------------------------------------------------------------------===// 5313 5314void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 5315 const APInt &Mask, 5316 APInt &KnownZero, 5317 APInt &KnownOne, 5318 const SelectionDAG &DAG, 5319 unsigned Depth) const { 5320 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 5321 switch (Op.getOpcode()) { 5322 default: break; 5323 case PPCISD::LBRX: { 5324 // lhbrx is known to have the top bits cleared out. 5325 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 5326 KnownZero = 0xFFFF0000; 5327 break; 5328 } 5329 case ISD::INTRINSIC_WO_CHAIN: { 5330 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 5331 default: break; 5332 case Intrinsic::ppc_altivec_vcmpbfp_p: 5333 case Intrinsic::ppc_altivec_vcmpeqfp_p: 5334 case Intrinsic::ppc_altivec_vcmpequb_p: 5335 case Intrinsic::ppc_altivec_vcmpequh_p: 5336 case Intrinsic::ppc_altivec_vcmpequw_p: 5337 case Intrinsic::ppc_altivec_vcmpgefp_p: 5338 case Intrinsic::ppc_altivec_vcmpgtfp_p: 5339 case Intrinsic::ppc_altivec_vcmpgtsb_p: 5340 case Intrinsic::ppc_altivec_vcmpgtsh_p: 5341 case Intrinsic::ppc_altivec_vcmpgtsw_p: 5342 case Intrinsic::ppc_altivec_vcmpgtub_p: 5343 case Intrinsic::ppc_altivec_vcmpgtuh_p: 5344 case Intrinsic::ppc_altivec_vcmpgtuw_p: 5345 KnownZero = ~1U; // All bits but the low one are known to be zero. 5346 break; 5347 } 5348 } 5349 } 5350} 5351 5352 5353/// getConstraintType - Given a constraint, return the type of 5354/// constraint it is for this target. 5355PPCTargetLowering::ConstraintType 5356PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 5357 if (Constraint.size() == 1) { 5358 switch (Constraint[0]) { 5359 default: break; 5360 case 'b': 5361 case 'r': 5362 case 'f': 5363 case 'v': 5364 case 'y': 5365 return C_RegisterClass; 5366 } 5367 } 5368 return TargetLowering::getConstraintType(Constraint); 5369} 5370 5371/// Examine constraint type and operand type and determine a weight value. 5372/// This object must already have been set up with the operand type 5373/// and the current alternative constraint selected. 5374TargetLowering::ConstraintWeight 5375PPCTargetLowering::getSingleConstraintMatchWeight( 5376 AsmOperandInfo &info, const char *constraint) const { 5377 ConstraintWeight weight = CW_Invalid; 5378 Value *CallOperandVal = info.CallOperandVal; 5379 // If we don't have a value, we can't do a match, 5380 // but allow it at the lowest weight. 5381 if (CallOperandVal == NULL) 5382 return CW_Default; 5383 const Type *type = CallOperandVal->getType(); 5384 // Look at the constraint type. 5385 switch (*constraint) { 5386 default: 5387 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 5388 break; 5389 case 'b': 5390 if (type->isIntegerTy()) 5391 weight = CW_Register; 5392 break; 5393 case 'f': 5394 if (type->isFloatTy()) 5395 weight = CW_Register; 5396 break; 5397 case 'd': 5398 if (type->isDoubleTy()) 5399 weight = CW_Register; 5400 break; 5401 case 'v': 5402 if (type->isVectorTy()) 5403 weight = CW_Register; 5404 break; 5405 case 'y': 5406 weight = CW_Register; 5407 break; 5408 } 5409 return weight; 5410} 5411 5412std::pair<unsigned, const TargetRegisterClass*> 5413PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 5414 EVT VT) const { 5415 if (Constraint.size() == 1) { 5416 // GCC RS6000 Constraint Letters 5417 switch (Constraint[0]) { 5418 case 'b': // R1-R31 5419 case 'r': // R0-R31 5420 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 5421 return std::make_pair(0U, PPC::G8RCRegisterClass); 5422 return std::make_pair(0U, PPC::GPRCRegisterClass); 5423 case 'f': 5424 if (VT == MVT::f32) 5425 return std::make_pair(0U, PPC::F4RCRegisterClass); 5426 else if (VT == MVT::f64) 5427 return std::make_pair(0U, PPC::F8RCRegisterClass); 5428 break; 5429 case 'v': 5430 return std::make_pair(0U, PPC::VRRCRegisterClass); 5431 case 'y': // crrc 5432 return std::make_pair(0U, PPC::CRRCRegisterClass); 5433 } 5434 } 5435 5436 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5437} 5438 5439 5440/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 5441/// vector. If it is invalid, don't add anything to Ops. 5442void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 5443 std::string &Constraint, 5444 std::vector<SDValue>&Ops, 5445 SelectionDAG &DAG) const { 5446 SDValue Result(0,0); 5447 5448 // Only support length 1 constraints. 5449 if (Constraint.length() > 1) return; 5450 5451 char Letter = Constraint[0]; 5452 switch (Letter) { 5453 default: break; 5454 case 'I': 5455 case 'J': 5456 case 'K': 5457 case 'L': 5458 case 'M': 5459 case 'N': 5460 case 'O': 5461 case 'P': { 5462 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 5463 if (!CST) return; // Must be an immediate to match. 5464 unsigned Value = CST->getZExtValue(); 5465 switch (Letter) { 5466 default: llvm_unreachable("Unknown constraint letter!"); 5467 case 'I': // "I" is a signed 16-bit constant. 5468 if ((short)Value == (int)Value) 5469 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5470 break; 5471 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 5472 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 5473 if ((short)Value == 0) 5474 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5475 break; 5476 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 5477 if ((Value >> 16) == 0) 5478 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5479 break; 5480 case 'M': // "M" is a constant that is greater than 31. 5481 if (Value > 31) 5482 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5483 break; 5484 case 'N': // "N" is a positive constant that is an exact power of two. 5485 if ((int)Value > 0 && isPowerOf2_32(Value)) 5486 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5487 break; 5488 case 'O': // "O" is the constant zero. 5489 if (Value == 0) 5490 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5491 break; 5492 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 5493 if ((short)-Value == (int)-Value) 5494 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5495 break; 5496 } 5497 break; 5498 } 5499 } 5500 5501 if (Result.getNode()) { 5502 Ops.push_back(Result); 5503 return; 5504 } 5505 5506 // Handle standard constraint letters. 5507 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 5508} 5509 5510// isLegalAddressingMode - Return true if the addressing mode represented 5511// by AM is legal for this target, for a load/store of the specified type. 5512bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 5513 const Type *Ty) const { 5514 // FIXME: PPC does not allow r+i addressing modes for vectors! 5515 5516 // PPC allows a sign-extended 16-bit immediate field. 5517 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 5518 return false; 5519 5520 // No global is ever allowed as a base. 5521 if (AM.BaseGV) 5522 return false; 5523 5524 // PPC only support r+r, 5525 switch (AM.Scale) { 5526 case 0: // "r+i" or just "i", depending on HasBaseReg. 5527 break; 5528 case 1: 5529 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 5530 return false; 5531 // Otherwise we have r+r or r+i. 5532 break; 5533 case 2: 5534 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 5535 return false; 5536 // Allow 2*r as r+r. 5537 break; 5538 default: 5539 // No other scales are supported. 5540 return false; 5541 } 5542 5543 return true; 5544} 5545 5546/// isLegalAddressImmediate - Return true if the integer value can be used 5547/// as the offset of the target addressing mode for load / store of the 5548/// given type. 5549bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 5550 // PPC allows a sign-extended 16-bit immediate field. 5551 return (V > -(1 << 16) && V < (1 << 16)-1); 5552} 5553 5554bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 5555 return false; 5556} 5557 5558SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, 5559 SelectionDAG &DAG) const { 5560 MachineFunction &MF = DAG.getMachineFunction(); 5561 MachineFrameInfo *MFI = MF.getFrameInfo(); 5562 MFI->setReturnAddressIsTaken(true); 5563 5564 DebugLoc dl = Op.getDebugLoc(); 5565 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5566 5567 // Make sure the function does not optimize away the store of the RA to 5568 // the stack. 5569 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 5570 FuncInfo->setLRStoreRequired(); 5571 bool isPPC64 = PPCSubTarget.isPPC64(); 5572 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 5573 5574 if (Depth > 0) { 5575 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 5576 SDValue Offset = 5577 5578 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI), 5579 isPPC64? MVT::i64 : MVT::i32); 5580 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5581 DAG.getNode(ISD::ADD, dl, getPointerTy(), 5582 FrameAddr, Offset), 5583 MachinePointerInfo(), false, false, 0); 5584 } 5585 5586 // Just load the return address off the stack. 5587 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 5588 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5589 RetAddrFI, MachinePointerInfo(), false, false, 0); 5590} 5591 5592SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, 5593 SelectionDAG &DAG) const { 5594 DebugLoc dl = Op.getDebugLoc(); 5595 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5596 5597 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 5598 bool isPPC64 = PtrVT == MVT::i64; 5599 5600 MachineFunction &MF = DAG.getMachineFunction(); 5601 MachineFrameInfo *MFI = MF.getFrameInfo(); 5602 MFI->setFrameAddressIsTaken(true); 5603 bool is31 = (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()) && 5604 MFI->getStackSize() && 5605 !MF.getFunction()->hasFnAttr(Attribute::Naked); 5606 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) : 5607 (is31 ? PPC::R31 : PPC::R1); 5608 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, 5609 PtrVT); 5610 while (Depth--) 5611 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), 5612 FrameAddr, MachinePointerInfo(), false, false, 0); 5613 return FrameAddr; 5614} 5615 5616bool 5617PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 5618 // The PowerPC target isn't yet aware of offsets. 5619 return false; 5620} 5621 5622/// getOptimalMemOpType - Returns the target specific optimal type for load 5623/// and store operations as a result of memset, memcpy, and memmove 5624/// lowering. If DstAlign is zero that means it's safe to destination 5625/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 5626/// means there isn't a need to check it against alignment requirement, 5627/// probably because the source does not need to be loaded. If 5628/// 'NonScalarIntSafe' is true, that means it's safe to return a 5629/// non-scalar-integer type, e.g. empty string source, constant, or loaded 5630/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 5631/// constant so it does not need to be loaded. 5632/// It returns EVT::Other if the type should be determined using generic 5633/// target-independent logic. 5634EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, 5635 unsigned DstAlign, unsigned SrcAlign, 5636 bool NonScalarIntSafe, 5637 bool MemcpyStrSrc, 5638 MachineFunction &MF) const { 5639 if (this->PPCSubTarget.isPPC64()) { 5640 return MVT::i64; 5641 } else { 5642 return MVT::i32; 5643 } 5644} 5645