PPCISelLowering.cpp revision 1db3c92306f551a81440dffd88ce07b9fbea97f4
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPredicates.h" 17#include "PPCTargetMachine.h" 18#include "PPCPerfectShuffle.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/Function.h" 31#include "llvm/Intrinsics.h" 32#include "llvm/ParameterAttributes.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/Support/CommandLine.h" 36using namespace llvm; 37 38static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 39cl::desc("enable preincrement load/store generation on PPC (experimental)"), 40 cl::Hidden); 41 42PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 43 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { 44 45 setPow2DivIsCheap(); 46 47 // Use _setjmp/_longjmp instead of setjmp/longjmp. 48 setUseUnderscoreSetJmp(true); 49 setUseUnderscoreLongJmp(true); 50 51 // Set up the register classes. 52 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 53 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 54 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 55 56 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 57 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 58 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); 59 60 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 61 62 // PowerPC has pre-inc load and store's. 63 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 64 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 65 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 66 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 67 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 68 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 69 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 70 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 71 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 72 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 73 74 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg) 75 setConvertAction(MVT::ppcf128, MVT::f64, Expand); 76 setConvertAction(MVT::ppcf128, MVT::f32, Expand); 77 // This is used in the ppcf128->int sequence. Note it has different semantics 78 // from FP_ROUND: that rounds to nearest, this rounds to zero. 79 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 80 81 // PowerPC has no intrinsics for these particular operations 82 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 83 84 // PowerPC has no SREM/UREM instructions 85 setOperationAction(ISD::SREM, MVT::i32, Expand); 86 setOperationAction(ISD::UREM, MVT::i32, Expand); 87 setOperationAction(ISD::SREM, MVT::i64, Expand); 88 setOperationAction(ISD::UREM, MVT::i64, Expand); 89 90 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 91 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 92 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 93 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 94 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 95 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 96 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 97 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 98 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 99 100 // We don't support sin/cos/sqrt/fmod/pow 101 setOperationAction(ISD::FSIN , MVT::f64, Expand); 102 setOperationAction(ISD::FCOS , MVT::f64, Expand); 103 setOperationAction(ISD::FREM , MVT::f64, Expand); 104 setOperationAction(ISD::FPOW , MVT::f64, Expand); 105 setOperationAction(ISD::FSIN , MVT::f32, Expand); 106 setOperationAction(ISD::FCOS , MVT::f32, Expand); 107 setOperationAction(ISD::FREM , MVT::f32, Expand); 108 setOperationAction(ISD::FPOW , MVT::f32, Expand); 109 110 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 111 112 // If we're enabling GP optimizations, use hardware square root 113 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 114 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 115 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 116 } 117 118 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 119 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 120 121 // PowerPC does not have BSWAP, CTPOP or CTTZ 122 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 123 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 124 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 125 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 126 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 127 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 128 129 // PowerPC does not have ROTR 130 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 131 132 // PowerPC does not have Select 133 setOperationAction(ISD::SELECT, MVT::i32, Expand); 134 setOperationAction(ISD::SELECT, MVT::i64, Expand); 135 setOperationAction(ISD::SELECT, MVT::f32, Expand); 136 setOperationAction(ISD::SELECT, MVT::f64, Expand); 137 138 // PowerPC wants to turn select_cc of FP into fsel when possible. 139 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 140 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 141 142 // PowerPC wants to optimize integer setcc a bit 143 setOperationAction(ISD::SETCC, MVT::i32, Custom); 144 145 // PowerPC does not have BRCOND which requires SetCC 146 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 147 148 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 149 150 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 151 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 152 153 // PowerPC does not have [U|S]INT_TO_FP 154 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 155 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 156 157 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 158 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 159 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 160 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 161 162 // We cannot sextinreg(i1). Expand to shifts. 163 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 164 165 // Support label based line numbers. 166 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 167 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 168 169 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 170 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 171 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 172 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 173 174 175 // We want to legalize GlobalAddress and ConstantPool nodes into the 176 // appropriate instructions to materialize the address. 177 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 178 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 179 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 180 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 181 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 182 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 183 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 184 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 185 186 // RET must be custom lowered, to meet ABI requirements. 187 setOperationAction(ISD::RET , MVT::Other, Custom); 188 189 // TRAP is legal. 190 setOperationAction(ISD::TRAP, MVT::Other, Legal); 191 192 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 193 setOperationAction(ISD::VASTART , MVT::Other, Custom); 194 195 // VAARG is custom lowered with ELF 32 ABI 196 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI()) 197 setOperationAction(ISD::VAARG, MVT::Other, Custom); 198 else 199 setOperationAction(ISD::VAARG, MVT::Other, Expand); 200 201 // Use the default implementation. 202 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 203 setOperationAction(ISD::VAEND , MVT::Other, Expand); 204 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 205 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 208 209 setOperationAction(ISD::ATOMIC_LOAD_ADD , MVT::i32 , Custom); 210 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i32 , Custom); 211 setOperationAction(ISD::ATOMIC_SWAP , MVT::i32 , Custom); 212 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 213 setOperationAction(ISD::ATOMIC_LOAD_ADD , MVT::i64 , Custom); 214 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i64 , Custom); 215 setOperationAction(ISD::ATOMIC_SWAP , MVT::i64 , Custom); 216 } 217 218 // We want to custom lower some of our intrinsics. 219 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 220 221 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 222 // They also have instructions for converting between i64 and fp. 223 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 224 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 225 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 226 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 227 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 228 229 // FIXME: disable this lowered code. This generates 64-bit register values, 230 // and we don't model the fact that the top part is clobbered by calls. We 231 // need to flag these together so that the value isn't live across a call. 232 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 233 234 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 235 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 236 } else { 237 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 238 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 239 } 240 241 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 242 // 64-bit PowerPC implementations can support i64 types directly 243 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 244 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 245 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 246 // 64-bit PowerPC wants to expand i128 shifts itself. 247 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 248 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 249 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 250 } else { 251 // 32-bit PowerPC wants to expand i64 shifts itself. 252 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 253 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 254 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 255 } 256 257 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 258 // First set operation action for all vector types to expand. Then we 259 // will selectively turn on ones that can be effectively codegen'd. 260 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 261 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 262 MVT VT = (MVT::SimpleValueType)i; 263 264 // add/sub are legal for all supported vector VT's. 265 setOperationAction(ISD::ADD , VT, Legal); 266 setOperationAction(ISD::SUB , VT, Legal); 267 268 // We promote all shuffles to v16i8. 269 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 270 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 271 272 // We promote all non-typed operations to v4i32. 273 setOperationAction(ISD::AND , VT, Promote); 274 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 275 setOperationAction(ISD::OR , VT, Promote); 276 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 277 setOperationAction(ISD::XOR , VT, Promote); 278 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 279 setOperationAction(ISD::LOAD , VT, Promote); 280 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 281 setOperationAction(ISD::SELECT, VT, Promote); 282 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 283 setOperationAction(ISD::STORE, VT, Promote); 284 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 285 286 // No other operations are legal. 287 setOperationAction(ISD::MUL , VT, Expand); 288 setOperationAction(ISD::SDIV, VT, Expand); 289 setOperationAction(ISD::SREM, VT, Expand); 290 setOperationAction(ISD::UDIV, VT, Expand); 291 setOperationAction(ISD::UREM, VT, Expand); 292 setOperationAction(ISD::FDIV, VT, Expand); 293 setOperationAction(ISD::FNEG, VT, Expand); 294 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 295 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 296 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 297 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 298 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 299 setOperationAction(ISD::UDIVREM, VT, Expand); 300 setOperationAction(ISD::SDIVREM, VT, Expand); 301 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 302 setOperationAction(ISD::FPOW, VT, Expand); 303 setOperationAction(ISD::CTPOP, VT, Expand); 304 setOperationAction(ISD::CTLZ, VT, Expand); 305 setOperationAction(ISD::CTTZ, VT, Expand); 306 } 307 308 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 309 // with merges, splats, etc. 310 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 311 312 setOperationAction(ISD::AND , MVT::v4i32, Legal); 313 setOperationAction(ISD::OR , MVT::v4i32, Legal); 314 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 315 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 316 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 317 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 318 319 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 320 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 321 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 322 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 323 324 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 325 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 326 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 327 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 328 329 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 330 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 331 332 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 333 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 334 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 335 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 336 } 337 338 setShiftAmountType(MVT::i32); 339 setSetCCResultContents(ZeroOrOneSetCCResult); 340 341 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 342 setStackPointerRegisterToSaveRestore(PPC::X1); 343 setExceptionPointerRegister(PPC::X3); 344 setExceptionSelectorRegister(PPC::X4); 345 } else { 346 setStackPointerRegisterToSaveRestore(PPC::R1); 347 setExceptionPointerRegister(PPC::R3); 348 setExceptionSelectorRegister(PPC::R4); 349 } 350 351 // We have target-specific dag combine patterns for the following nodes: 352 setTargetDAGCombine(ISD::SINT_TO_FP); 353 setTargetDAGCombine(ISD::STORE); 354 setTargetDAGCombine(ISD::BR_CC); 355 setTargetDAGCombine(ISD::BSWAP); 356 357 // Darwin long double math library functions have $LDBL128 appended. 358 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 359 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 360 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 361 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 362 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 363 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 364 } 365 366 computeRegisterProperties(); 367} 368 369/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 370/// function arguments in the caller parameter area. 371unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const { 372 TargetMachine &TM = getTargetMachine(); 373 // Darwin passes everything on 4 byte boundary. 374 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 375 return 4; 376 // FIXME Elf TBD 377 return 4; 378} 379 380const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 381 switch (Opcode) { 382 default: return 0; 383 case PPCISD::FSEL: return "PPCISD::FSEL"; 384 case PPCISD::FCFID: return "PPCISD::FCFID"; 385 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 386 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 387 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 388 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 389 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 390 case PPCISD::VPERM: return "PPCISD::VPERM"; 391 case PPCISD::Hi: return "PPCISD::Hi"; 392 case PPCISD::Lo: return "PPCISD::Lo"; 393 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 394 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 395 case PPCISD::SRL: return "PPCISD::SRL"; 396 case PPCISD::SRA: return "PPCISD::SRA"; 397 case PPCISD::SHL: return "PPCISD::SHL"; 398 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 399 case PPCISD::STD_32: return "PPCISD::STD_32"; 400 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF"; 401 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; 402 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 403 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; 404 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; 405 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 406 case PPCISD::MFCR: return "PPCISD::MFCR"; 407 case PPCISD::VCMP: return "PPCISD::VCMP"; 408 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 409 case PPCISD::LBRX: return "PPCISD::LBRX"; 410 case PPCISD::STBRX: return "PPCISD::STBRX"; 411 case PPCISD::ATOMIC_LOAD_ADD: return "PPCISD::ATOMIC_LOAD_ADD"; 412 case PPCISD::ATOMIC_CMP_SWAP: return "PPCISD::ATOMIC_CMP_SWAP"; 413 case PPCISD::ATOMIC_SWAP: return "PPCISD::ATOMIC_SWAP"; 414 case PPCISD::LARX: return "PPCISD::LARX"; 415 case PPCISD::STCX: return "PPCISD::STCX"; 416 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 417 case PPCISD::MFFS: return "PPCISD::MFFS"; 418 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 419 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 420 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 421 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 422 case PPCISD::TAILCALL: return "PPCISD::TAILCALL"; 423 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 424 } 425} 426 427 428MVT PPCTargetLowering::getSetCCResultType(const SDValue &) const { 429 return MVT::i32; 430} 431 432 433//===----------------------------------------------------------------------===// 434// Node matching predicates, for use by the tblgen matching code. 435//===----------------------------------------------------------------------===// 436 437/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 438static bool isFloatingPointZero(SDValue Op) { 439 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 440 return CFP->getValueAPF().isZero(); 441 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 442 // Maybe this has already been legalized into the constant pool? 443 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 444 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 445 return CFP->getValueAPF().isZero(); 446 } 447 return false; 448} 449 450/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 451/// true if Op is undef or if it matches the specified value. 452static bool isConstantOrUndef(SDValue Op, unsigned Val) { 453 return Op.getOpcode() == ISD::UNDEF || 454 cast<ConstantSDNode>(Op)->getValue() == Val; 455} 456 457/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 458/// VPKUHUM instruction. 459bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 460 if (!isUnary) { 461 for (unsigned i = 0; i != 16; ++i) 462 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 463 return false; 464 } else { 465 for (unsigned i = 0; i != 8; ++i) 466 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 467 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 468 return false; 469 } 470 return true; 471} 472 473/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 474/// VPKUWUM instruction. 475bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 476 if (!isUnary) { 477 for (unsigned i = 0; i != 16; i += 2) 478 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 479 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 480 return false; 481 } else { 482 for (unsigned i = 0; i != 8; i += 2) 483 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 484 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 485 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 486 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 487 return false; 488 } 489 return true; 490} 491 492/// isVMerge - Common function, used to match vmrg* shuffles. 493/// 494static bool isVMerge(SDNode *N, unsigned UnitSize, 495 unsigned LHSStart, unsigned RHSStart) { 496 assert(N->getOpcode() == ISD::BUILD_VECTOR && 497 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 498 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 499 "Unsupported merge size!"); 500 501 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 502 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 503 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 504 LHSStart+j+i*UnitSize) || 505 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 506 RHSStart+j+i*UnitSize)) 507 return false; 508 } 509 return true; 510} 511 512/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 513/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 514bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 515 if (!isUnary) 516 return isVMerge(N, UnitSize, 8, 24); 517 return isVMerge(N, UnitSize, 8, 8); 518} 519 520/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 521/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 522bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 523 if (!isUnary) 524 return isVMerge(N, UnitSize, 0, 16); 525 return isVMerge(N, UnitSize, 0, 0); 526} 527 528 529/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 530/// amount, otherwise return -1. 531int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 532 assert(N->getOpcode() == ISD::BUILD_VECTOR && 533 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 534 // Find the first non-undef value in the shuffle mask. 535 unsigned i; 536 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 537 /*search*/; 538 539 if (i == 16) return -1; // all undef. 540 541 // Otherwise, check to see if the rest of the elements are consequtively 542 // numbered from this value. 543 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 544 if (ShiftAmt < i) return -1; 545 ShiftAmt -= i; 546 547 if (!isUnary) { 548 // Check the rest of the elements to see if they are consequtive. 549 for (++i; i != 16; ++i) 550 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 551 return -1; 552 } else { 553 // Check the rest of the elements to see if they are consequtive. 554 for (++i; i != 16; ++i) 555 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 556 return -1; 557 } 558 559 return ShiftAmt; 560} 561 562/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 563/// specifies a splat of a single element that is suitable for input to 564/// VSPLTB/VSPLTH/VSPLTW. 565bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 566 assert(N->getOpcode() == ISD::BUILD_VECTOR && 567 N->getNumOperands() == 16 && 568 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 569 570 // This is a splat operation if each element of the permute is the same, and 571 // if the value doesn't reference the second vector. 572 unsigned ElementBase = 0; 573 SDValue Elt = N->getOperand(0); 574 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 575 ElementBase = EltV->getValue(); 576 else 577 return false; // FIXME: Handle UNDEF elements too! 578 579 if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 580 return false; 581 582 // Check that they are consequtive. 583 for (unsigned i = 1; i != EltSize; ++i) { 584 if (!isa<ConstantSDNode>(N->getOperand(i)) || 585 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 586 return false; 587 } 588 589 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 590 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 591 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 592 assert(isa<ConstantSDNode>(N->getOperand(i)) && 593 "Invalid VECTOR_SHUFFLE mask!"); 594 for (unsigned j = 0; j != EltSize; ++j) 595 if (N->getOperand(i+j) != N->getOperand(j)) 596 return false; 597 } 598 599 return true; 600} 601 602/// isAllNegativeZeroVector - Returns true if all elements of build_vector 603/// are -0.0. 604bool PPC::isAllNegativeZeroVector(SDNode *N) { 605 assert(N->getOpcode() == ISD::BUILD_VECTOR); 606 if (PPC::isSplatShuffleMask(N, N->getNumOperands())) 607 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N)) 608 return CFP->getValueAPF().isNegZero(); 609 return false; 610} 611 612/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 613/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 614unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 615 assert(isSplatShuffleMask(N, EltSize)); 616 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 617} 618 619/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 620/// by using a vspltis[bhw] instruction of the specified element size, return 621/// the constant being splatted. The ByteSize field indicates the number of 622/// bytes of each element [124] -> [bhw]. 623SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 624 SDValue OpVal(0, 0); 625 626 // If ByteSize of the splat is bigger than the element size of the 627 // build_vector, then we have a case where we are checking for a splat where 628 // multiple elements of the buildvector are folded together into a single 629 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 630 unsigned EltSize = 16/N->getNumOperands(); 631 if (EltSize < ByteSize) { 632 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 633 SDValue UniquedVals[4]; 634 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 635 636 // See if all of the elements in the buildvector agree across. 637 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 638 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 639 // If the element isn't a constant, bail fully out. 640 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 641 642 643 if (UniquedVals[i&(Multiple-1)].Val == 0) 644 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 645 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 646 return SDValue(); // no match. 647 } 648 649 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 650 // either constant or undef values that are identical for each chunk. See 651 // if these chunks can form into a larger vspltis*. 652 653 // Check to see if all of the leading entries are either 0 or -1. If 654 // neither, then this won't fit into the immediate field. 655 bool LeadingZero = true; 656 bool LeadingOnes = true; 657 for (unsigned i = 0; i != Multiple-1; ++i) { 658 if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 659 660 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 661 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 662 } 663 // Finally, check the least significant entry. 664 if (LeadingZero) { 665 if (UniquedVals[Multiple-1].Val == 0) 666 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 667 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 668 if (Val < 16) 669 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 670 } 671 if (LeadingOnes) { 672 if (UniquedVals[Multiple-1].Val == 0) 673 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 674 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 675 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 676 return DAG.getTargetConstant(Val, MVT::i32); 677 } 678 679 return SDValue(); 680 } 681 682 // Check to see if this buildvec has a single non-undef value in its elements. 683 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 684 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 685 if (OpVal.Val == 0) 686 OpVal = N->getOperand(i); 687 else if (OpVal != N->getOperand(i)) 688 return SDValue(); 689 } 690 691 if (OpVal.Val == 0) return SDValue(); // All UNDEF: use implicit def. 692 693 unsigned ValSizeInBytes = 0; 694 uint64_t Value = 0; 695 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 696 Value = CN->getValue(); 697 ValSizeInBytes = CN->getValueType(0).getSizeInBits()/8; 698 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 699 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 700 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 701 ValSizeInBytes = 4; 702 } 703 704 // If the splat value is larger than the element value, then we can never do 705 // this splat. The only case that we could fit the replicated bits into our 706 // immediate field for would be zero, and we prefer to use vxor for it. 707 if (ValSizeInBytes < ByteSize) return SDValue(); 708 709 // If the element value is larger than the splat value, cut it in half and 710 // check to see if the two halves are equal. Continue doing this until we 711 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 712 while (ValSizeInBytes > ByteSize) { 713 ValSizeInBytes >>= 1; 714 715 // If the top half equals the bottom half, we're still ok. 716 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 717 (Value & ((1 << (8*ValSizeInBytes))-1))) 718 return SDValue(); 719 } 720 721 // Properly sign extend the value. 722 int ShAmt = (4-ByteSize)*8; 723 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 724 725 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 726 if (MaskVal == 0) return SDValue(); 727 728 // Finally, if this value fits in a 5 bit sext field, return it 729 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 730 return DAG.getTargetConstant(MaskVal, MVT::i32); 731 return SDValue(); 732} 733 734//===----------------------------------------------------------------------===// 735// Addressing Mode Selection 736//===----------------------------------------------------------------------===// 737 738/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 739/// or 64-bit immediate, and if the value can be accurately represented as a 740/// sign extension from a 16-bit value. If so, this returns true and the 741/// immediate. 742static bool isIntS16Immediate(SDNode *N, short &Imm) { 743 if (N->getOpcode() != ISD::Constant) 744 return false; 745 746 Imm = (short)cast<ConstantSDNode>(N)->getValue(); 747 if (N->getValueType(0) == MVT::i32) 748 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); 749 else 750 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); 751} 752static bool isIntS16Immediate(SDValue Op, short &Imm) { 753 return isIntS16Immediate(Op.Val, Imm); 754} 755 756 757/// SelectAddressRegReg - Given the specified addressed, check to see if it 758/// can be represented as an indexed [r+r] operation. Returns false if it 759/// can be more efficiently represented with [r+imm]. 760bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 761 SDValue &Index, 762 SelectionDAG &DAG) { 763 short imm = 0; 764 if (N.getOpcode() == ISD::ADD) { 765 if (isIntS16Immediate(N.getOperand(1), imm)) 766 return false; // r+i 767 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 768 return false; // r+i 769 770 Base = N.getOperand(0); 771 Index = N.getOperand(1); 772 return true; 773 } else if (N.getOpcode() == ISD::OR) { 774 if (isIntS16Immediate(N.getOperand(1), imm)) 775 return false; // r+i can fold it if we can. 776 777 // If this is an or of disjoint bitfields, we can codegen this as an add 778 // (for better address arithmetic) if the LHS and RHS of the OR are provably 779 // disjoint. 780 APInt LHSKnownZero, LHSKnownOne; 781 APInt RHSKnownZero, RHSKnownOne; 782 DAG.ComputeMaskedBits(N.getOperand(0), 783 APInt::getAllOnesValue(N.getOperand(0) 784 .getValueSizeInBits()), 785 LHSKnownZero, LHSKnownOne); 786 787 if (LHSKnownZero.getBoolValue()) { 788 DAG.ComputeMaskedBits(N.getOperand(1), 789 APInt::getAllOnesValue(N.getOperand(1) 790 .getValueSizeInBits()), 791 RHSKnownZero, RHSKnownOne); 792 // If all of the bits are known zero on the LHS or RHS, the add won't 793 // carry. 794 if (~(LHSKnownZero | RHSKnownZero) == 0) { 795 Base = N.getOperand(0); 796 Index = N.getOperand(1); 797 return true; 798 } 799 } 800 } 801 802 return false; 803} 804 805/// Returns true if the address N can be represented by a base register plus 806/// a signed 16-bit displacement [r+imm], and if it is not better 807/// represented as reg+reg. 808bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 809 SDValue &Base, SelectionDAG &DAG){ 810 // If this can be more profitably realized as r+r, fail. 811 if (SelectAddressRegReg(N, Disp, Base, DAG)) 812 return false; 813 814 if (N.getOpcode() == ISD::ADD) { 815 short imm = 0; 816 if (isIntS16Immediate(N.getOperand(1), imm)) { 817 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 818 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 819 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 820 } else { 821 Base = N.getOperand(0); 822 } 823 return true; // [r+i] 824 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 825 // Match LOAD (ADD (X, Lo(G))). 826 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 827 && "Cannot handle constant offsets yet!"); 828 Disp = N.getOperand(1).getOperand(0); // The global address. 829 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 830 Disp.getOpcode() == ISD::TargetConstantPool || 831 Disp.getOpcode() == ISD::TargetJumpTable); 832 Base = N.getOperand(0); 833 return true; // [&g+r] 834 } 835 } else if (N.getOpcode() == ISD::OR) { 836 short imm = 0; 837 if (isIntS16Immediate(N.getOperand(1), imm)) { 838 // If this is an or of disjoint bitfields, we can codegen this as an add 839 // (for better address arithmetic) if the LHS and RHS of the OR are 840 // provably disjoint. 841 APInt LHSKnownZero, LHSKnownOne; 842 DAG.ComputeMaskedBits(N.getOperand(0), 843 APInt::getAllOnesValue(N.getOperand(0) 844 .getValueSizeInBits()), 845 LHSKnownZero, LHSKnownOne); 846 847 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 848 // If all of the bits are known zero on the LHS or RHS, the add won't 849 // carry. 850 Base = N.getOperand(0); 851 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 852 return true; 853 } 854 } 855 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 856 // Loading from a constant address. 857 858 // If this address fits entirely in a 16-bit sext immediate field, codegen 859 // this as "d, 0" 860 short Imm; 861 if (isIntS16Immediate(CN, Imm)) { 862 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 863 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 864 return true; 865 } 866 867 // Handle 32-bit sext immediates with LIS + addr mode. 868 if (CN->getValueType(0) == MVT::i32 || 869 (int64_t)CN->getValue() == (int)CN->getValue()) { 870 int Addr = (int)CN->getValue(); 871 872 // Otherwise, break this down into an LIS + disp. 873 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 874 875 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 876 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 877 Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 878 return true; 879 } 880 } 881 882 Disp = DAG.getTargetConstant(0, getPointerTy()); 883 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 884 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 885 else 886 Base = N; 887 return true; // [r+0] 888} 889 890/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 891/// represented as an indexed [r+r] operation. 892bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 893 SDValue &Index, 894 SelectionDAG &DAG) { 895 // Check to see if we can easily represent this as an [r+r] address. This 896 // will fail if it thinks that the address is more profitably represented as 897 // reg+imm, e.g. where imm = 0. 898 if (SelectAddressRegReg(N, Base, Index, DAG)) 899 return true; 900 901 // If the operand is an addition, always emit this as [r+r], since this is 902 // better (for code size, and execution, as the memop does the add for free) 903 // than emitting an explicit add. 904 if (N.getOpcode() == ISD::ADD) { 905 Base = N.getOperand(0); 906 Index = N.getOperand(1); 907 return true; 908 } 909 910 // Otherwise, do it the hard way, using R0 as the base register. 911 Base = DAG.getRegister(PPC::R0, N.getValueType()); 912 Index = N; 913 return true; 914} 915 916/// SelectAddressRegImmShift - Returns true if the address N can be 917/// represented by a base register plus a signed 14-bit displacement 918/// [r+imm*4]. Suitable for use by STD and friends. 919bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 920 SDValue &Base, 921 SelectionDAG &DAG) { 922 // If this can be more profitably realized as r+r, fail. 923 if (SelectAddressRegReg(N, Disp, Base, DAG)) 924 return false; 925 926 if (N.getOpcode() == ISD::ADD) { 927 short imm = 0; 928 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 929 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 930 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 931 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 932 } else { 933 Base = N.getOperand(0); 934 } 935 return true; // [r+i] 936 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 937 // Match LOAD (ADD (X, Lo(G))). 938 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 939 && "Cannot handle constant offsets yet!"); 940 Disp = N.getOperand(1).getOperand(0); // The global address. 941 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 942 Disp.getOpcode() == ISD::TargetConstantPool || 943 Disp.getOpcode() == ISD::TargetJumpTable); 944 Base = N.getOperand(0); 945 return true; // [&g+r] 946 } 947 } else if (N.getOpcode() == ISD::OR) { 948 short imm = 0; 949 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 950 // If this is an or of disjoint bitfields, we can codegen this as an add 951 // (for better address arithmetic) if the LHS and RHS of the OR are 952 // provably disjoint. 953 APInt LHSKnownZero, LHSKnownOne; 954 DAG.ComputeMaskedBits(N.getOperand(0), 955 APInt::getAllOnesValue(N.getOperand(0) 956 .getValueSizeInBits()), 957 LHSKnownZero, LHSKnownOne); 958 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 959 // If all of the bits are known zero on the LHS or RHS, the add won't 960 // carry. 961 Base = N.getOperand(0); 962 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 963 return true; 964 } 965 } 966 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 967 // Loading from a constant address. Verify low two bits are clear. 968 if ((CN->getValue() & 3) == 0) { 969 // If this address fits entirely in a 14-bit sext immediate field, codegen 970 // this as "d, 0" 971 short Imm; 972 if (isIntS16Immediate(CN, Imm)) { 973 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 974 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 975 return true; 976 } 977 978 // Fold the low-part of 32-bit absolute addresses into addr mode. 979 if (CN->getValueType(0) == MVT::i32 || 980 (int64_t)CN->getValue() == (int)CN->getValue()) { 981 int Addr = (int)CN->getValue(); 982 983 // Otherwise, break this down into an LIS + disp. 984 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 985 986 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 987 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 988 Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 989 return true; 990 } 991 } 992 } 993 994 Disp = DAG.getTargetConstant(0, getPointerTy()); 995 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 996 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 997 else 998 Base = N; 999 return true; // [r+0] 1000} 1001 1002 1003/// getPreIndexedAddressParts - returns true by value, base pointer and 1004/// offset pointer and addressing mode by reference if the node's address 1005/// can be legally represented as pre-indexed load / store address. 1006bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1007 SDValue &Offset, 1008 ISD::MemIndexedMode &AM, 1009 SelectionDAG &DAG) { 1010 // Disabled by default for now. 1011 if (!EnablePPCPreinc) return false; 1012 1013 SDValue Ptr; 1014 MVT VT; 1015 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1016 Ptr = LD->getBasePtr(); 1017 VT = LD->getMemoryVT(); 1018 1019 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1020 ST = ST; 1021 Ptr = ST->getBasePtr(); 1022 VT = ST->getMemoryVT(); 1023 } else 1024 return false; 1025 1026 // PowerPC doesn't have preinc load/store instructions for vectors. 1027 if (VT.isVector()) 1028 return false; 1029 1030 // TODO: Check reg+reg first. 1031 1032 // LDU/STU use reg+imm*4, others use reg+imm. 1033 if (VT != MVT::i64) { 1034 // reg + imm 1035 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1036 return false; 1037 } else { 1038 // reg + imm * 4. 1039 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1040 return false; 1041 } 1042 1043 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1044 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1045 // sext i32 to i64 when addr mode is r+i. 1046 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1047 LD->getExtensionType() == ISD::SEXTLOAD && 1048 isa<ConstantSDNode>(Offset)) 1049 return false; 1050 } 1051 1052 AM = ISD::PRE_INC; 1053 return true; 1054} 1055 1056//===----------------------------------------------------------------------===// 1057// LowerOperation implementation 1058//===----------------------------------------------------------------------===// 1059 1060SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1061 SelectionDAG &DAG) { 1062 MVT PtrVT = Op.getValueType(); 1063 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1064 Constant *C = CP->getConstVal(); 1065 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 1066 SDValue Zero = DAG.getConstant(0, PtrVT); 1067 1068 const TargetMachine &TM = DAG.getTarget(); 1069 1070 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 1071 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 1072 1073 // If this is a non-darwin platform, we don't support non-static relo models 1074 // yet. 1075 if (TM.getRelocationModel() == Reloc::Static || 1076 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1077 // Generate non-pic code that has direct accesses to the constant pool. 1078 // The address of the global is just (hi(&g)+lo(&g)). 1079 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1080 } 1081 1082 if (TM.getRelocationModel() == Reloc::PIC_) { 1083 // With PIC, the first instruction is actually "GR+hi(&G)". 1084 Hi = DAG.getNode(ISD::ADD, PtrVT, 1085 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1086 } 1087 1088 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1089 return Lo; 1090} 1091 1092SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 1093 MVT PtrVT = Op.getValueType(); 1094 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1095 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1096 SDValue Zero = DAG.getConstant(0, PtrVT); 1097 1098 const TargetMachine &TM = DAG.getTarget(); 1099 1100 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 1101 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 1102 1103 // If this is a non-darwin platform, we don't support non-static relo models 1104 // yet. 1105 if (TM.getRelocationModel() == Reloc::Static || 1106 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1107 // Generate non-pic code that has direct accesses to the constant pool. 1108 // The address of the global is just (hi(&g)+lo(&g)). 1109 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1110 } 1111 1112 if (TM.getRelocationModel() == Reloc::PIC_) { 1113 // With PIC, the first instruction is actually "GR+hi(&G)". 1114 Hi = DAG.getNode(ISD::ADD, PtrVT, 1115 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1116 } 1117 1118 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1119 return Lo; 1120} 1121 1122SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1123 SelectionDAG &DAG) { 1124 assert(0 && "TLS not implemented for PPC."); 1125 return SDValue(); // Not reached 1126} 1127 1128SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1129 SelectionDAG &DAG) { 1130 MVT PtrVT = Op.getValueType(); 1131 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1132 GlobalValue *GV = GSDN->getGlobal(); 1133 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1134 // If it's a debug information descriptor, don't mess with it. 1135 if (DAG.isVerifiedDebugInfoDesc(Op)) 1136 return GA; 1137 SDValue Zero = DAG.getConstant(0, PtrVT); 1138 1139 const TargetMachine &TM = DAG.getTarget(); 1140 1141 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); 1142 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); 1143 1144 // If this is a non-darwin platform, we don't support non-static relo models 1145 // yet. 1146 if (TM.getRelocationModel() == Reloc::Static || 1147 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1148 // Generate non-pic code that has direct accesses to globals. 1149 // The address of the global is just (hi(&g)+lo(&g)). 1150 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1151 } 1152 1153 if (TM.getRelocationModel() == Reloc::PIC_) { 1154 // With PIC, the first instruction is actually "GR+hi(&G)". 1155 Hi = DAG.getNode(ISD::ADD, PtrVT, 1156 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1157 } 1158 1159 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1160 1161 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) 1162 return Lo; 1163 1164 // If the global is weak or external, we have to go through the lazy 1165 // resolution stub. 1166 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); 1167} 1168 1169SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 1170 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1171 1172 // If we're comparing for equality to zero, expose the fact that this is 1173 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1174 // fold the new nodes. 1175 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1176 if (C->isNullValue() && CC == ISD::SETEQ) { 1177 MVT VT = Op.getOperand(0).getValueType(); 1178 SDValue Zext = Op.getOperand(0); 1179 if (VT.bitsLT(MVT::i32)) { 1180 VT = MVT::i32; 1181 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 1182 } 1183 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1184 SDValue Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 1185 SDValue Scc = DAG.getNode(ISD::SRL, VT, Clz, 1186 DAG.getConstant(Log2b, MVT::i32)); 1187 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 1188 } 1189 // Leave comparisons against 0 and -1 alone for now, since they're usually 1190 // optimized. FIXME: revisit this when we can custom lower all setcc 1191 // optimizations. 1192 if (C->isAllOnesValue() || C->isNullValue()) 1193 return SDValue(); 1194 } 1195 1196 // If we have an integer seteq/setne, turn it into a compare against zero 1197 // by xor'ing the rhs with the lhs, which is faster than setting a 1198 // condition register, reading it back out, and masking the correct bit. The 1199 // normal approach here uses sub to do this instead of xor. Using xor exposes 1200 // the result to other bit-twiddling opportunities. 1201 MVT LHSVT = Op.getOperand(0).getValueType(); 1202 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1203 MVT VT = Op.getValueType(); 1204 SDValue Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), 1205 Op.getOperand(1)); 1206 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 1207 } 1208 return SDValue(); 1209} 1210 1211SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1212 int VarArgsFrameIndex, 1213 int VarArgsStackOffset, 1214 unsigned VarArgsNumGPR, 1215 unsigned VarArgsNumFPR, 1216 const PPCSubtarget &Subtarget) { 1217 1218 assert(0 && "VAARG in ELF32 ABI not implemented yet!"); 1219 return SDValue(); // Not reached 1220} 1221 1222SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1223 int VarArgsFrameIndex, 1224 int VarArgsStackOffset, 1225 unsigned VarArgsNumGPR, 1226 unsigned VarArgsNumFPR, 1227 const PPCSubtarget &Subtarget) { 1228 1229 if (Subtarget.isMachoABI()) { 1230 // vastart just stores the address of the VarArgsFrameIndex slot into the 1231 // memory location argument. 1232 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1233 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1234 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1235 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); 1236 } 1237 1238 // For ELF 32 ABI we follow the layout of the va_list struct. 1239 // We suppose the given va_list is already allocated. 1240 // 1241 // typedef struct { 1242 // char gpr; /* index into the array of 8 GPRs 1243 // * stored in the register save area 1244 // * gpr=0 corresponds to r3, 1245 // * gpr=1 to r4, etc. 1246 // */ 1247 // char fpr; /* index into the array of 8 FPRs 1248 // * stored in the register save area 1249 // * fpr=0 corresponds to f1, 1250 // * fpr=1 to f2, etc. 1251 // */ 1252 // char *overflow_arg_area; 1253 // /* location on stack that holds 1254 // * the next overflow argument 1255 // */ 1256 // char *reg_save_area; 1257 // /* where r3:r10 and f1:f8 (if saved) 1258 // * are stored 1259 // */ 1260 // } va_list[1]; 1261 1262 1263 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); 1264 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); 1265 1266 1267 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1268 1269 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); 1270 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1271 1272 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1273 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1274 1275 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1276 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1277 1278 uint64_t FPROffset = 1; 1279 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1280 1281 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1282 1283 // Store first byte : number of int regs 1284 SDValue firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, 1285 Op.getOperand(1), SV, 0); 1286 uint64_t nextOffset = FPROffset; 1287 SDValue nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), 1288 ConstFPROffset); 1289 1290 // Store second byte : number of float regs 1291 SDValue secondStore = 1292 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset); 1293 nextOffset += StackOffset; 1294 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); 1295 1296 // Store second word : arguments given on stack 1297 SDValue thirdStore = 1298 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset); 1299 nextOffset += FrameOffset; 1300 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); 1301 1302 // Store third word : arguments given in registers 1303 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset); 1304 1305} 1306 1307#include "PPCGenCallingConv.inc" 1308 1309/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1310/// depending on which subtarget is selected. 1311static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { 1312 if (Subtarget.isMachoABI()) { 1313 static const unsigned FPR[] = { 1314 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1315 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1316 }; 1317 return FPR; 1318 } 1319 1320 1321 static const unsigned FPR[] = { 1322 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1323 PPC::F8 1324 }; 1325 return FPR; 1326} 1327 1328/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1329/// the stack. 1330static unsigned CalculateStackSlotSize(SDValue Arg, SDValue Flag, 1331 bool isVarArg, unsigned PtrByteSize) { 1332 MVT ArgVT = Arg.getValueType(); 1333 ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Flag)->getArgFlags(); 1334 unsigned ArgSize =ArgVT.getSizeInBits()/8; 1335 if (Flags.isByVal()) 1336 ArgSize = Flags.getByValSize(); 1337 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1338 1339 return ArgSize; 1340} 1341 1342SDValue 1343PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, 1344 SelectionDAG &DAG, 1345 int &VarArgsFrameIndex, 1346 int &VarArgsStackOffset, 1347 unsigned &VarArgsNumGPR, 1348 unsigned &VarArgsNumFPR, 1349 const PPCSubtarget &Subtarget) { 1350 // TODO: add description of PPC stack frame format, or at least some docs. 1351 // 1352 MachineFunction &MF = DAG.getMachineFunction(); 1353 MachineFrameInfo *MFI = MF.getFrameInfo(); 1354 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 1355 SmallVector<SDValue, 8> ArgValues; 1356 SDValue Root = Op.getOperand(0); 1357 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1358 1359 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1360 bool isPPC64 = PtrVT == MVT::i64; 1361 bool isMachoABI = Subtarget.isMachoABI(); 1362 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1363 // Potential tail calls could cause overwriting of argument stack slots. 1364 unsigned CC = MF.getFunction()->getCallingConv(); 1365 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast)); 1366 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1367 1368 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1369 // Area that is at least reserved in caller of this function. 1370 unsigned MinReservedArea = ArgOffset; 1371 1372 static const unsigned GPR_32[] = { // 32-bit registers. 1373 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1374 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1375 }; 1376 static const unsigned GPR_64[] = { // 64-bit registers. 1377 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1378 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1379 }; 1380 1381 static const unsigned *FPR = GetFPR(Subtarget); 1382 1383 static const unsigned VR[] = { 1384 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1385 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1386 }; 1387 1388 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1389 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8; 1390 const unsigned Num_VR_Regs = array_lengthof( VR); 1391 1392 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1393 1394 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1395 1396 // In 32-bit non-varargs functions, the stack space for vectors is after the 1397 // stack space for non-vectors. We do not use this space unless we have 1398 // too many vectors to fit in registers, something that only occurs in 1399 // constructed examples:), but we have to walk the arglist to figure 1400 // that out...for the pathological case, compute VecArgOffset as the 1401 // start of the vector parameter area. Computing VecArgOffset is the 1402 // entire point of the following loop. 1403 // Altivec is not mentioned in the ppc32 Elf Supplement, so I'm not trying 1404 // to handle Elf here. 1405 unsigned VecArgOffset = ArgOffset; 1406 if (!isVarArg && !isPPC64) { 1407 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; 1408 ++ArgNo) { 1409 MVT ObjectVT = Op.getValue(ArgNo).getValueType(); 1410 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1411 ISD::ArgFlagsTy Flags = 1412 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags(); 1413 1414 if (Flags.isByVal()) { 1415 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 1416 ObjSize = Flags.getByValSize(); 1417 unsigned ArgSize = 1418 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1419 VecArgOffset += ArgSize; 1420 continue; 1421 } 1422 1423 switch(ObjectVT.getSimpleVT()) { 1424 default: assert(0 && "Unhandled argument type!"); 1425 case MVT::i32: 1426 case MVT::f32: 1427 VecArgOffset += isPPC64 ? 8 : 4; 1428 break; 1429 case MVT::i64: // PPC64 1430 case MVT::f64: 1431 VecArgOffset += 8; 1432 break; 1433 case MVT::v4f32: 1434 case MVT::v4i32: 1435 case MVT::v8i16: 1436 case MVT::v16i8: 1437 // Nothing to do, we're only looking at Nonvector args here. 1438 break; 1439 } 1440 } 1441 } 1442 // We've found where the vector parameter area in memory is. Skip the 1443 // first 12 parameters; these don't use that memory. 1444 VecArgOffset = ((VecArgOffset+15)/16)*16; 1445 VecArgOffset += 12*16; 1446 1447 // Add DAG nodes to load the arguments or copy them out of registers. On 1448 // entry to a function on PPC, the arguments start after the linkage area, 1449 // although the first ones are often in registers. 1450 // 1451 // In the ELF 32 ABI, GPRs and stack are double word align: an argument 1452 // represented with two words (long long or double) must be copied to an 1453 // even GPR_idx value or to an even ArgOffset value. 1454 1455 SmallVector<SDValue, 8> MemOps; 1456 unsigned nAltivecParamsAtEnd = 0; 1457 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { 1458 SDValue ArgVal; 1459 bool needsLoad = false; 1460 MVT ObjectVT = Op.getValue(ArgNo).getValueType(); 1461 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1462 unsigned ArgSize = ObjSize; 1463 ISD::ArgFlagsTy Flags = 1464 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags(); 1465 // See if next argument requires stack alignment in ELF 1466 bool Align = Flags.isSplit(); 1467 1468 unsigned CurArgOffset = ArgOffset; 1469 1470 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 1471 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 1472 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 1473 if (isVarArg || isPPC64) { 1474 MinReservedArea = ((MinReservedArea+15)/16)*16; 1475 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo), 1476 Op.getOperand(ArgNo+3), 1477 isVarArg, 1478 PtrByteSize); 1479 } else nAltivecParamsAtEnd++; 1480 } else 1481 // Calculate min reserved area. 1482 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo), 1483 Op.getOperand(ArgNo+3), 1484 isVarArg, 1485 PtrByteSize); 1486 1487 // FIXME alignment for ELF may not be right 1488 // FIXME the codegen can be much improved in some cases. 1489 // We do not have to keep everything in memory. 1490 if (Flags.isByVal()) { 1491 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 1492 ObjSize = Flags.getByValSize(); 1493 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1494 // Double word align in ELF 1495 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1496 // Objects of size 1 and 2 are right justified, everything else is 1497 // left justified. This means the memory address is adjusted forwards. 1498 if (ObjSize==1 || ObjSize==2) { 1499 CurArgOffset = CurArgOffset + (4 - ObjSize); 1500 } 1501 // The value of the object is its address. 1502 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset); 1503 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1504 ArgValues.push_back(FIN); 1505 if (ObjSize==1 || ObjSize==2) { 1506 if (GPR_idx != Num_GPR_Regs) { 1507 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1508 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1509 SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1510 SDValue Store = DAG.getTruncStore(Val.getValue(1), Val, FIN, 1511 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 ); 1512 MemOps.push_back(Store); 1513 ++GPR_idx; 1514 if (isMachoABI) ArgOffset += PtrByteSize; 1515 } else { 1516 ArgOffset += PtrByteSize; 1517 } 1518 continue; 1519 } 1520 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 1521 // Store whatever pieces of the object are in registers 1522 // to memory. ArgVal will be address of the beginning of 1523 // the object. 1524 if (GPR_idx != Num_GPR_Regs) { 1525 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1526 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1527 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset); 1528 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1529 SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1530 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1531 MemOps.push_back(Store); 1532 ++GPR_idx; 1533 if (isMachoABI) ArgOffset += PtrByteSize; 1534 } else { 1535 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 1536 break; 1537 } 1538 } 1539 continue; 1540 } 1541 1542 switch (ObjectVT.getSimpleVT()) { 1543 default: assert(0 && "Unhandled argument type!"); 1544 case MVT::i32: 1545 if (!isPPC64) { 1546 // Double word align in ELF 1547 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1548 1549 if (GPR_idx != Num_GPR_Regs) { 1550 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1551 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1552 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1553 ++GPR_idx; 1554 } else { 1555 needsLoad = true; 1556 ArgSize = PtrByteSize; 1557 } 1558 // Stack align in ELF 1559 if (needsLoad && Align && isELF32_ABI) 1560 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1561 // All int arguments reserve stack space in Macho ABI. 1562 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; 1563 break; 1564 } 1565 // FALLTHROUGH 1566 case MVT::i64: // PPC64 1567 if (GPR_idx != Num_GPR_Regs) { 1568 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); 1569 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1570 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1571 1572 if (ObjectVT == MVT::i32) { 1573 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 1574 // value to MVT::i64 and then truncate to the correct register size. 1575 if (Flags.isSExt()) 1576 ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal, 1577 DAG.getValueType(ObjectVT)); 1578 else if (Flags.isZExt()) 1579 ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal, 1580 DAG.getValueType(ObjectVT)); 1581 1582 ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal); 1583 } 1584 1585 ++GPR_idx; 1586 } else { 1587 needsLoad = true; 1588 ArgSize = PtrByteSize; 1589 } 1590 // All int arguments reserve stack space in Macho ABI. 1591 if (isMachoABI || needsLoad) ArgOffset += 8; 1592 break; 1593 1594 case MVT::f32: 1595 case MVT::f64: 1596 // Every 4 bytes of argument space consumes one of the GPRs available for 1597 // argument passing. 1598 if (GPR_idx != Num_GPR_Regs && isMachoABI) { 1599 ++GPR_idx; 1600 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1601 ++GPR_idx; 1602 } 1603 if (FPR_idx != Num_FPR_Regs) { 1604 unsigned VReg; 1605 if (ObjectVT == MVT::f32) 1606 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass); 1607 else 1608 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 1609 RegInfo.addLiveIn(FPR[FPR_idx], VReg); 1610 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1611 ++FPR_idx; 1612 } else { 1613 needsLoad = true; 1614 } 1615 1616 // Stack align in ELF 1617 if (needsLoad && Align && isELF32_ABI) 1618 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1619 // All FP arguments reserve stack space in Macho ABI. 1620 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize; 1621 break; 1622 case MVT::v4f32: 1623 case MVT::v4i32: 1624 case MVT::v8i16: 1625 case MVT::v16i8: 1626 // Note that vector arguments in registers don't reserve stack space, 1627 // except in varargs functions. 1628 if (VR_idx != Num_VR_Regs) { 1629 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass); 1630 RegInfo.addLiveIn(VR[VR_idx], VReg); 1631 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1632 if (isVarArg) { 1633 while ((ArgOffset % 16) != 0) { 1634 ArgOffset += PtrByteSize; 1635 if (GPR_idx != Num_GPR_Regs) 1636 GPR_idx++; 1637 } 1638 ArgOffset += 16; 1639 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); 1640 } 1641 ++VR_idx; 1642 } else { 1643 if (!isVarArg && !isPPC64) { 1644 // Vectors go after all the nonvectors. 1645 CurArgOffset = VecArgOffset; 1646 VecArgOffset += 16; 1647 } else { 1648 // Vectors are aligned. 1649 ArgOffset = ((ArgOffset+15)/16)*16; 1650 CurArgOffset = ArgOffset; 1651 ArgOffset += 16; 1652 } 1653 needsLoad = true; 1654 } 1655 break; 1656 } 1657 1658 // We need to load the argument to a virtual register if we determined above 1659 // that we ran out of physical registers of the appropriate type. 1660 if (needsLoad) { 1661 int FI = MFI->CreateFixedObject(ObjSize, 1662 CurArgOffset + (ArgSize - ObjSize), 1663 isImmutable); 1664 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1665 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 1666 } 1667 1668 ArgValues.push_back(ArgVal); 1669 } 1670 1671 // Set the size that is at least reserved in caller of this function. Tail 1672 // call optimized function's reserved stack space needs to be aligned so that 1673 // taking the difference between two stack areas will result in an aligned 1674 // stack. 1675 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1676 // Add the Altivec parameters at the end, if needed. 1677 if (nAltivecParamsAtEnd) { 1678 MinReservedArea = ((MinReservedArea+15)/16)*16; 1679 MinReservedArea += 16*nAltivecParamsAtEnd; 1680 } 1681 MinReservedArea = 1682 std::max(MinReservedArea, 1683 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1684 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 1685 getStackAlignment(); 1686 unsigned AlignMask = TargetAlign-1; 1687 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1688 FI->setMinReservedArea(MinReservedArea); 1689 1690 // If the function takes variable number of arguments, make a frame index for 1691 // the start of the first vararg value... for expansion of llvm.va_start. 1692 if (isVarArg) { 1693 1694 int depth; 1695 if (isELF32_ABI) { 1696 VarArgsNumGPR = GPR_idx; 1697 VarArgsNumFPR = FPR_idx; 1698 1699 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame 1700 // pointer. 1701 depth = -(Num_GPR_Regs * PtrVT.getSizeInBits()/8 + 1702 Num_FPR_Regs * MVT(MVT::f64).getSizeInBits()/8 + 1703 PtrVT.getSizeInBits()/8); 1704 1705 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1706 ArgOffset); 1707 1708 } 1709 else 1710 depth = ArgOffset; 1711 1712 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1713 depth); 1714 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1715 1716 // In ELF 32 ABI, the fixed integer arguments of a variadic function are 1717 // stored to the VarArgsFrameIndex on the stack. 1718 if (isELF32_ABI) { 1719 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { 1720 SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT); 1721 SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1722 MemOps.push_back(Store); 1723 // Increment the address by four for the next argument to store 1724 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1725 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1726 } 1727 } 1728 1729 // If this function is vararg, store any remaining integer argument regs 1730 // to their spots on the stack so that they may be loaded by deferencing the 1731 // result of va_next. 1732 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 1733 unsigned VReg; 1734 if (isPPC64) 1735 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); 1736 else 1737 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1738 1739 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1740 SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1741 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1742 MemOps.push_back(Store); 1743 // Increment the address by four for the next argument to store 1744 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1745 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1746 } 1747 1748 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex 1749 // on the stack. 1750 if (isELF32_ABI) { 1751 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { 1752 SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); 1753 SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1754 MemOps.push_back(Store); 1755 // Increment the address by eight for the next argument to store 1756 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, 1757 PtrVT); 1758 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1759 } 1760 1761 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { 1762 unsigned VReg; 1763 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 1764 1765 RegInfo.addLiveIn(FPR[FPR_idx], VReg); 1766 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); 1767 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1768 MemOps.push_back(Store); 1769 // Increment the address by eight for the next argument to store 1770 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, 1771 PtrVT); 1772 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1773 } 1774 } 1775 } 1776 1777 if (!MemOps.empty()) 1778 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 1779 1780 ArgValues.push_back(Root); 1781 1782 // Return the new list of results. 1783 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0], 1784 ArgValues.size()); 1785} 1786 1787/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus 1788/// linkage area. 1789static unsigned 1790CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 1791 bool isPPC64, 1792 bool isMachoABI, 1793 bool isVarArg, 1794 unsigned CC, 1795 SDValue Call, 1796 unsigned &nAltivecParamsAtEnd) { 1797 // Count how many bytes are to be pushed on the stack, including the linkage 1798 // area, and parameter passing area. We start with 24/48 bytes, which is 1799 // prereserved space for [SP][CR][LR][3 x unused]. 1800 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1801 unsigned NumOps = (Call.getNumOperands() - 5) / 2; 1802 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1803 1804 // Add up all the space actually used. 1805 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 1806 // they all go in registers, but we must reserve stack space for them for 1807 // possible use by the caller. In varargs or 64-bit calls, parameters are 1808 // assigned stack space in order, with padding so Altivec parameters are 1809 // 16-byte aligned. 1810 nAltivecParamsAtEnd = 0; 1811 for (unsigned i = 0; i != NumOps; ++i) { 1812 SDValue Arg = Call.getOperand(5+2*i); 1813 SDValue Flag = Call.getOperand(5+2*i+1); 1814 MVT ArgVT = Arg.getValueType(); 1815 // Varargs Altivec parameters are padded to a 16 byte boundary. 1816 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 1817 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 1818 if (!isVarArg && !isPPC64) { 1819 // Non-varargs Altivec parameters go after all the non-Altivec 1820 // parameters; handle those later so we know how much padding we need. 1821 nAltivecParamsAtEnd++; 1822 continue; 1823 } 1824 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 1825 NumBytes = ((NumBytes+15)/16)*16; 1826 } 1827 NumBytes += CalculateStackSlotSize(Arg, Flag, isVarArg, PtrByteSize); 1828 } 1829 1830 // Allow for Altivec parameters at the end, if needed. 1831 if (nAltivecParamsAtEnd) { 1832 NumBytes = ((NumBytes+15)/16)*16; 1833 NumBytes += 16*nAltivecParamsAtEnd; 1834 } 1835 1836 // The prolog code of the callee may store up to 8 GPR argument registers to 1837 // the stack, allowing va_start to index over them in memory if its varargs. 1838 // Because we cannot tell if this is needed on the caller side, we have to 1839 // conservatively assume that it is needed. As such, make sure we have at 1840 // least enough stack space for the caller to store the 8 GPRs. 1841 NumBytes = std::max(NumBytes, 1842 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1843 1844 // Tail call needs the stack to be aligned. 1845 if (CC==CallingConv::Fast && PerformTailCallOpt) { 1846 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 1847 getStackAlignment(); 1848 unsigned AlignMask = TargetAlign-1; 1849 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 1850 } 1851 1852 return NumBytes; 1853} 1854 1855/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 1856/// adjusted to accomodate the arguments for the tailcall. 1857static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall, 1858 unsigned ParamSize) { 1859 1860 if (!IsTailCall) return 0; 1861 1862 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 1863 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 1864 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 1865 // Remember only if the new adjustement is bigger. 1866 if (SPDiff < FI->getTailCallSPDelta()) 1867 FI->setTailCallSPDelta(SPDiff); 1868 1869 return SPDiff; 1870} 1871 1872/// IsEligibleForTailCallElimination - Check to see whether the next instruction 1873/// following the call is a return. A function is eligible if caller/callee 1874/// calling conventions match, currently only fastcc supports tail calls, and 1875/// the function CALL is immediatly followed by a RET. 1876bool 1877PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Call, 1878 SDValue Ret, 1879 SelectionDAG& DAG) const { 1880 // Variable argument functions are not supported. 1881 if (!PerformTailCallOpt || 1882 cast<ConstantSDNode>(Call.getOperand(2))->getValue() != 0) return false; 1883 1884 if (CheckTailCallReturnConstraints(Call, Ret)) { 1885 MachineFunction &MF = DAG.getMachineFunction(); 1886 unsigned CallerCC = MF.getFunction()->getCallingConv(); 1887 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue(); 1888 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 1889 // Functions containing by val parameters are not supported. 1890 for (unsigned i = 0; i != ((Call.getNumOperands()-5)/2); i++) { 1891 ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Call.getOperand(5+2*i+1)) 1892 ->getArgFlags(); 1893 if (Flags.isByVal()) return false; 1894 } 1895 1896 SDValue Callee = Call.getOperand(4); 1897 // Non PIC/GOT tail calls are supported. 1898 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1899 return true; 1900 1901 // At the moment we can only do local tail calls (in same module, hidden 1902 // or protected) if we are generating PIC. 1903 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1904 return G->getGlobal()->hasHiddenVisibility() 1905 || G->getGlobal()->hasProtectedVisibility(); 1906 } 1907 } 1908 1909 return false; 1910} 1911 1912/// isCallCompatibleAddress - Return the immediate to use if the specified 1913/// 32-bit value is representable in the immediate field of a BxA instruction. 1914static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 1915 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1916 if (!C) return 0; 1917 1918 int Addr = C->getValue(); 1919 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 1920 (Addr << 6 >> 6) != Addr) 1921 return 0; // Top 6 bits have to be sext of immediate. 1922 1923 return DAG.getConstant((int)C->getValue() >> 2, 1924 DAG.getTargetLoweringInfo().getPointerTy()).Val; 1925} 1926 1927namespace { 1928 1929struct TailCallArgumentInfo { 1930 SDValue Arg; 1931 SDValue FrameIdxOp; 1932 int FrameIdx; 1933 1934 TailCallArgumentInfo() : FrameIdx(0) {} 1935}; 1936 1937} 1938 1939/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 1940static void 1941StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 1942 SDValue Chain, 1943 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 1944 SmallVector<SDValue, 8> &MemOpChains) { 1945 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 1946 SDValue Arg = TailCallArgs[i].Arg; 1947 SDValue FIN = TailCallArgs[i].FrameIdxOp; 1948 int FI = TailCallArgs[i].FrameIdx; 1949 // Store relative to framepointer. 1950 MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN, 1951 PseudoSourceValue::getFixedStack(FI), 1952 0)); 1953 } 1954} 1955 1956/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 1957/// the appropriate stack slot for the tail call optimized function call. 1958static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 1959 MachineFunction &MF, 1960 SDValue Chain, 1961 SDValue OldRetAddr, 1962 SDValue OldFP, 1963 int SPDiff, 1964 bool isPPC64, 1965 bool isMachoABI) { 1966 if (SPDiff) { 1967 // Calculate the new stack slot for the return address. 1968 int SlotSize = isPPC64 ? 8 : 4; 1969 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64, 1970 isMachoABI); 1971 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 1972 NewRetAddrLoc); 1973 int NewFPLoc = SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, 1974 isMachoABI); 1975 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc); 1976 1977 MVT VT = isPPC64 ? MVT::i64 : MVT::i32; 1978 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 1979 Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx, 1980 PseudoSourceValue::getFixedStack(NewRetAddr), 0); 1981 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 1982 Chain = DAG.getStore(Chain, OldFP, NewFramePtrIdx, 1983 PseudoSourceValue::getFixedStack(NewFPIdx), 0); 1984 } 1985 return Chain; 1986} 1987 1988/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 1989/// the position of the argument. 1990static void 1991CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 1992 SDValue Arg, int SPDiff, unsigned ArgOffset, 1993 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 1994 int Offset = ArgOffset + SPDiff; 1995 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 1996 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); 1997 MVT VT = isPPC64 ? MVT::i64 : MVT::i32; 1998 SDValue FIN = DAG.getFrameIndex(FI, VT); 1999 TailCallArgumentInfo Info; 2000 Info.Arg = Arg; 2001 Info.FrameIdxOp = FIN; 2002 Info.FrameIdx = FI; 2003 TailCallArguments.push_back(Info); 2004} 2005 2006/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2007/// stack slot. Returns the chain as result and the loaded frame pointers in 2008/// LROpOut/FPOpout. Used when tail calling. 2009SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2010 int SPDiff, 2011 SDValue Chain, 2012 SDValue &LROpOut, 2013 SDValue &FPOpOut) { 2014 if (SPDiff) { 2015 // Load the LR and FP stack slot for later adjusting. 2016 MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2017 LROpOut = getReturnAddrFrameIndex(DAG); 2018 LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0); 2019 Chain = SDValue(LROpOut.Val, 1); 2020 FPOpOut = getFramePointerFrameIndex(DAG); 2021 FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0); 2022 Chain = SDValue(FPOpOut.Val, 1); 2023 } 2024 return Chain; 2025} 2026 2027/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 2028/// by "Src" to address "Dst" of size "Size". Alignment information is 2029/// specified by the specific parameter attribute. The copy will be passed as 2030/// a byval function parameter. 2031/// Sometimes what we are copying is the end of a larger object, the part that 2032/// does not fit in registers. 2033static SDValue 2034CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 2035 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 2036 unsigned Size) { 2037 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); 2038 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), false, 2039 NULL, 0, NULL, 0); 2040} 2041 2042/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 2043/// tail calls. 2044static void 2045LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 2046 SDValue Arg, SDValue PtrOff, int SPDiff, 2047 unsigned ArgOffset, bool isPPC64, bool isTailCall, 2048 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 2049 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2050 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2051 if (!isTailCall) { 2052 if (isVector) { 2053 SDValue StackPtr; 2054 if (isPPC64) 2055 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2056 else 2057 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2058 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, 2059 DAG.getConstant(ArgOffset, PtrVT)); 2060 } 2061 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 2062 // Calculate and remember argument location. 2063 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 2064 TailCallArguments); 2065} 2066 2067SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG, 2068 const PPCSubtarget &Subtarget, 2069 TargetMachine &TM) { 2070 SDValue Chain = Op.getOperand(0); 2071 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 2072 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 2073 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0 && 2074 CC == CallingConv::Fast && PerformTailCallOpt; 2075 SDValue Callee = Op.getOperand(4); 2076 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 2077 2078 bool isMachoABI = Subtarget.isMachoABI(); 2079 bool isELF32_ABI = Subtarget.isELF32_ABI(); 2080 2081 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2082 bool isPPC64 = PtrVT == MVT::i64; 2083 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2084 2085 MachineFunction &MF = DAG.getMachineFunction(); 2086 2087 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 2088 // SelectExpr to use to put the arguments in the appropriate registers. 2089 std::vector<SDValue> args_to_use; 2090 2091 // Mark this function as potentially containing a function that contains a 2092 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2093 // and restoring the callers stack pointer in this functions epilog. This is 2094 // done because by tail calling the called function might overwrite the value 2095 // in this function's (MF) stack pointer stack slot 0(SP). 2096 if (PerformTailCallOpt && CC==CallingConv::Fast) 2097 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2098 2099 unsigned nAltivecParamsAtEnd = 0; 2100 2101 // Count how many bytes are to be pushed on the stack, including the linkage 2102 // area, and parameter passing area. We start with 24/48 bytes, which is 2103 // prereserved space for [SP][CR][LR][3 x unused]. 2104 unsigned NumBytes = 2105 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isMachoABI, isVarArg, CC, 2106 Op, nAltivecParamsAtEnd); 2107 2108 // Calculate by how many bytes the stack has to be adjusted in case of tail 2109 // call optimization. 2110 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2111 2112 // Adjust the stack pointer for the new arguments... 2113 // These operations are automatically eliminated by the prolog/epilog pass 2114 Chain = DAG.getCALLSEQ_START(Chain, 2115 DAG.getConstant(NumBytes, PtrVT)); 2116 SDValue CallSeqStart = Chain; 2117 2118 // Load the return address and frame pointer so it can be move somewhere else 2119 // later. 2120 SDValue LROp, FPOp; 2121 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp); 2122 2123 // Set up a copy of the stack pointer for use loading and storing any 2124 // arguments that may not fit in the registers available for argument 2125 // passing. 2126 SDValue StackPtr; 2127 if (isPPC64) 2128 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2129 else 2130 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2131 2132 // Figure out which arguments are going to go in registers, and which in 2133 // memory. Also, if this is a vararg function, floating point operations 2134 // must be stored to our stack, and loaded into integer regs as well, if 2135 // any integer regs are available for argument passing. 2136 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 2137 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2138 2139 static const unsigned GPR_32[] = { // 32-bit registers. 2140 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 2141 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 2142 }; 2143 static const unsigned GPR_64[] = { // 64-bit registers. 2144 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2145 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2146 }; 2147 static const unsigned *FPR = GetFPR(Subtarget); 2148 2149 static const unsigned VR[] = { 2150 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2151 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2152 }; 2153 const unsigned NumGPRs = array_lengthof(GPR_32); 2154 const unsigned NumFPRs = isMachoABI ? 13 : 8; 2155 const unsigned NumVRs = array_lengthof( VR); 2156 2157 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 2158 2159 std::vector<std::pair<unsigned, SDValue> > RegsToPass; 2160 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 2161 2162 SmallVector<SDValue, 8> MemOpChains; 2163 for (unsigned i = 0; i != NumOps; ++i) { 2164 bool inMem = false; 2165 SDValue Arg = Op.getOperand(5+2*i); 2166 ISD::ArgFlagsTy Flags = 2167 cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags(); 2168 // See if next argument requires stack alignment in ELF 2169 bool Align = Flags.isSplit(); 2170 2171 // PtrOff will be used to store the current argument to the stack if a 2172 // register cannot be found for it. 2173 SDValue PtrOff; 2174 2175 // Stack align in ELF 32 2176 if (isELF32_ABI && Align) 2177 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize, 2178 StackPtr.getValueType()); 2179 else 2180 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 2181 2182 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); 2183 2184 // On PPC64, promote integers to 64-bit values. 2185 if (isPPC64 && Arg.getValueType() == MVT::i32) { 2186 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 2187 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 2188 Arg = DAG.getNode(ExtOp, MVT::i64, Arg); 2189 } 2190 2191 // FIXME Elf untested, what are alignment rules? 2192 // FIXME memcpy is used way more than necessary. Correctness first. 2193 if (Flags.isByVal()) { 2194 unsigned Size = Flags.getByValSize(); 2195 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2); 2196 if (Size==1 || Size==2) { 2197 // Very small objects are passed right-justified. 2198 // Everything else is passed left-justified. 2199 MVT VT = (Size==1) ? MVT::i8 : MVT::i16; 2200 if (GPR_idx != NumGPRs) { 2201 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg, 2202 NULL, 0, VT); 2203 MemOpChains.push_back(Load.getValue(1)); 2204 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 2205 if (isMachoABI) 2206 ArgOffset += PtrByteSize; 2207 } else { 2208 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); 2209 SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const); 2210 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 2211 CallSeqStart.Val->getOperand(0), 2212 Flags, DAG, Size); 2213 // This must go outside the CALLSEQ_START..END. 2214 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2215 CallSeqStart.Val->getOperand(1)); 2216 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val); 2217 Chain = CallSeqStart = NewCallSeqStart; 2218 ArgOffset += PtrByteSize; 2219 } 2220 continue; 2221 } 2222 // Copy entire object into memory. There are cases where gcc-generated 2223 // code assumes it is there, even if it could be put entirely into 2224 // registers. (This is not what the doc says.) 2225 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 2226 CallSeqStart.Val->getOperand(0), 2227 Flags, DAG, Size); 2228 // This must go outside the CALLSEQ_START..END. 2229 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2230 CallSeqStart.Val->getOperand(1)); 2231 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val); 2232 Chain = CallSeqStart = NewCallSeqStart; 2233 // And copy the pieces of it that fit into registers. 2234 for (unsigned j=0; j<Size; j+=PtrByteSize) { 2235 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 2236 SDValue AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const); 2237 if (GPR_idx != NumGPRs) { 2238 SDValue Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0); 2239 MemOpChains.push_back(Load.getValue(1)); 2240 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 2241 if (isMachoABI) 2242 ArgOffset += PtrByteSize; 2243 } else { 2244 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 2245 break; 2246 } 2247 } 2248 continue; 2249 } 2250 2251 switch (Arg.getValueType().getSimpleVT()) { 2252 default: assert(0 && "Unexpected ValueType for argument!"); 2253 case MVT::i32: 2254 case MVT::i64: 2255 // Double word align in ELF 2256 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2); 2257 if (GPR_idx != NumGPRs) { 2258 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 2259 } else { 2260 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 2261 isPPC64, isTailCall, false, MemOpChains, 2262 TailCallArguments); 2263 inMem = true; 2264 } 2265 if (inMem || isMachoABI) { 2266 // Stack align in ELF 2267 if (isELF32_ABI && Align) 2268 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 2269 2270 ArgOffset += PtrByteSize; 2271 } 2272 break; 2273 case MVT::f32: 2274 case MVT::f64: 2275 if (FPR_idx != NumFPRs) { 2276 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 2277 2278 if (isVarArg) { 2279 SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 2280 MemOpChains.push_back(Store); 2281 2282 // Float varargs are always shadowed in available integer registers 2283 if (GPR_idx != NumGPRs) { 2284 SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 2285 MemOpChains.push_back(Load.getValue(1)); 2286 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 2287 Load)); 2288 } 2289 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 2290 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 2291 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); 2292 SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 2293 MemOpChains.push_back(Load.getValue(1)); 2294 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 2295 Load)); 2296 } 2297 } else { 2298 // If we have any FPRs remaining, we may also have GPRs remaining. 2299 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 2300 // GPRs. 2301 if (isMachoABI) { 2302 if (GPR_idx != NumGPRs) 2303 ++GPR_idx; 2304 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 2305 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 2306 ++GPR_idx; 2307 } 2308 } 2309 } else { 2310 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 2311 isPPC64, isTailCall, false, MemOpChains, 2312 TailCallArguments); 2313 inMem = true; 2314 } 2315 if (inMem || isMachoABI) { 2316 // Stack align in ELF 2317 if (isELF32_ABI && Align) 2318 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 2319 if (isPPC64) 2320 ArgOffset += 8; 2321 else 2322 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 2323 } 2324 break; 2325 case MVT::v4f32: 2326 case MVT::v4i32: 2327 case MVT::v8i16: 2328 case MVT::v16i8: 2329 if (isVarArg) { 2330 // These go aligned on the stack, or in the corresponding R registers 2331 // when within range. The Darwin PPC ABI doc claims they also go in 2332 // V registers; in fact gcc does this only for arguments that are 2333 // prototyped, not for those that match the ... We do it for all 2334 // arguments, seems to work. 2335 while (ArgOffset % 16 !=0) { 2336 ArgOffset += PtrByteSize; 2337 if (GPR_idx != NumGPRs) 2338 GPR_idx++; 2339 } 2340 // We could elide this store in the case where the object fits 2341 // entirely in R registers. Maybe later. 2342 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, 2343 DAG.getConstant(ArgOffset, PtrVT)); 2344 SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 2345 MemOpChains.push_back(Store); 2346 if (VR_idx != NumVRs) { 2347 SDValue Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0); 2348 MemOpChains.push_back(Load.getValue(1)); 2349 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 2350 } 2351 ArgOffset += 16; 2352 for (unsigned i=0; i<16; i+=PtrByteSize) { 2353 if (GPR_idx == NumGPRs) 2354 break; 2355 SDValue Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff, 2356 DAG.getConstant(i, PtrVT)); 2357 SDValue Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0); 2358 MemOpChains.push_back(Load.getValue(1)); 2359 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 2360 } 2361 break; 2362 } 2363 2364 // Non-varargs Altivec params generally go in registers, but have 2365 // stack space allocated at the end. 2366 if (VR_idx != NumVRs) { 2367 // Doesn't have GPR space allocated. 2368 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 2369 } else if (nAltivecParamsAtEnd==0) { 2370 // We are emitting Altivec params in order. 2371 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 2372 isPPC64, isTailCall, true, MemOpChains, 2373 TailCallArguments); 2374 ArgOffset += 16; 2375 } 2376 break; 2377 } 2378 } 2379 // If all Altivec parameters fit in registers, as they usually do, 2380 // they get stack space following the non-Altivec parameters. We 2381 // don't track this here because nobody below needs it. 2382 // If there are more Altivec parameters than fit in registers emit 2383 // the stores here. 2384 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 2385 unsigned j = 0; 2386 // Offset is aligned; skip 1st 12 params which go in V registers. 2387 ArgOffset = ((ArgOffset+15)/16)*16; 2388 ArgOffset += 12*16; 2389 for (unsigned i = 0; i != NumOps; ++i) { 2390 SDValue Arg = Op.getOperand(5+2*i); 2391 MVT ArgType = Arg.getValueType(); 2392 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 2393 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 2394 if (++j > NumVRs) { 2395 SDValue PtrOff; 2396 // We are emitting Altivec params in order. 2397 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 2398 isPPC64, isTailCall, true, MemOpChains, 2399 TailCallArguments); 2400 ArgOffset += 16; 2401 } 2402 } 2403 } 2404 } 2405 2406 if (!MemOpChains.empty()) 2407 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2408 &MemOpChains[0], MemOpChains.size()); 2409 2410 // Build a sequence of copy-to-reg nodes chained together with token chain 2411 // and flag operands which copy the outgoing args into the appropriate regs. 2412 SDValue InFlag; 2413 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2414 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 2415 InFlag); 2416 InFlag = Chain.getValue(1); 2417 } 2418 2419 // With the ELF 32 ABI, set CR6 to true if this is a vararg call. 2420 if (isVarArg && isELF32_ABI) { 2421 SDValue SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0); 2422 Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag); 2423 InFlag = Chain.getValue(1); 2424 } 2425 2426 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 2427 // might overwrite each other in case of tail call optimization. 2428 if (isTailCall) { 2429 SmallVector<SDValue, 8> MemOpChains2; 2430 // Do not flag preceeding copytoreg stuff together with the following stuff. 2431 InFlag = SDValue(); 2432 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 2433 MemOpChains2); 2434 if (!MemOpChains2.empty()) 2435 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2436 &MemOpChains2[0], MemOpChains2.size()); 2437 2438 // Store the return address to the appropriate stack slot. 2439 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 2440 isPPC64, isMachoABI); 2441 } 2442 2443 // Emit callseq_end just before tailcall node. 2444 if (isTailCall) { 2445 SmallVector<SDValue, 8> CallSeqOps; 2446 SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 2447 CallSeqOps.push_back(Chain); 2448 CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes)); 2449 CallSeqOps.push_back(DAG.getIntPtrConstant(0)); 2450 if (InFlag.Val) 2451 CallSeqOps.push_back(InFlag); 2452 Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0], 2453 CallSeqOps.size()); 2454 InFlag = Chain.getValue(1); 2455 } 2456 2457 std::vector<MVT> NodeTys; 2458 NodeTys.push_back(MVT::Other); // Returns a chain 2459 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 2460 2461 SmallVector<SDValue, 8> Ops; 2462 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; 2463 2464 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2465 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2466 // node so that legalize doesn't hack it. 2467 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2468 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 2469 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 2470 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 2471 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 2472 // If this is an absolute destination address, use the munged value. 2473 Callee = SDValue(Dest, 0); 2474 else { 2475 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 2476 // to do the call, we can't use PPCISD::CALL. 2477 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 2478 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); 2479 InFlag = Chain.getValue(1); 2480 2481 // Copy the callee address into R12/X12 on darwin. 2482 if (isMachoABI) { 2483 unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12; 2484 Chain = DAG.getCopyToReg(Chain, Reg, Callee, InFlag); 2485 InFlag = Chain.getValue(1); 2486 } 2487 2488 NodeTys.clear(); 2489 NodeTys.push_back(MVT::Other); 2490 NodeTys.push_back(MVT::Flag); 2491 Ops.push_back(Chain); 2492 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF; 2493 Callee.Val = 0; 2494 // Add CTR register as callee so a bctr can be emitted later. 2495 if (isTailCall) 2496 Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy())); 2497 } 2498 2499 // If this is a direct call, pass the chain and the callee. 2500 if (Callee.Val) { 2501 Ops.push_back(Chain); 2502 Ops.push_back(Callee); 2503 } 2504 // If this is a tail call add stack pointer delta. 2505 if (isTailCall) 2506 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 2507 2508 // Add argument registers to the end of the list so that they are known live 2509 // into the call. 2510 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2511 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2512 RegsToPass[i].second.getValueType())); 2513 2514 // When performing tail call optimization the callee pops its arguments off 2515 // the stack. Account for this here so these bytes can be pushed back on in 2516 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 2517 int BytesCalleePops = 2518 (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0; 2519 2520 if (InFlag.Val) 2521 Ops.push_back(InFlag); 2522 2523 // Emit tail call. 2524 if (isTailCall) { 2525 assert(InFlag.Val && 2526 "Flag must be set. Depend on flag being set in LowerRET"); 2527 Chain = DAG.getNode(PPCISD::TAILCALL, 2528 Op.Val->getVTList(), &Ops[0], Ops.size()); 2529 return SDValue(Chain.Val, Op.ResNo); 2530 } 2531 2532 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 2533 InFlag = Chain.getValue(1); 2534 2535 Chain = DAG.getCALLSEQ_END(Chain, 2536 DAG.getConstant(NumBytes, PtrVT), 2537 DAG.getConstant(BytesCalleePops, PtrVT), 2538 InFlag); 2539 if (Op.Val->getValueType(0) != MVT::Other) 2540 InFlag = Chain.getValue(1); 2541 2542 SmallVector<SDValue, 16> ResultVals; 2543 SmallVector<CCValAssign, 16> RVLocs; 2544 unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv(); 2545 CCState CCInfo(CallerCC, isVarArg, TM, RVLocs); 2546 CCInfo.AnalyzeCallResult(Op.Val, RetCC_PPC); 2547 2548 // Copy all of the result registers out of their specified physreg. 2549 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2550 CCValAssign &VA = RVLocs[i]; 2551 MVT VT = VA.getValVT(); 2552 assert(VA.isRegLoc() && "Can only return in registers!"); 2553 Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1); 2554 ResultVals.push_back(Chain.getValue(0)); 2555 InFlag = Chain.getValue(2); 2556 } 2557 2558 // If the function returns void, just return the chain. 2559 if (RVLocs.empty()) 2560 return Chain; 2561 2562 // Otherwise, merge everything together with a MERGE_VALUES node. 2563 ResultVals.push_back(Chain); 2564 SDValue Res = DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0], 2565 ResultVals.size()); 2566 return Res.getValue(Op.ResNo); 2567} 2568 2569SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG, 2570 TargetMachine &TM) { 2571 SmallVector<CCValAssign, 16> RVLocs; 2572 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 2573 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 2574 CCState CCInfo(CC, isVarArg, TM, RVLocs); 2575 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC); 2576 2577 // If this is the first return lowered for this function, add the regs to the 2578 // liveout set for the function. 2579 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2580 for (unsigned i = 0; i != RVLocs.size(); ++i) 2581 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2582 } 2583 2584 SDValue Chain = Op.getOperand(0); 2585 2586 Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL); 2587 if (Chain.getOpcode() == PPCISD::TAILCALL) { 2588 SDValue TailCall = Chain; 2589 SDValue TargetAddress = TailCall.getOperand(1); 2590 SDValue StackAdjustment = TailCall.getOperand(2); 2591 2592 assert(((TargetAddress.getOpcode() == ISD::Register && 2593 cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) || 2594 TargetAddress.getOpcode() == ISD::TargetExternalSymbol || 2595 TargetAddress.getOpcode() == ISD::TargetGlobalAddress || 2596 isa<ConstantSDNode>(TargetAddress)) && 2597 "Expecting an global address, external symbol, absolute value or register"); 2598 2599 assert(StackAdjustment.getOpcode() == ISD::Constant && 2600 "Expecting a const value"); 2601 2602 SmallVector<SDValue,8> Operands; 2603 Operands.push_back(Chain.getOperand(0)); 2604 Operands.push_back(TargetAddress); 2605 Operands.push_back(StackAdjustment); 2606 // Copy registers used by the call. Last operand is a flag so it is not 2607 // copied. 2608 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) { 2609 Operands.push_back(Chain.getOperand(i)); 2610 } 2611 return DAG.getNode(PPCISD::TC_RETURN, MVT::Other, &Operands[0], 2612 Operands.size()); 2613 } 2614 2615 SDValue Flag; 2616 2617 // Copy the result values into the output registers. 2618 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2619 CCValAssign &VA = RVLocs[i]; 2620 assert(VA.isRegLoc() && "Can only return in registers!"); 2621 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 2622 Flag = Chain.getValue(1); 2623 } 2624 2625 if (Flag.Val) 2626 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag); 2627 else 2628 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); 2629} 2630 2631SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 2632 const PPCSubtarget &Subtarget) { 2633 // When we pop the dynamic allocation we need to restore the SP link. 2634 2635 // Get the corect type for pointers. 2636 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2637 2638 // Construct the stack pointer operand. 2639 bool IsPPC64 = Subtarget.isPPC64(); 2640 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; 2641 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 2642 2643 // Get the operands for the STACKRESTORE. 2644 SDValue Chain = Op.getOperand(0); 2645 SDValue SaveSP = Op.getOperand(1); 2646 2647 // Load the old link SP. 2648 SDValue LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); 2649 2650 // Restore the stack pointer. 2651 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); 2652 2653 // Store the old link SP. 2654 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); 2655} 2656 2657 2658 2659SDValue 2660PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 2661 MachineFunction &MF = DAG.getMachineFunction(); 2662 bool IsPPC64 = PPCSubTarget.isPPC64(); 2663 bool isMachoABI = PPCSubTarget.isMachoABI(); 2664 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2665 2666 // Get current frame pointer save index. The users of this index will be 2667 // primarily DYNALLOC instructions. 2668 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2669 int RASI = FI->getReturnAddrSaveIndex(); 2670 2671 // If the frame pointer save index hasn't been defined yet. 2672 if (!RASI) { 2673 // Find out what the fix offset of the frame pointer save area. 2674 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isMachoABI); 2675 // Allocate the frame index for frame pointer save area. 2676 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset); 2677 // Save the result. 2678 FI->setReturnAddrSaveIndex(RASI); 2679 } 2680 return DAG.getFrameIndex(RASI, PtrVT); 2681} 2682 2683SDValue 2684PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 2685 MachineFunction &MF = DAG.getMachineFunction(); 2686 bool IsPPC64 = PPCSubTarget.isPPC64(); 2687 bool isMachoABI = PPCSubTarget.isMachoABI(); 2688 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2689 2690 // Get current frame pointer save index. The users of this index will be 2691 // primarily DYNALLOC instructions. 2692 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2693 int FPSI = FI->getFramePointerSaveIndex(); 2694 2695 // If the frame pointer save index hasn't been defined yet. 2696 if (!FPSI) { 2697 // Find out what the fix offset of the frame pointer save area. 2698 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI); 2699 2700 // Allocate the frame index for frame pointer save area. 2701 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 2702 // Save the result. 2703 FI->setFramePointerSaveIndex(FPSI); 2704 } 2705 return DAG.getFrameIndex(FPSI, PtrVT); 2706} 2707 2708SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 2709 SelectionDAG &DAG, 2710 const PPCSubtarget &Subtarget) { 2711 // Get the inputs. 2712 SDValue Chain = Op.getOperand(0); 2713 SDValue Size = Op.getOperand(1); 2714 2715 // Get the corect type for pointers. 2716 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2717 // Negate the size. 2718 SDValue NegSize = DAG.getNode(ISD::SUB, PtrVT, 2719 DAG.getConstant(0, PtrVT), Size); 2720 // Construct a node for the frame pointer save index. 2721 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 2722 // Build a DYNALLOC node. 2723 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 2724 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 2725 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); 2726} 2727 2728SDValue PPCTargetLowering::LowerAtomicLOAD_ADD(SDValue Op, SelectionDAG &DAG) { 2729 MVT VT = Op.Val->getValueType(0); 2730 SDValue Chain = Op.getOperand(0); 2731 SDValue Ptr = Op.getOperand(1); 2732 SDValue Incr = Op.getOperand(2); 2733 2734 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 2735 SDValue Ops[] = { 2736 Chain, 2737 Ptr, 2738 Incr, 2739 }; 2740 return DAG.getNode(PPCISD::ATOMIC_LOAD_ADD, VTs, Ops, 3); 2741} 2742 2743SDValue PPCTargetLowering::LowerAtomicCMP_SWAP(SDValue Op, SelectionDAG &DAG) { 2744 MVT VT = Op.Val->getValueType(0); 2745 SDValue Chain = Op.getOperand(0); 2746 SDValue Ptr = Op.getOperand(1); 2747 SDValue NewVal = Op.getOperand(2); 2748 SDValue OldVal = Op.getOperand(3); 2749 2750 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 2751 SDValue Ops[] = { 2752 Chain, 2753 Ptr, 2754 OldVal, 2755 NewVal, 2756 }; 2757 return DAG.getNode(PPCISD::ATOMIC_CMP_SWAP, VTs, Ops, 4); 2758} 2759 2760SDValue PPCTargetLowering::LowerAtomicSWAP(SDValue Op, SelectionDAG &DAG) { 2761 MVT VT = Op.Val->getValueType(0); 2762 SDValue Chain = Op.getOperand(0); 2763 SDValue Ptr = Op.getOperand(1); 2764 SDValue NewVal = Op.getOperand(2); 2765 2766 SDVTList VTs = DAG.getVTList(VT, MVT::Other); 2767 SDValue Ops[] = { 2768 Chain, 2769 Ptr, 2770 NewVal, 2771 }; 2772 return DAG.getNode(PPCISD::ATOMIC_SWAP, VTs, Ops, 3); 2773} 2774 2775/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 2776/// possible. 2777SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 2778 // Not FP? Not a fsel. 2779 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 2780 !Op.getOperand(2).getValueType().isFloatingPoint()) 2781 return SDValue(); 2782 2783 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2784 2785 // Cannot handle SETEQ/SETNE. 2786 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDValue(); 2787 2788 MVT ResVT = Op.getValueType(); 2789 MVT CmpVT = Op.getOperand(0).getValueType(); 2790 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2791 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 2792 2793 // If the RHS of the comparison is a 0.0, we don't need to do the 2794 // subtraction at all. 2795 if (isFloatingPointZero(RHS)) 2796 switch (CC) { 2797 default: break; // SETUO etc aren't handled by fsel. 2798 case ISD::SETULT: 2799 case ISD::SETOLT: 2800 case ISD::SETLT: 2801 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2802 case ISD::SETUGE: 2803 case ISD::SETOGE: 2804 case ISD::SETGE: 2805 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2806 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2807 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 2808 case ISD::SETUGT: 2809 case ISD::SETOGT: 2810 case ISD::SETGT: 2811 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2812 case ISD::SETULE: 2813 case ISD::SETOLE: 2814 case ISD::SETLE: 2815 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2816 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2817 return DAG.getNode(PPCISD::FSEL, ResVT, 2818 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 2819 } 2820 2821 SDValue Cmp; 2822 switch (CC) { 2823 default: break; // SETUO etc aren't handled by fsel. 2824 case ISD::SETULT: 2825 case ISD::SETOLT: 2826 case ISD::SETLT: 2827 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2828 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2829 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2830 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2831 case ISD::SETUGE: 2832 case ISD::SETOGE: 2833 case ISD::SETGE: 2834 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2835 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2836 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2837 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2838 case ISD::SETUGT: 2839 case ISD::SETOGT: 2840 case ISD::SETGT: 2841 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2842 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2843 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2844 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2845 case ISD::SETULE: 2846 case ISD::SETOLE: 2847 case ISD::SETLE: 2848 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2849 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2850 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2851 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2852 } 2853 return SDValue(); 2854} 2855 2856// FIXME: Split this code up when LegalizeDAGTypes lands. 2857SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 2858 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 2859 SDValue Src = Op.getOperand(0); 2860 if (Src.getValueType() == MVT::f32) 2861 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 2862 2863 SDValue Tmp; 2864 switch (Op.getValueType().getSimpleVT()) { 2865 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 2866 case MVT::i32: 2867 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 2868 break; 2869 case MVT::i64: 2870 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 2871 break; 2872 } 2873 2874 // Convert the FP value to an int value through memory. 2875 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 2876 2877 // Emit a store to the stack slot. 2878 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0); 2879 2880 // Result is a load from the stack slot. If loading 4 bytes, make sure to 2881 // add in a bias. 2882 if (Op.getValueType() == MVT::i32) 2883 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, 2884 DAG.getConstant(4, FIPtr.getValueType())); 2885 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0); 2886} 2887 2888SDValue PPCTargetLowering::LowerFP_ROUND_INREG(SDValue Op, 2889 SelectionDAG &DAG) { 2890 assert(Op.getValueType() == MVT::ppcf128); 2891 SDNode *Node = Op.Val; 2892 assert(Node->getOperand(0).getValueType() == MVT::ppcf128); 2893 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR); 2894 SDValue Lo = Node->getOperand(0).Val->getOperand(0); 2895 SDValue Hi = Node->getOperand(0).Val->getOperand(1); 2896 2897 // This sequence changes FPSCR to do round-to-zero, adds the two halves 2898 // of the long double, and puts FPSCR back the way it was. We do not 2899 // actually model FPSCR. 2900 std::vector<MVT> NodeTys; 2901 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 2902 2903 NodeTys.push_back(MVT::f64); // Return register 2904 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns 2905 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); 2906 MFFSreg = Result.getValue(0); 2907 InFlag = Result.getValue(1); 2908 2909 NodeTys.clear(); 2910 NodeTys.push_back(MVT::Flag); // Returns a flag 2911 Ops[0] = DAG.getConstant(31, MVT::i32); 2912 Ops[1] = InFlag; 2913 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2); 2914 InFlag = Result.getValue(0); 2915 2916 NodeTys.clear(); 2917 NodeTys.push_back(MVT::Flag); // Returns a flag 2918 Ops[0] = DAG.getConstant(30, MVT::i32); 2919 Ops[1] = InFlag; 2920 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2); 2921 InFlag = Result.getValue(0); 2922 2923 NodeTys.clear(); 2924 NodeTys.push_back(MVT::f64); // result of add 2925 NodeTys.push_back(MVT::Flag); // Returns a flag 2926 Ops[0] = Lo; 2927 Ops[1] = Hi; 2928 Ops[2] = InFlag; 2929 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3); 2930 FPreg = Result.getValue(0); 2931 InFlag = Result.getValue(1); 2932 2933 NodeTys.clear(); 2934 NodeTys.push_back(MVT::f64); 2935 Ops[0] = DAG.getConstant(1, MVT::i32); 2936 Ops[1] = MFFSreg; 2937 Ops[2] = FPreg; 2938 Ops[3] = InFlag; 2939 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4); 2940 FPreg = Result.getValue(0); 2941 2942 // We know the low half is about to be thrown away, so just use something 2943 // convenient. 2944 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg); 2945} 2946 2947SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 2948 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 2949 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 2950 return SDValue(); 2951 2952 if (Op.getOperand(0).getValueType() == MVT::i64) { 2953 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 2954 SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 2955 if (Op.getValueType() == MVT::f32) 2956 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); 2957 return FP; 2958 } 2959 2960 assert(Op.getOperand(0).getValueType() == MVT::i32 && 2961 "Unhandled SINT_TO_FP type in custom expander!"); 2962 // Since we only generate this in 64-bit mode, we can take advantage of 2963 // 64-bit registers. In particular, sign extend the input value into the 2964 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 2965 // then lfd it and fcfid it. 2966 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2967 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 2968 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2969 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2970 2971 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 2972 Op.getOperand(0)); 2973 2974 // STD the extended value into the stack slot. 2975 MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx), 2976 MachineMemOperand::MOStore, 0, 8, 8); 2977 SDValue Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 2978 DAG.getEntryNode(), Ext64, FIdx, 2979 DAG.getMemOperand(MO)); 2980 // Load the value as a double. 2981 SDValue Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); 2982 2983 // FCFID it and return it. 2984 SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 2985 if (Op.getValueType() == MVT::f32) 2986 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); 2987 return FP; 2988} 2989 2990SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 2991 /* 2992 The rounding mode is in bits 30:31 of FPSR, and has the following 2993 settings: 2994 00 Round to nearest 2995 01 Round to 0 2996 10 Round to +inf 2997 11 Round to -inf 2998 2999 FLT_ROUNDS, on the other hand, expects the following: 3000 -1 Undefined 3001 0 Round to 0 3002 1 Round to nearest 3003 2 Round to +inf 3004 3 Round to -inf 3005 3006 To perform the conversion, we do: 3007 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 3008 */ 3009 3010 MachineFunction &MF = DAG.getMachineFunction(); 3011 MVT VT = Op.getValueType(); 3012 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3013 std::vector<MVT> NodeTys; 3014 SDValue MFFSreg, InFlag; 3015 3016 // Save FP Control Word to register 3017 NodeTys.push_back(MVT::f64); // return register 3018 NodeTys.push_back(MVT::Flag); // unused in this context 3019 SDValue Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); 3020 3021 // Save FP register to stack slot 3022 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 3023 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 3024 SDValue Store = DAG.getStore(DAG.getEntryNode(), Chain, 3025 StackSlot, NULL, 0); 3026 3027 // Load FP Control Word from low 32 bits of stack slot. 3028 SDValue Four = DAG.getConstant(4, PtrVT); 3029 SDValue Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four); 3030 SDValue CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0); 3031 3032 // Transform as necessary 3033 SDValue CWD1 = 3034 DAG.getNode(ISD::AND, MVT::i32, 3035 CWD, DAG.getConstant(3, MVT::i32)); 3036 SDValue CWD2 = 3037 DAG.getNode(ISD::SRL, MVT::i32, 3038 DAG.getNode(ISD::AND, MVT::i32, 3039 DAG.getNode(ISD::XOR, MVT::i32, 3040 CWD, DAG.getConstant(3, MVT::i32)), 3041 DAG.getConstant(3, MVT::i32)), 3042 DAG.getConstant(1, MVT::i8)); 3043 3044 SDValue RetVal = 3045 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2); 3046 3047 return DAG.getNode((VT.getSizeInBits() < 16 ? 3048 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); 3049} 3050 3051SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { 3052 MVT VT = Op.getValueType(); 3053 unsigned BitWidth = VT.getSizeInBits(); 3054 assert(Op.getNumOperands() == 3 && 3055 VT == Op.getOperand(1).getValueType() && 3056 "Unexpected SHL!"); 3057 3058 // Expand into a bunch of logical ops. Note that these ops 3059 // depend on the PPC behavior for oversized shift amounts. 3060 SDValue Lo = Op.getOperand(0); 3061 SDValue Hi = Op.getOperand(1); 3062 SDValue Amt = Op.getOperand(2); 3063 MVT AmtVT = Amt.getValueType(); 3064 3065 SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, 3066 DAG.getConstant(BitWidth, AmtVT), Amt); 3067 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt); 3068 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1); 3069 SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); 3070 SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, 3071 DAG.getConstant(-BitWidth, AmtVT)); 3072 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5); 3073 SDValue OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); 3074 SDValue OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt); 3075 SDValue OutOps[] = { OutLo, OutHi }; 3076 return DAG.getMergeValues(OutOps, 2); 3077} 3078 3079SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { 3080 MVT VT = Op.getValueType(); 3081 unsigned BitWidth = VT.getSizeInBits(); 3082 assert(Op.getNumOperands() == 3 && 3083 VT == Op.getOperand(1).getValueType() && 3084 "Unexpected SRL!"); 3085 3086 // Expand into a bunch of logical ops. Note that these ops 3087 // depend on the PPC behavior for oversized shift amounts. 3088 SDValue Lo = Op.getOperand(0); 3089 SDValue Hi = Op.getOperand(1); 3090 SDValue Amt = Op.getOperand(2); 3091 MVT AmtVT = Amt.getValueType(); 3092 3093 SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, 3094 DAG.getConstant(BitWidth, AmtVT), Amt); 3095 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); 3096 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); 3097 SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); 3098 SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, 3099 DAG.getConstant(-BitWidth, AmtVT)); 3100 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5); 3101 SDValue OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); 3102 SDValue OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt); 3103 SDValue OutOps[] = { OutLo, OutHi }; 3104 return DAG.getMergeValues(OutOps, 2); 3105} 3106 3107SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { 3108 MVT VT = Op.getValueType(); 3109 unsigned BitWidth = VT.getSizeInBits(); 3110 assert(Op.getNumOperands() == 3 && 3111 VT == Op.getOperand(1).getValueType() && 3112 "Unexpected SRA!"); 3113 3114 // Expand into a bunch of logical ops, followed by a select_cc. 3115 SDValue Lo = Op.getOperand(0); 3116 SDValue Hi = Op.getOperand(1); 3117 SDValue Amt = Op.getOperand(2); 3118 MVT AmtVT = Amt.getValueType(); 3119 3120 SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, 3121 DAG.getConstant(BitWidth, AmtVT), Amt); 3122 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); 3123 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); 3124 SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); 3125 SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, 3126 DAG.getConstant(-BitWidth, AmtVT)); 3127 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5); 3128 SDValue OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt); 3129 SDValue OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT), 3130 Tmp4, Tmp6, ISD::SETLE); 3131 SDValue OutOps[] = { OutLo, OutHi }; 3132 return DAG.getMergeValues(OutOps, 2); 3133} 3134 3135//===----------------------------------------------------------------------===// 3136// Vector related lowering. 3137// 3138 3139// If this is a vector of constants or undefs, get the bits. A bit in 3140// UndefBits is set if the corresponding element of the vector is an 3141// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 3142// zero. Return true if this is not an array of constants, false if it is. 3143// 3144static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 3145 uint64_t UndefBits[2]) { 3146 // Start with zero'd results. 3147 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 3148 3149 unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits(); 3150 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3151 SDValue OpVal = BV->getOperand(i); 3152 3153 unsigned PartNo = i >= e/2; // In the upper 128 bits? 3154 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 3155 3156 uint64_t EltBits = 0; 3157 if (OpVal.getOpcode() == ISD::UNDEF) { 3158 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 3159 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 3160 continue; 3161 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 3162 EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 3163 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 3164 assert(CN->getValueType(0) == MVT::f32 && 3165 "Only one legal FP vector type!"); 3166 EltBits = FloatToBits(CN->getValueAPF().convertToFloat()); 3167 } else { 3168 // Nonconstant element. 3169 return true; 3170 } 3171 3172 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 3173 } 3174 3175 //printf("%llx %llx %llx %llx\n", 3176 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 3177 return false; 3178} 3179 3180// If this is a splat (repetition) of a value across the whole vector, return 3181// the smallest size that splats it. For example, "0x01010101010101..." is a 3182// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 3183// SplatSize = 1 byte. 3184static bool isConstantSplat(const uint64_t Bits128[2], 3185 const uint64_t Undef128[2], 3186 unsigned &SplatBits, unsigned &SplatUndef, 3187 unsigned &SplatSize) { 3188 3189 // Don't let undefs prevent splats from matching. See if the top 64-bits are 3190 // the same as the lower 64-bits, ignoring undefs. 3191 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 3192 return false; // Can't be a splat if two pieces don't match. 3193 3194 uint64_t Bits64 = Bits128[0] | Bits128[1]; 3195 uint64_t Undef64 = Undef128[0] & Undef128[1]; 3196 3197 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 3198 // undefs. 3199 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 3200 return false; // Can't be a splat if two pieces don't match. 3201 3202 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 3203 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 3204 3205 // If the top 16-bits are different than the lower 16-bits, ignoring 3206 // undefs, we have an i32 splat. 3207 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 3208 SplatBits = Bits32; 3209 SplatUndef = Undef32; 3210 SplatSize = 4; 3211 return true; 3212 } 3213 3214 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 3215 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 3216 3217 // If the top 8-bits are different than the lower 8-bits, ignoring 3218 // undefs, we have an i16 splat. 3219 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 3220 SplatBits = Bits16; 3221 SplatUndef = Undef16; 3222 SplatSize = 2; 3223 return true; 3224 } 3225 3226 // Otherwise, we have an 8-bit splat. 3227 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 3228 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 3229 SplatSize = 1; 3230 return true; 3231} 3232 3233/// BuildSplatI - Build a canonical splati of Val with an element size of 3234/// SplatSize. Cast the result to VT. 3235static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT, 3236 SelectionDAG &DAG) { 3237 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 3238 3239 static const MVT VTys[] = { // canonical VT to use for each size. 3240 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 3241 }; 3242 3243 MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 3244 3245 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 3246 if (Val == -1) 3247 SplatSize = 1; 3248 3249 MVT CanonicalVT = VTys[SplatSize-1]; 3250 3251 // Build a canonical splat for this value. 3252 SDValue Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType()); 3253 SmallVector<SDValue, 8> Ops; 3254 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 3255 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, 3256 &Ops[0], Ops.size()); 3257 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); 3258} 3259 3260/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 3261/// specified intrinsic ID. 3262static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 3263 SelectionDAG &DAG, 3264 MVT DestVT = MVT::Other) { 3265 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 3266 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 3267 DAG.getConstant(IID, MVT::i32), LHS, RHS); 3268} 3269 3270/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 3271/// specified intrinsic ID. 3272static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 3273 SDValue Op2, SelectionDAG &DAG, 3274 MVT DestVT = MVT::Other) { 3275 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 3276 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 3277 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 3278} 3279 3280 3281/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 3282/// amount. The result has the specified value type. 3283static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 3284 MVT VT, SelectionDAG &DAG) { 3285 // Force LHS/RHS to be the right type. 3286 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 3287 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 3288 3289 SDValue Ops[16]; 3290 for (unsigned i = 0; i != 16; ++i) 3291 Ops[i] = DAG.getConstant(i+Amt, MVT::i8); 3292 SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 3293 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); 3294 return DAG.getNode(ISD::BIT_CONVERT, VT, T); 3295} 3296 3297// If this is a case we can't handle, return null and let the default 3298// expansion code take care of it. If we CAN select this case, and if it 3299// selects to a single instruction, return Op. Otherwise, if we can codegen 3300// this case more efficiently than a constant pool load, lower it to the 3301// sequence of ops that should be used. 3302SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 3303 SelectionDAG &DAG) { 3304 // If this is a vector of constants or undefs, get the bits. A bit in 3305 // UndefBits is set if the corresponding element of the vector is an 3306 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 3307 // zero. 3308 uint64_t VectorBits[2]; 3309 uint64_t UndefBits[2]; 3310 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 3311 return SDValue(); // Not a constant vector. 3312 3313 // If this is a splat (repetition) of a value across the whole vector, return 3314 // the smallest size that splats it. For example, "0x01010101010101..." is a 3315 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 3316 // SplatSize = 1 byte. 3317 unsigned SplatBits, SplatUndef, SplatSize; 3318 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 3319 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 3320 3321 // First, handle single instruction cases. 3322 3323 // All zeros? 3324 if (SplatBits == 0) { 3325 // Canonicalize all zero vectors to be v4i32. 3326 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 3327 SDValue Z = DAG.getConstant(0, MVT::i32); 3328 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 3329 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 3330 } 3331 return Op; 3332 } 3333 3334 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 3335 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 3336 if (SextVal >= -16 && SextVal <= 15) 3337 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 3338 3339 3340 // Two instruction sequences. 3341 3342 // If this value is in the range [-32,30] and is even, use: 3343 // tmp = VSPLTI[bhw], result = add tmp, tmp 3344 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 3345 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG); 3346 Res = DAG.getNode(ISD::ADD, Res.getValueType(), Res, Res); 3347 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 3348 } 3349 3350 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 3351 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 3352 // for fneg/fabs. 3353 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 3354 // Make -1 and vspltisw -1: 3355 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 3356 3357 // Make the VSLW intrinsic, computing 0x8000_0000. 3358 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 3359 OnesV, DAG); 3360 3361 // xor by OnesV to invert it. 3362 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 3363 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 3364 } 3365 3366 // Check to see if this is a wide variety of vsplti*, binop self cases. 3367 unsigned SplatBitSize = SplatSize*8; 3368 static const signed char SplatCsts[] = { 3369 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 3370 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 3371 }; 3372 3373 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 3374 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 3375 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 3376 int i = SplatCsts[idx]; 3377 3378 // Figure out what shift amount will be used by altivec if shifted by i in 3379 // this splat size. 3380 unsigned TypeShiftAmt = i & (SplatBitSize-1); 3381 3382 // vsplti + shl self. 3383 if (SextVal == (i << (int)TypeShiftAmt)) { 3384 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 3385 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3386 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 3387 Intrinsic::ppc_altivec_vslw 3388 }; 3389 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 3390 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 3391 } 3392 3393 // vsplti + srl self. 3394 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3395 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 3396 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3397 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 3398 Intrinsic::ppc_altivec_vsrw 3399 }; 3400 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 3401 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 3402 } 3403 3404 // vsplti + sra self. 3405 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3406 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 3407 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3408 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 3409 Intrinsic::ppc_altivec_vsraw 3410 }; 3411 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 3412 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 3413 } 3414 3415 // vsplti + rol self. 3416 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 3417 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 3418 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 3419 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3420 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 3421 Intrinsic::ppc_altivec_vrlw 3422 }; 3423 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 3424 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 3425 } 3426 3427 // t = vsplti c, result = vsldoi t, t, 1 3428 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 3429 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 3430 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 3431 } 3432 // t = vsplti c, result = vsldoi t, t, 2 3433 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 3434 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 3435 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 3436 } 3437 // t = vsplti c, result = vsldoi t, t, 3 3438 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 3439 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 3440 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 3441 } 3442 } 3443 3444 // Three instruction sequences. 3445 3446 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 3447 if (SextVal >= 0 && SextVal <= 31) { 3448 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); 3449 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 3450 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS); 3451 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 3452 } 3453 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 3454 if (SextVal >= -31 && SextVal <= 0) { 3455 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); 3456 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 3457 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); 3458 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 3459 } 3460 } 3461 3462 return SDValue(); 3463} 3464 3465/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 3466/// the specified operations to build the shuffle. 3467static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 3468 SDValue RHS, SelectionDAG &DAG) { 3469 unsigned OpNum = (PFEntry >> 26) & 0x0F; 3470 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 3471 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 3472 3473 enum { 3474 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 3475 OP_VMRGHW, 3476 OP_VMRGLW, 3477 OP_VSPLTISW0, 3478 OP_VSPLTISW1, 3479 OP_VSPLTISW2, 3480 OP_VSPLTISW3, 3481 OP_VSLDOI4, 3482 OP_VSLDOI8, 3483 OP_VSLDOI12 3484 }; 3485 3486 if (OpNum == OP_COPY) { 3487 if (LHSID == (1*9+2)*9+3) return LHS; 3488 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 3489 return RHS; 3490 } 3491 3492 SDValue OpLHS, OpRHS; 3493 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 3494 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 3495 3496 unsigned ShufIdxs[16]; 3497 switch (OpNum) { 3498 default: assert(0 && "Unknown i32 permute!"); 3499 case OP_VMRGHW: 3500 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 3501 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 3502 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 3503 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 3504 break; 3505 case OP_VMRGLW: 3506 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 3507 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 3508 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 3509 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 3510 break; 3511 case OP_VSPLTISW0: 3512 for (unsigned i = 0; i != 16; ++i) 3513 ShufIdxs[i] = (i&3)+0; 3514 break; 3515 case OP_VSPLTISW1: 3516 for (unsigned i = 0; i != 16; ++i) 3517 ShufIdxs[i] = (i&3)+4; 3518 break; 3519 case OP_VSPLTISW2: 3520 for (unsigned i = 0; i != 16; ++i) 3521 ShufIdxs[i] = (i&3)+8; 3522 break; 3523 case OP_VSPLTISW3: 3524 for (unsigned i = 0; i != 16; ++i) 3525 ShufIdxs[i] = (i&3)+12; 3526 break; 3527 case OP_VSLDOI4: 3528 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 3529 case OP_VSLDOI8: 3530 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 3531 case OP_VSLDOI12: 3532 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 3533 } 3534 SDValue Ops[16]; 3535 for (unsigned i = 0; i != 16; ++i) 3536 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8); 3537 3538 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 3539 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 3540} 3541 3542/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 3543/// is a shuffle we can handle in a single instruction, return it. Otherwise, 3544/// return the code it can be lowered into. Worst case, it can always be 3545/// lowered into a vperm. 3546SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 3547 SelectionDAG &DAG) { 3548 SDValue V1 = Op.getOperand(0); 3549 SDValue V2 = Op.getOperand(1); 3550 SDValue PermMask = Op.getOperand(2); 3551 3552 // Cases that are handled by instructions that take permute immediates 3553 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 3554 // selected by the instruction selector. 3555 if (V2.getOpcode() == ISD::UNDEF) { 3556 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 3557 PPC::isSplatShuffleMask(PermMask.Val, 2) || 3558 PPC::isSplatShuffleMask(PermMask.Val, 4) || 3559 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 3560 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 3561 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 3562 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 3563 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 3564 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 3565 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 3566 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 3567 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 3568 return Op; 3569 } 3570 } 3571 3572 // Altivec has a variety of "shuffle immediates" that take two vector inputs 3573 // and produce a fixed permutation. If any of these match, do not lower to 3574 // VPERM. 3575 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 3576 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 3577 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 3578 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 3579 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 3580 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 3581 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 3582 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 3583 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 3584 return Op; 3585 3586 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 3587 // perfect shuffle table to emit an optimal matching sequence. 3588 unsigned PFIndexes[4]; 3589 bool isFourElementShuffle = true; 3590 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 3591 unsigned EltNo = 8; // Start out undef. 3592 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 3593 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 3594 continue; // Undef, ignore it. 3595 3596 unsigned ByteSource = 3597 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); 3598 if ((ByteSource & 3) != j) { 3599 isFourElementShuffle = false; 3600 break; 3601 } 3602 3603 if (EltNo == 8) { 3604 EltNo = ByteSource/4; 3605 } else if (EltNo != ByteSource/4) { 3606 isFourElementShuffle = false; 3607 break; 3608 } 3609 } 3610 PFIndexes[i] = EltNo; 3611 } 3612 3613 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 3614 // perfect shuffle vector to determine if it is cost effective to do this as 3615 // discrete instructions, or whether we should use a vperm. 3616 if (isFourElementShuffle) { 3617 // Compute the index in the perfect shuffle table. 3618 unsigned PFTableIndex = 3619 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 3620 3621 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 3622 unsigned Cost = (PFEntry >> 30); 3623 3624 // Determining when to avoid vperm is tricky. Many things affect the cost 3625 // of vperm, particularly how many times the perm mask needs to be computed. 3626 // For example, if the perm mask can be hoisted out of a loop or is already 3627 // used (perhaps because there are multiple permutes with the same shuffle 3628 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 3629 // the loop requires an extra register. 3630 // 3631 // As a compromise, we only emit discrete instructions if the shuffle can be 3632 // generated in 3 or fewer operations. When we have loop information 3633 // available, if this block is within a loop, we should avoid using vperm 3634 // for 3-operation perms and use a constant pool load instead. 3635 if (Cost < 3) 3636 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 3637 } 3638 3639 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 3640 // vector that will get spilled to the constant pool. 3641 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 3642 3643 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 3644 // that it is in input element units, not in bytes. Convert now. 3645 MVT EltVT = V1.getValueType().getVectorElementType(); 3646 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 3647 3648 SmallVector<SDValue, 16> ResultMask; 3649 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 3650 unsigned SrcElt; 3651 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 3652 SrcElt = 0; 3653 else 3654 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 3655 3656 for (unsigned j = 0; j != BytesPerElement; ++j) 3657 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 3658 MVT::i8)); 3659 } 3660 3661 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 3662 &ResultMask[0], ResultMask.size()); 3663 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 3664} 3665 3666/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 3667/// altivec comparison. If it is, return true and fill in Opc/isDot with 3668/// information about the intrinsic. 3669static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 3670 bool &isDot) { 3671 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); 3672 CompareOpc = -1; 3673 isDot = false; 3674 switch (IntrinsicID) { 3675 default: return false; 3676 // Comparison predicates. 3677 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 3678 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 3679 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 3680 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 3681 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 3682 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 3683 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 3684 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 3685 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 3686 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 3687 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 3688 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 3689 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 3690 3691 // Normal Comparisons. 3692 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 3693 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 3694 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 3695 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 3696 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 3697 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 3698 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 3699 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 3700 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 3701 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 3702 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 3703 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 3704 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 3705 } 3706 return true; 3707} 3708 3709/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 3710/// lower, do it, otherwise return null. 3711SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 3712 SelectionDAG &DAG) { 3713 // If this is a lowered altivec predicate compare, CompareOpc is set to the 3714 // opcode number of the comparison. 3715 int CompareOpc; 3716 bool isDot; 3717 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 3718 return SDValue(); // Don't custom lower most intrinsics. 3719 3720 // If this is a non-dot comparison, make the VCMP node and we are done. 3721 if (!isDot) { 3722 SDValue Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 3723 Op.getOperand(1), Op.getOperand(2), 3724 DAG.getConstant(CompareOpc, MVT::i32)); 3725 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 3726 } 3727 3728 // Create the PPCISD altivec 'dot' comparison node. 3729 SDValue Ops[] = { 3730 Op.getOperand(2), // LHS 3731 Op.getOperand(3), // RHS 3732 DAG.getConstant(CompareOpc, MVT::i32) 3733 }; 3734 std::vector<MVT> VTs; 3735 VTs.push_back(Op.getOperand(2).getValueType()); 3736 VTs.push_back(MVT::Flag); 3737 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 3738 3739 // Now that we have the comparison, emit a copy from the CR to a GPR. 3740 // This is flagged to the above dot comparison. 3741 SDValue Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 3742 DAG.getRegister(PPC::CR6, MVT::i32), 3743 CompNode.getValue(1)); 3744 3745 // Unpack the result based on how the target uses it. 3746 unsigned BitNo; // Bit # of CR6. 3747 bool InvertBit; // Invert result? 3748 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 3749 default: // Can't happen, don't crash on invalid number though. 3750 case 0: // Return the value of the EQ bit of CR6. 3751 BitNo = 0; InvertBit = false; 3752 break; 3753 case 1: // Return the inverted value of the EQ bit of CR6. 3754 BitNo = 0; InvertBit = true; 3755 break; 3756 case 2: // Return the value of the LT bit of CR6. 3757 BitNo = 2; InvertBit = false; 3758 break; 3759 case 3: // Return the inverted value of the LT bit of CR6. 3760 BitNo = 2; InvertBit = true; 3761 break; 3762 } 3763 3764 // Shift the bit into the low position. 3765 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 3766 DAG.getConstant(8-(3-BitNo), MVT::i32)); 3767 // Isolate the bit. 3768 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 3769 DAG.getConstant(1, MVT::i32)); 3770 3771 // If we are supposed to, toggle the bit. 3772 if (InvertBit) 3773 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 3774 DAG.getConstant(1, MVT::i32)); 3775 return Flags; 3776} 3777 3778SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 3779 SelectionDAG &DAG) { 3780 // Create a stack slot that is 16-byte aligned. 3781 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 3782 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 3783 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3784 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 3785 3786 // Store the input value into Value#0 of the stack slot. 3787 SDValue Store = DAG.getStore(DAG.getEntryNode(), 3788 Op.getOperand(0), FIdx, NULL, 0); 3789 // Load it out. 3790 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); 3791} 3792 3793SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { 3794 if (Op.getValueType() == MVT::v4i32) { 3795 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3796 3797 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 3798 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 3799 3800 SDValue RHSSwap = // = vrlw RHS, 16 3801 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 3802 3803 // Shrinkify inputs to v8i16. 3804 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 3805 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 3806 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 3807 3808 // Low parts multiplied together, generating 32-bit results (we ignore the 3809 // top parts). 3810 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 3811 LHS, RHS, DAG, MVT::v4i32); 3812 3813 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 3814 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 3815 // Shift the high parts up 16 bits. 3816 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 3817 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 3818 } else if (Op.getValueType() == MVT::v8i16) { 3819 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3820 3821 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 3822 3823 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 3824 LHS, RHS, Zero, DAG); 3825 } else if (Op.getValueType() == MVT::v16i8) { 3826 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3827 3828 // Multiply the even 8-bit parts, producing 16-bit sums. 3829 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 3830 LHS, RHS, DAG, MVT::v8i16); 3831 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 3832 3833 // Multiply the odd 8-bit parts, producing 16-bit sums. 3834 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 3835 LHS, RHS, DAG, MVT::v8i16); 3836 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 3837 3838 // Merge the results together. 3839 SDValue Ops[16]; 3840 for (unsigned i = 0; i != 8; ++i) { 3841 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 3842 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 3843 } 3844 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 3845 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 3846 } else { 3847 assert(0 && "Unknown mul to lower!"); 3848 abort(); 3849 } 3850} 3851 3852/// LowerOperation - Provide custom lowering hooks for some operations. 3853/// 3854SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 3855 switch (Op.getOpcode()) { 3856 default: assert(0 && "Wasn't expecting to be able to lower this!"); 3857 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 3858 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 3859 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 3860 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 3861 case ISD::SETCC: return LowerSETCC(Op, DAG); 3862 case ISD::VASTART: 3863 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3864 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3865 3866 case ISD::VAARG: 3867 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3868 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3869 3870 case ISD::FORMAL_ARGUMENTS: 3871 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, 3872 VarArgsStackOffset, VarArgsNumGPR, 3873 VarArgsNumFPR, PPCSubTarget); 3874 3875 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget, 3876 getTargetMachine()); 3877 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine()); 3878 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 3879 case ISD::DYNAMIC_STACKALLOC: 3880 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 3881 3882 case ISD::ATOMIC_LOAD_ADD: return LowerAtomicLOAD_ADD(Op, DAG); 3883 case ISD::ATOMIC_CMP_SWAP: return LowerAtomicCMP_SWAP(Op, DAG); 3884 case ISD::ATOMIC_SWAP: return LowerAtomicSWAP(Op, DAG); 3885 3886 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 3887 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 3888 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 3889 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG); 3890 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 3891 3892 // Lower 64-bit shifts. 3893 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 3894 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 3895 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 3896 3897 // Vector-related lowering. 3898 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 3899 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 3900 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 3901 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 3902 case ISD::MUL: return LowerMUL(Op, DAG); 3903 3904 // Frame & Return address. 3905 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 3906 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 3907 } 3908 return SDValue(); 3909} 3910 3911SDNode *PPCTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { 3912 switch (N->getOpcode()) { 3913 default: assert(0 && "Wasn't expecting to be able to lower this!"); 3914 case ISD::FP_TO_SINT: { 3915 SDValue Res = LowerFP_TO_SINT(SDValue(N, 0), DAG); 3916 // Use MERGE_VALUES to drop the chain result value and get a node with one 3917 // result. This requires turning off getMergeValues simplification, since 3918 // otherwise it will give us Res back. 3919 return DAG.getMergeValues(&Res, 1, false).Val; 3920 } 3921 } 3922} 3923 3924 3925//===----------------------------------------------------------------------===// 3926// Other Lowering Code 3927//===----------------------------------------------------------------------===// 3928 3929MachineBasicBlock * 3930PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 3931 MachineBasicBlock *BB) { 3932 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3933 3934 // To "insert" these instructions we actually have to insert their 3935 // control-flow patterns. 3936 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3937 MachineFunction::iterator It = BB; 3938 ++It; 3939 3940 MachineFunction *F = BB->getParent(); 3941 3942 if (MI->getOpcode() == PPC::SELECT_CC_I4 || 3943 MI->getOpcode() == PPC::SELECT_CC_I8 || 3944 MI->getOpcode() == PPC::SELECT_CC_F4 || 3945 MI->getOpcode() == PPC::SELECT_CC_F8 || 3946 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 3947 3948 // The incoming instruction knows the destination vreg to set, the 3949 // condition code register to branch on, the true/false values to 3950 // select between, and a branch opcode to use. 3951 3952 // thisMBB: 3953 // ... 3954 // TrueVal = ... 3955 // cmpTY ccX, r1, r2 3956 // bCC copy1MBB 3957 // fallthrough --> copy0MBB 3958 MachineBasicBlock *thisMBB = BB; 3959 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 3960 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 3961 unsigned SelectPred = MI->getOperand(4).getImm(); 3962 BuildMI(BB, TII->get(PPC::BCC)) 3963 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 3964 F->insert(It, copy0MBB); 3965 F->insert(It, sinkMBB); 3966 // Update machine-CFG edges by transferring all successors of the current 3967 // block to the new block which will contain the Phi node for the select. 3968 sinkMBB->transferSuccessors(BB); 3969 // Next, add the true and fallthrough blocks as its successors. 3970 BB->addSuccessor(copy0MBB); 3971 BB->addSuccessor(sinkMBB); 3972 3973 // copy0MBB: 3974 // %FalseValue = ... 3975 // # fallthrough to sinkMBB 3976 BB = copy0MBB; 3977 3978 // Update machine-CFG edges 3979 BB->addSuccessor(sinkMBB); 3980 3981 // sinkMBB: 3982 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 3983 // ... 3984 BB = sinkMBB; 3985 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 3986 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 3987 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 3988 } 3989 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32 || 3990 MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) { 3991 bool is64bit = MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64; 3992 3993 unsigned dest = MI->getOperand(0).getReg(); 3994 unsigned ptrA = MI->getOperand(1).getReg(); 3995 unsigned ptrB = MI->getOperand(2).getReg(); 3996 unsigned incr = MI->getOperand(3).getReg(); 3997 3998 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 3999 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4000 F->insert(It, loopMBB); 4001 F->insert(It, exitMBB); 4002 exitMBB->transferSuccessors(BB); 4003 4004 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4005 unsigned TmpReg = RegInfo.createVirtualRegister( 4006 is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass : 4007 (const TargetRegisterClass *) &PPC::G8RCRegClass); 4008 4009 // thisMBB: 4010 // ... 4011 // fallthrough --> loopMBB 4012 BB->addSuccessor(loopMBB); 4013 4014 // loopMBB: 4015 // l[wd]arx dest, ptr 4016 // add r0, dest, incr 4017 // st[wd]cx. r0, ptr 4018 // bne- loopMBB 4019 // fallthrough --> exitMBB 4020 BB = loopMBB; 4021 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4022 .addReg(ptrA).addReg(ptrB); 4023 BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), TmpReg) 4024 .addReg(incr).addReg(dest); 4025 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4026 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 4027 BuildMI(BB, TII->get(PPC::BCC)) 4028 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4029 BB->addSuccessor(loopMBB); 4030 BB->addSuccessor(exitMBB); 4031 4032 // exitMBB: 4033 // ... 4034 BB = exitMBB; 4035 } 4036 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 4037 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 4038 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 4039 4040 unsigned dest = MI->getOperand(0).getReg(); 4041 unsigned ptrA = MI->getOperand(1).getReg(); 4042 unsigned ptrB = MI->getOperand(2).getReg(); 4043 unsigned oldval = MI->getOperand(3).getReg(); 4044 unsigned newval = MI->getOperand(4).getReg(); 4045 4046 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4047 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4048 F->insert(It, loopMBB); 4049 F->insert(It, exitMBB); 4050 exitMBB->transferSuccessors(BB); 4051 4052 // thisMBB: 4053 // ... 4054 // fallthrough --> loopMBB 4055 BB->addSuccessor(loopMBB); 4056 4057 // loopMBB: 4058 // l[wd]arx dest, ptr 4059 // cmp[wd] dest, oldval 4060 // bne- exitMBB 4061 // st[wd]cx. newval, ptr 4062 // bne- loopMBB 4063 // fallthrough --> exitMBB 4064 BB = loopMBB; 4065 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4066 .addReg(ptrA).addReg(ptrB); 4067 BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 4068 .addReg(oldval).addReg(dest); 4069 BuildMI(BB, TII->get(PPC::BCC)) 4070 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(exitMBB); 4071 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4072 .addReg(newval).addReg(ptrA).addReg(ptrB); 4073 BuildMI(BB, TII->get(PPC::BCC)) 4074 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4075 BB->addSuccessor(loopMBB); 4076 BB->addSuccessor(exitMBB); 4077 4078 // exitMBB: 4079 // ... 4080 BB = exitMBB; 4081 } 4082 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32 || 4083 MI->getOpcode() == PPC::ATOMIC_SWAP_I64) { 4084 bool is64bit = MI->getOpcode() == PPC::ATOMIC_SWAP_I64; 4085 4086 unsigned dest = MI->getOperand(0).getReg(); 4087 unsigned ptrA = MI->getOperand(1).getReg(); 4088 unsigned ptrB = MI->getOperand(2).getReg(); 4089 unsigned newval = MI->getOperand(3).getReg(); 4090 4091 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4092 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4093 F->insert(It, loopMBB); 4094 F->insert(It, exitMBB); 4095 exitMBB->transferSuccessors(BB); 4096 4097 // thisMBB: 4098 // ... 4099 // fallthrough --> loopMBB 4100 BB->addSuccessor(loopMBB); 4101 4102 // loopMBB: 4103 // l[wd]arx dest, ptr 4104 // st[wd]cx. newval, ptr 4105 // bne- loopMBB 4106 // fallthrough --> exitMBB 4107 BB = loopMBB; 4108 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4109 .addReg(ptrA).addReg(ptrB); 4110 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4111 .addReg(newval).addReg(ptrA).addReg(ptrB); 4112 BuildMI(BB, TII->get(PPC::BCC)) 4113 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4114 BB->addSuccessor(loopMBB); 4115 BB->addSuccessor(exitMBB); 4116 4117 // exitMBB: 4118 // ... 4119 BB = exitMBB; 4120 } 4121 else { 4122 assert(0 && "Unexpected instr type to insert"); 4123 } 4124 4125 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 4126 return BB; 4127} 4128 4129//===----------------------------------------------------------------------===// 4130// Target Optimization Hooks 4131//===----------------------------------------------------------------------===// 4132 4133SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 4134 DAGCombinerInfo &DCI) const { 4135 TargetMachine &TM = getTargetMachine(); 4136 SelectionDAG &DAG = DCI.DAG; 4137 switch (N->getOpcode()) { 4138 default: break; 4139 case PPCISD::SHL: 4140 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 4141 if (C->getValue() == 0) // 0 << V -> 0. 4142 return N->getOperand(0); 4143 } 4144 break; 4145 case PPCISD::SRL: 4146 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 4147 if (C->getValue() == 0) // 0 >>u V -> 0. 4148 return N->getOperand(0); 4149 } 4150 break; 4151 case PPCISD::SRA: 4152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 4153 if (C->getValue() == 0 || // 0 >>s V -> 0. 4154 C->isAllOnesValue()) // -1 >>s V -> -1. 4155 return N->getOperand(0); 4156 } 4157 break; 4158 4159 case ISD::SINT_TO_FP: 4160 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 4161 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 4162 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 4163 // We allow the src/dst to be either f32/f64, but the intermediate 4164 // type must be i64. 4165 if (N->getOperand(0).getValueType() == MVT::i64 && 4166 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 4167 SDValue Val = N->getOperand(0).getOperand(0); 4168 if (Val.getValueType() == MVT::f32) { 4169 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 4170 DCI.AddToWorklist(Val.Val); 4171 } 4172 4173 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 4174 DCI.AddToWorklist(Val.Val); 4175 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 4176 DCI.AddToWorklist(Val.Val); 4177 if (N->getValueType(0) == MVT::f32) { 4178 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val, 4179 DAG.getIntPtrConstant(0)); 4180 DCI.AddToWorklist(Val.Val); 4181 } 4182 return Val; 4183 } else if (N->getOperand(0).getValueType() == MVT::i32) { 4184 // If the intermediate type is i32, we can avoid the load/store here 4185 // too. 4186 } 4187 } 4188 } 4189 break; 4190 case ISD::STORE: 4191 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 4192 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 4193 !cast<StoreSDNode>(N)->isTruncatingStore() && 4194 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 4195 N->getOperand(1).getValueType() == MVT::i32 && 4196 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 4197 SDValue Val = N->getOperand(1).getOperand(0); 4198 if (Val.getValueType() == MVT::f32) { 4199 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 4200 DCI.AddToWorklist(Val.Val); 4201 } 4202 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 4203 DCI.AddToWorklist(Val.Val); 4204 4205 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 4206 N->getOperand(2), N->getOperand(3)); 4207 DCI.AddToWorklist(Val.Val); 4208 return Val; 4209 } 4210 4211 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 4212 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 4213 N->getOperand(1).Val->hasOneUse() && 4214 (N->getOperand(1).getValueType() == MVT::i32 || 4215 N->getOperand(1).getValueType() == MVT::i16)) { 4216 SDValue BSwapOp = N->getOperand(1).getOperand(0); 4217 // Do an any-extend to 32-bits if this is a half-word input. 4218 if (BSwapOp.getValueType() == MVT::i16) 4219 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); 4220 4221 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, 4222 N->getOperand(2), N->getOperand(3), 4223 DAG.getValueType(N->getOperand(1).getValueType())); 4224 } 4225 break; 4226 case ISD::BSWAP: 4227 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 4228 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && 4229 N->getOperand(0).hasOneUse() && 4230 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 4231 SDValue Load = N->getOperand(0); 4232 LoadSDNode *LD = cast<LoadSDNode>(Load); 4233 // Create the byte-swapping load. 4234 std::vector<MVT> VTs; 4235 VTs.push_back(MVT::i32); 4236 VTs.push_back(MVT::Other); 4237 SDValue MO = DAG.getMemOperand(LD->getMemOperand()); 4238 SDValue Ops[] = { 4239 LD->getChain(), // Chain 4240 LD->getBasePtr(), // Ptr 4241 MO, // MemOperand 4242 DAG.getValueType(N->getValueType(0)) // VT 4243 }; 4244 SDValue BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); 4245 4246 // If this is an i16 load, insert the truncate. 4247 SDValue ResVal = BSLoad; 4248 if (N->getValueType(0) == MVT::i16) 4249 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); 4250 4251 // First, combine the bswap away. This makes the value produced by the 4252 // load dead. 4253 DCI.CombineTo(N, ResVal); 4254 4255 // Next, combine the load away, we give it a bogus result value but a real 4256 // chain result. The result value is dead because the bswap is dead. 4257 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); 4258 4259 // Return N so it doesn't get rechecked! 4260 return SDValue(N, 0); 4261 } 4262 4263 break; 4264 case PPCISD::VCMP: { 4265 // If a VCMPo node already exists with exactly the same operands as this 4266 // node, use its result instead of this node (VCMPo computes both a CR6 and 4267 // a normal output). 4268 // 4269 if (!N->getOperand(0).hasOneUse() && 4270 !N->getOperand(1).hasOneUse() && 4271 !N->getOperand(2).hasOneUse()) { 4272 4273 // Scan all of the users of the LHS, looking for VCMPo's that match. 4274 SDNode *VCMPoNode = 0; 4275 4276 SDNode *LHSN = N->getOperand(0).Val; 4277 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 4278 UI != E; ++UI) 4279 if (UI->getOpcode() == PPCISD::VCMPo && 4280 UI->getOperand(1) == N->getOperand(1) && 4281 UI->getOperand(2) == N->getOperand(2) && 4282 UI->getOperand(0) == N->getOperand(0)) { 4283 VCMPoNode = *UI; 4284 break; 4285 } 4286 4287 // If there is no VCMPo node, or if the flag value has a single use, don't 4288 // transform this. 4289 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 4290 break; 4291 4292 // Look at the (necessarily single) use of the flag value. If it has a 4293 // chain, this transformation is more complex. Note that multiple things 4294 // could use the value result, which we should ignore. 4295 SDNode *FlagUser = 0; 4296 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 4297 FlagUser == 0; ++UI) { 4298 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 4299 SDNode *User = *UI; 4300 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 4301 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 4302 FlagUser = User; 4303 break; 4304 } 4305 } 4306 } 4307 4308 // If the user is a MFCR instruction, we know this is safe. Otherwise we 4309 // give up for right now. 4310 if (FlagUser->getOpcode() == PPCISD::MFCR) 4311 return SDValue(VCMPoNode, 0); 4312 } 4313 break; 4314 } 4315 case ISD::BR_CC: { 4316 // If this is a branch on an altivec predicate comparison, lower this so 4317 // that we don't have to do a MFCR: instead, branch directly on CR6. This 4318 // lowering is done pre-legalize, because the legalizer lowers the predicate 4319 // compare down to code that is difficult to reassemble. 4320 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 4321 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 4322 int CompareOpc; 4323 bool isDot; 4324 4325 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 4326 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 4327 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 4328 assert(isDot && "Can't compare against a vector result!"); 4329 4330 // If this is a comparison against something other than 0/1, then we know 4331 // that the condition is never/always true. 4332 unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); 4333 if (Val != 0 && Val != 1) { 4334 if (CC == ISD::SETEQ) // Cond never true, remove branch. 4335 return N->getOperand(0); 4336 // Always !=, turn it into an unconditional branch. 4337 return DAG.getNode(ISD::BR, MVT::Other, 4338 N->getOperand(0), N->getOperand(4)); 4339 } 4340 4341 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 4342 4343 // Create the PPCISD altivec 'dot' comparison node. 4344 std::vector<MVT> VTs; 4345 SDValue Ops[] = { 4346 LHS.getOperand(2), // LHS of compare 4347 LHS.getOperand(3), // RHS of compare 4348 DAG.getConstant(CompareOpc, MVT::i32) 4349 }; 4350 VTs.push_back(LHS.getOperand(2).getValueType()); 4351 VTs.push_back(MVT::Flag); 4352 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 4353 4354 // Unpack the result based on how the target uses it. 4355 PPC::Predicate CompOpc; 4356 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { 4357 default: // Can't happen, don't crash on invalid number though. 4358 case 0: // Branch on the value of the EQ bit of CR6. 4359 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 4360 break; 4361 case 1: // Branch on the inverted value of the EQ bit of CR6. 4362 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 4363 break; 4364 case 2: // Branch on the value of the LT bit of CR6. 4365 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 4366 break; 4367 case 3: // Branch on the inverted value of the LT bit of CR6. 4368 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 4369 break; 4370 } 4371 4372 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 4373 DAG.getConstant(CompOpc, MVT::i32), 4374 DAG.getRegister(PPC::CR6, MVT::i32), 4375 N->getOperand(4), CompNode.getValue(1)); 4376 } 4377 break; 4378 } 4379 } 4380 4381 return SDValue(); 4382} 4383 4384//===----------------------------------------------------------------------===// 4385// Inline Assembly Support 4386//===----------------------------------------------------------------------===// 4387 4388void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 4389 const APInt &Mask, 4390 APInt &KnownZero, 4391 APInt &KnownOne, 4392 const SelectionDAG &DAG, 4393 unsigned Depth) const { 4394 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 4395 switch (Op.getOpcode()) { 4396 default: break; 4397 case PPCISD::LBRX: { 4398 // lhbrx is known to have the top bits cleared out. 4399 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 4400 KnownZero = 0xFFFF0000; 4401 break; 4402 } 4403 case ISD::INTRINSIC_WO_CHAIN: { 4404 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 4405 default: break; 4406 case Intrinsic::ppc_altivec_vcmpbfp_p: 4407 case Intrinsic::ppc_altivec_vcmpeqfp_p: 4408 case Intrinsic::ppc_altivec_vcmpequb_p: 4409 case Intrinsic::ppc_altivec_vcmpequh_p: 4410 case Intrinsic::ppc_altivec_vcmpequw_p: 4411 case Intrinsic::ppc_altivec_vcmpgefp_p: 4412 case Intrinsic::ppc_altivec_vcmpgtfp_p: 4413 case Intrinsic::ppc_altivec_vcmpgtsb_p: 4414 case Intrinsic::ppc_altivec_vcmpgtsh_p: 4415 case Intrinsic::ppc_altivec_vcmpgtsw_p: 4416 case Intrinsic::ppc_altivec_vcmpgtub_p: 4417 case Intrinsic::ppc_altivec_vcmpgtuh_p: 4418 case Intrinsic::ppc_altivec_vcmpgtuw_p: 4419 KnownZero = ~1U; // All bits but the low one are known to be zero. 4420 break; 4421 } 4422 } 4423 } 4424} 4425 4426 4427/// getConstraintType - Given a constraint, return the type of 4428/// constraint it is for this target. 4429PPCTargetLowering::ConstraintType 4430PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 4431 if (Constraint.size() == 1) { 4432 switch (Constraint[0]) { 4433 default: break; 4434 case 'b': 4435 case 'r': 4436 case 'f': 4437 case 'v': 4438 case 'y': 4439 return C_RegisterClass; 4440 } 4441 } 4442 return TargetLowering::getConstraintType(Constraint); 4443} 4444 4445std::pair<unsigned, const TargetRegisterClass*> 4446PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 4447 MVT VT) const { 4448 if (Constraint.size() == 1) { 4449 // GCC RS6000 Constraint Letters 4450 switch (Constraint[0]) { 4451 case 'b': // R1-R31 4452 case 'r': // R0-R31 4453 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 4454 return std::make_pair(0U, PPC::G8RCRegisterClass); 4455 return std::make_pair(0U, PPC::GPRCRegisterClass); 4456 case 'f': 4457 if (VT == MVT::f32) 4458 return std::make_pair(0U, PPC::F4RCRegisterClass); 4459 else if (VT == MVT::f64) 4460 return std::make_pair(0U, PPC::F8RCRegisterClass); 4461 break; 4462 case 'v': 4463 return std::make_pair(0U, PPC::VRRCRegisterClass); 4464 case 'y': // crrc 4465 return std::make_pair(0U, PPC::CRRCRegisterClass); 4466 } 4467 } 4468 4469 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 4470} 4471 4472 4473/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 4474/// vector. If it is invalid, don't add anything to Ops. 4475void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter, 4476 std::vector<SDValue>&Ops, 4477 SelectionDAG &DAG) const { 4478 SDValue Result(0,0); 4479 switch (Letter) { 4480 default: break; 4481 case 'I': 4482 case 'J': 4483 case 'K': 4484 case 'L': 4485 case 'M': 4486 case 'N': 4487 case 'O': 4488 case 'P': { 4489 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 4490 if (!CST) return; // Must be an immediate to match. 4491 unsigned Value = CST->getValue(); 4492 switch (Letter) { 4493 default: assert(0 && "Unknown constraint letter!"); 4494 case 'I': // "I" is a signed 16-bit constant. 4495 if ((short)Value == (int)Value) 4496 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4497 break; 4498 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 4499 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 4500 if ((short)Value == 0) 4501 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4502 break; 4503 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 4504 if ((Value >> 16) == 0) 4505 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4506 break; 4507 case 'M': // "M" is a constant that is greater than 31. 4508 if (Value > 31) 4509 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4510 break; 4511 case 'N': // "N" is a positive constant that is an exact power of two. 4512 if ((int)Value > 0 && isPowerOf2_32(Value)) 4513 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4514 break; 4515 case 'O': // "O" is the constant zero. 4516 if (Value == 0) 4517 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4518 break; 4519 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 4520 if ((short)-Value == (int)-Value) 4521 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4522 break; 4523 } 4524 break; 4525 } 4526 } 4527 4528 if (Result.Val) { 4529 Ops.push_back(Result); 4530 return; 4531 } 4532 4533 // Handle standard constraint letters. 4534 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG); 4535} 4536 4537// isLegalAddressingMode - Return true if the addressing mode represented 4538// by AM is legal for this target, for a load/store of the specified type. 4539bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 4540 const Type *Ty) const { 4541 // FIXME: PPC does not allow r+i addressing modes for vectors! 4542 4543 // PPC allows a sign-extended 16-bit immediate field. 4544 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 4545 return false; 4546 4547 // No global is ever allowed as a base. 4548 if (AM.BaseGV) 4549 return false; 4550 4551 // PPC only support r+r, 4552 switch (AM.Scale) { 4553 case 0: // "r+i" or just "i", depending on HasBaseReg. 4554 break; 4555 case 1: 4556 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 4557 return false; 4558 // Otherwise we have r+r or r+i. 4559 break; 4560 case 2: 4561 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 4562 return false; 4563 // Allow 2*r as r+r. 4564 break; 4565 default: 4566 // No other scales are supported. 4567 return false; 4568 } 4569 4570 return true; 4571} 4572 4573/// isLegalAddressImmediate - Return true if the integer value can be used 4574/// as the offset of the target addressing mode for load / store of the 4575/// given type. 4576bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 4577 // PPC allows a sign-extended 16-bit immediate field. 4578 return (V > -(1 << 16) && V < (1 << 16)-1); 4579} 4580 4581bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 4582 return false; 4583} 4584 4585SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 4586 // Depths > 0 not supported yet! 4587 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 4588 return SDValue(); 4589 4590 MachineFunction &MF = DAG.getMachineFunction(); 4591 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 4592 4593 // Just load the return address off the stack. 4594 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 4595 4596 // Make sure the function really does not optimize away the store of the RA 4597 // to the stack. 4598 FuncInfo->setLRStoreRequired(); 4599 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); 4600} 4601 4602SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 4603 // Depths > 0 not supported yet! 4604 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 4605 return SDValue(); 4606 4607 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4608 bool isPPC64 = PtrVT == MVT::i64; 4609 4610 MachineFunction &MF = DAG.getMachineFunction(); 4611 MachineFrameInfo *MFI = MF.getFrameInfo(); 4612 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) 4613 && MFI->getStackSize(); 4614 4615 if (isPPC64) 4616 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1, 4617 MVT::i64); 4618 else 4619 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1, 4620 MVT::i32); 4621} 4622