PPCISelLowering.cpp revision 2fe4bf453b433cfe7113e282a59bf0f1e7fb0195
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCTargetMachine.h" 16#include "PPCPerfectShuffle.h" 17#include "llvm/ADT/VectorExtras.h" 18#include "llvm/Analysis/ScalarEvolutionExpressions.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Constants.h" 25#include "llvm/Function.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/Support/MathExtras.h" 28#include "llvm/Target/TargetOptions.h" 29#include "llvm/Support/CommandLine.h" 30using namespace llvm; 31 32static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc"); 33 34PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 35 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { 36 37 // Fold away setcc operations if possible. 38 setSetCCIsExpensive(); 39 setPow2DivIsCheap(); 40 41 // Use _setjmp/_longjmp instead of setjmp/longjmp. 42 setUseUnderscoreSetJmpLongJmp(true); 43 44 // Set up the register classes. 45 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 46 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 47 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 48 49 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 50 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); 51 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); 52 53 // PowerPC does not have truncstore for i1. 54 setStoreXAction(MVT::i1, Promote); 55 56 // PowerPC has pre-inc load and store's. 57 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 58 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 59 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 60 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 61 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 62 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 63 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 64 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 65 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 66 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 67 68 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 69 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 70 71 // PowerPC has no intrinsics for these particular operations 72 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 73 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 74 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 75 76 // PowerPC has no SREM/UREM instructions 77 setOperationAction(ISD::SREM, MVT::i32, Expand); 78 setOperationAction(ISD::UREM, MVT::i32, Expand); 79 setOperationAction(ISD::SREM, MVT::i64, Expand); 80 setOperationAction(ISD::UREM, MVT::i64, Expand); 81 82 // We don't support sin/cos/sqrt/fmod 83 setOperationAction(ISD::FSIN , MVT::f64, Expand); 84 setOperationAction(ISD::FCOS , MVT::f64, Expand); 85 setOperationAction(ISD::FREM , MVT::f64, Expand); 86 setOperationAction(ISD::FSIN , MVT::f32, Expand); 87 setOperationAction(ISD::FCOS , MVT::f32, Expand); 88 setOperationAction(ISD::FREM , MVT::f32, Expand); 89 90 // If we're enabling GP optimizations, use hardware square root 91 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 92 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 93 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 94 } 95 96 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 97 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 98 99 // PowerPC does not have BSWAP, CTPOP or CTTZ 100 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 101 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 102 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 103 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 104 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 105 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 106 107 // PowerPC does not have ROTR 108 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 109 110 // PowerPC does not have Select 111 setOperationAction(ISD::SELECT, MVT::i32, Expand); 112 setOperationAction(ISD::SELECT, MVT::i64, Expand); 113 setOperationAction(ISD::SELECT, MVT::f32, Expand); 114 setOperationAction(ISD::SELECT, MVT::f64, Expand); 115 116 // PowerPC wants to turn select_cc of FP into fsel when possible. 117 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 118 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 119 120 // PowerPC wants to optimize integer setcc a bit 121 setOperationAction(ISD::SETCC, MVT::i32, Custom); 122 123 // PowerPC does not have BRCOND which requires SetCC 124 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 125 126 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 127 128 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 129 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 130 131 // PowerPC does not have [U|S]INT_TO_FP 132 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 133 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 134 135 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 136 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 137 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 138 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 139 140 // We cannot sextinreg(i1). Expand to shifts. 141 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 142 143 144 // Support label based line numbers. 145 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 146 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 147 // FIXME - use subtarget debug flags 148 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) 149 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 150 151 // We want to legalize GlobalAddress and ConstantPool nodes into the 152 // appropriate instructions to materialize the address. 153 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 154 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 155 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 156 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 157 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 158 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 159 160 // RET must be custom lowered, to meet ABI requirements 161 setOperationAction(ISD::RET , MVT::Other, Custom); 162 163 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 164 setOperationAction(ISD::VASTART , MVT::Other, Custom); 165 166 // Use the default implementation. 167 setOperationAction(ISD::VAARG , MVT::Other, Expand); 168 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 169 setOperationAction(ISD::VAEND , MVT::Other, Expand); 170 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 171 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 172 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 173 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand); 174 175 // We want to custom lower some of our intrinsics. 176 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 177 178 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 179 // They also have instructions for converting between i64 and fp. 180 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 181 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 182 183 // FIXME: disable this lowered code. This generates 64-bit register values, 184 // and we don't model the fact that the top part is clobbered by calls. We 185 // need to flag these together so that the value isn't live across a call. 186 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 187 188 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 189 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 190 } else { 191 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 192 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 193 } 194 195 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 196 // 64 bit PowerPC implementations can support i64 types directly 197 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 198 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 199 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 200 } else { 201 // 32 bit PowerPC wants to expand i64 shifts itself. 202 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 203 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 204 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 205 } 206 207 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 208 // First set operation action for all vector types to expand. Then we 209 // will selectively turn on ones that can be effectively codegen'd. 210 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 211 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 212 // add/sub are legal for all supported vector VT's. 213 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); 214 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); 215 216 // We promote all shuffles to v16i8. 217 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); 218 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); 219 220 // We promote all non-typed operations to v4i32. 221 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); 222 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); 223 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); 224 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); 225 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); 226 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); 227 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); 228 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); 229 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 230 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); 231 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); 232 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); 233 234 // No other operations are legal. 235 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 236 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 237 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 238 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 239 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 240 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 241 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 242 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 243 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 244 245 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); 246 } 247 248 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 249 // with merges, splats, etc. 250 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 251 252 setOperationAction(ISD::AND , MVT::v4i32, Legal); 253 setOperationAction(ISD::OR , MVT::v4i32, Legal); 254 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 255 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 256 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 257 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 258 259 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 260 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 261 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 262 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 263 264 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 265 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 266 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 267 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 268 269 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 270 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 271 272 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 273 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 274 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 275 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 276 } 277 278 setSetCCResultType(MVT::i32); 279 setShiftAmountType(MVT::i32); 280 setSetCCResultContents(ZeroOrOneSetCCResult); 281 282 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) 283 setStackPointerRegisterToSaveRestore(PPC::X1); 284 else 285 setStackPointerRegisterToSaveRestore(PPC::R1); 286 287 // We have target-specific dag combine patterns for the following nodes: 288 setTargetDAGCombine(ISD::SINT_TO_FP); 289 setTargetDAGCombine(ISD::STORE); 290 setTargetDAGCombine(ISD::BR_CC); 291 setTargetDAGCombine(ISD::BSWAP); 292 293 computeRegisterProperties(); 294} 295 296const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 297 switch (Opcode) { 298 default: return 0; 299 case PPCISD::FSEL: return "PPCISD::FSEL"; 300 case PPCISD::FCFID: return "PPCISD::FCFID"; 301 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 302 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 303 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 304 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 305 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 306 case PPCISD::VPERM: return "PPCISD::VPERM"; 307 case PPCISD::Hi: return "PPCISD::Hi"; 308 case PPCISD::Lo: return "PPCISD::Lo"; 309 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 310 case PPCISD::SRL: return "PPCISD::SRL"; 311 case PPCISD::SRA: return "PPCISD::SRA"; 312 case PPCISD::SHL: return "PPCISD::SHL"; 313 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 314 case PPCISD::STD_32: return "PPCISD::STD_32"; 315 case PPCISD::CALL: return "PPCISD::CALL"; 316 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 317 case PPCISD::BCTRL: return "PPCISD::BCTRL"; 318 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 319 case PPCISD::MFCR: return "PPCISD::MFCR"; 320 case PPCISD::VCMP: return "PPCISD::VCMP"; 321 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 322 case PPCISD::LBRX: return "PPCISD::LBRX"; 323 case PPCISD::STBRX: return "PPCISD::STBRX"; 324 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 325 } 326} 327 328//===----------------------------------------------------------------------===// 329// Node matching predicates, for use by the tblgen matching code. 330//===----------------------------------------------------------------------===// 331 332/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 333static bool isFloatingPointZero(SDOperand Op) { 334 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 335 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 336 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 337 // Maybe this has already been legalized into the constant pool? 338 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 339 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 340 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 341 } 342 return false; 343} 344 345/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 346/// true if Op is undef or if it matches the specified value. 347static bool isConstantOrUndef(SDOperand Op, unsigned Val) { 348 return Op.getOpcode() == ISD::UNDEF || 349 cast<ConstantSDNode>(Op)->getValue() == Val; 350} 351 352/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 353/// VPKUHUM instruction. 354bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 355 if (!isUnary) { 356 for (unsigned i = 0; i != 16; ++i) 357 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 358 return false; 359 } else { 360 for (unsigned i = 0; i != 8; ++i) 361 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 362 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 363 return false; 364 } 365 return true; 366} 367 368/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 369/// VPKUWUM instruction. 370bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 371 if (!isUnary) { 372 for (unsigned i = 0; i != 16; i += 2) 373 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 374 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 375 return false; 376 } else { 377 for (unsigned i = 0; i != 8; i += 2) 378 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 379 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 380 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 381 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 382 return false; 383 } 384 return true; 385} 386 387/// isVMerge - Common function, used to match vmrg* shuffles. 388/// 389static bool isVMerge(SDNode *N, unsigned UnitSize, 390 unsigned LHSStart, unsigned RHSStart) { 391 assert(N->getOpcode() == ISD::BUILD_VECTOR && 392 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 393 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 394 "Unsupported merge size!"); 395 396 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 397 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 398 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 399 LHSStart+j+i*UnitSize) || 400 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 401 RHSStart+j+i*UnitSize)) 402 return false; 403 } 404 return true; 405} 406 407/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 408/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 409bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 410 if (!isUnary) 411 return isVMerge(N, UnitSize, 8, 24); 412 return isVMerge(N, UnitSize, 8, 8); 413} 414 415/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 416/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 417bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 418 if (!isUnary) 419 return isVMerge(N, UnitSize, 0, 16); 420 return isVMerge(N, UnitSize, 0, 0); 421} 422 423 424/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 425/// amount, otherwise return -1. 426int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 427 assert(N->getOpcode() == ISD::BUILD_VECTOR && 428 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 429 // Find the first non-undef value in the shuffle mask. 430 unsigned i; 431 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 432 /*search*/; 433 434 if (i == 16) return -1; // all undef. 435 436 // Otherwise, check to see if the rest of the elements are consequtively 437 // numbered from this value. 438 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 439 if (ShiftAmt < i) return -1; 440 ShiftAmt -= i; 441 442 if (!isUnary) { 443 // Check the rest of the elements to see if they are consequtive. 444 for (++i; i != 16; ++i) 445 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 446 return -1; 447 } else { 448 // Check the rest of the elements to see if they are consequtive. 449 for (++i; i != 16; ++i) 450 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 451 return -1; 452 } 453 454 return ShiftAmt; 455} 456 457/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 458/// specifies a splat of a single element that is suitable for input to 459/// VSPLTB/VSPLTH/VSPLTW. 460bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 461 assert(N->getOpcode() == ISD::BUILD_VECTOR && 462 N->getNumOperands() == 16 && 463 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 464 465 // This is a splat operation if each element of the permute is the same, and 466 // if the value doesn't reference the second vector. 467 unsigned ElementBase = 0; 468 SDOperand Elt = N->getOperand(0); 469 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 470 ElementBase = EltV->getValue(); 471 else 472 return false; // FIXME: Handle UNDEF elements too! 473 474 if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 475 return false; 476 477 // Check that they are consequtive. 478 for (unsigned i = 1; i != EltSize; ++i) { 479 if (!isa<ConstantSDNode>(N->getOperand(i)) || 480 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 481 return false; 482 } 483 484 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 485 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 486 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 487 assert(isa<ConstantSDNode>(N->getOperand(i)) && 488 "Invalid VECTOR_SHUFFLE mask!"); 489 for (unsigned j = 0; j != EltSize; ++j) 490 if (N->getOperand(i+j) != N->getOperand(j)) 491 return false; 492 } 493 494 return true; 495} 496 497/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 498/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 499unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 500 assert(isSplatShuffleMask(N, EltSize)); 501 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 502} 503 504/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 505/// by using a vspltis[bhw] instruction of the specified element size, return 506/// the constant being splatted. The ByteSize field indicates the number of 507/// bytes of each element [124] -> [bhw]. 508SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 509 SDOperand OpVal(0, 0); 510 511 // If ByteSize of the splat is bigger than the element size of the 512 // build_vector, then we have a case where we are checking for a splat where 513 // multiple elements of the buildvector are folded together into a single 514 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 515 unsigned EltSize = 16/N->getNumOperands(); 516 if (EltSize < ByteSize) { 517 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 518 SDOperand UniquedVals[4]; 519 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 520 521 // See if all of the elements in the buildvector agree across. 522 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 523 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 524 // If the element isn't a constant, bail fully out. 525 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); 526 527 528 if (UniquedVals[i&(Multiple-1)].Val == 0) 529 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 530 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 531 return SDOperand(); // no match. 532 } 533 534 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 535 // either constant or undef values that are identical for each chunk. See 536 // if these chunks can form into a larger vspltis*. 537 538 // Check to see if all of the leading entries are either 0 or -1. If 539 // neither, then this won't fit into the immediate field. 540 bool LeadingZero = true; 541 bool LeadingOnes = true; 542 for (unsigned i = 0; i != Multiple-1; ++i) { 543 if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 544 545 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 546 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 547 } 548 // Finally, check the least significant entry. 549 if (LeadingZero) { 550 if (UniquedVals[Multiple-1].Val == 0) 551 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 552 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 553 if (Val < 16) 554 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 555 } 556 if (LeadingOnes) { 557 if (UniquedVals[Multiple-1].Val == 0) 558 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 559 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 560 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 561 return DAG.getTargetConstant(Val, MVT::i32); 562 } 563 564 return SDOperand(); 565 } 566 567 // Check to see if this buildvec has a single non-undef value in its elements. 568 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 569 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 570 if (OpVal.Val == 0) 571 OpVal = N->getOperand(i); 572 else if (OpVal != N->getOperand(i)) 573 return SDOperand(); 574 } 575 576 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. 577 578 unsigned ValSizeInBytes = 0; 579 uint64_t Value = 0; 580 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 581 Value = CN->getValue(); 582 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 583 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 584 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 585 Value = FloatToBits(CN->getValue()); 586 ValSizeInBytes = 4; 587 } 588 589 // If the splat value is larger than the element value, then we can never do 590 // this splat. The only case that we could fit the replicated bits into our 591 // immediate field for would be zero, and we prefer to use vxor for it. 592 if (ValSizeInBytes < ByteSize) return SDOperand(); 593 594 // If the element value is larger than the splat value, cut it in half and 595 // check to see if the two halves are equal. Continue doing this until we 596 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 597 while (ValSizeInBytes > ByteSize) { 598 ValSizeInBytes >>= 1; 599 600 // If the top half equals the bottom half, we're still ok. 601 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 602 (Value & ((1 << (8*ValSizeInBytes))-1))) 603 return SDOperand(); 604 } 605 606 // Properly sign extend the value. 607 int ShAmt = (4-ByteSize)*8; 608 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 609 610 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 611 if (MaskVal == 0) return SDOperand(); 612 613 // Finally, if this value fits in a 5 bit sext field, return it 614 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 615 return DAG.getTargetConstant(MaskVal, MVT::i32); 616 return SDOperand(); 617} 618 619//===----------------------------------------------------------------------===// 620// Addressing Mode Selection 621//===----------------------------------------------------------------------===// 622 623/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 624/// or 64-bit immediate, and if the value can be accurately represented as a 625/// sign extension from a 16-bit value. If so, this returns true and the 626/// immediate. 627static bool isIntS16Immediate(SDNode *N, short &Imm) { 628 if (N->getOpcode() != ISD::Constant) 629 return false; 630 631 Imm = (short)cast<ConstantSDNode>(N)->getValue(); 632 if (N->getValueType(0) == MVT::i32) 633 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); 634 else 635 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); 636} 637static bool isIntS16Immediate(SDOperand Op, short &Imm) { 638 return isIntS16Immediate(Op.Val, Imm); 639} 640 641 642/// SelectAddressRegReg - Given the specified addressed, check to see if it 643/// can be represented as an indexed [r+r] operation. Returns false if it 644/// can be more efficiently represented with [r+imm]. 645bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, 646 SDOperand &Index, 647 SelectionDAG &DAG) { 648 short imm = 0; 649 if (N.getOpcode() == ISD::ADD) { 650 if (isIntS16Immediate(N.getOperand(1), imm)) 651 return false; // r+i 652 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 653 return false; // r+i 654 655 Base = N.getOperand(0); 656 Index = N.getOperand(1); 657 return true; 658 } else if (N.getOpcode() == ISD::OR) { 659 if (isIntS16Immediate(N.getOperand(1), imm)) 660 return false; // r+i can fold it if we can. 661 662 // If this is an or of disjoint bitfields, we can codegen this as an add 663 // (for better address arithmetic) if the LHS and RHS of the OR are provably 664 // disjoint. 665 uint64_t LHSKnownZero, LHSKnownOne; 666 uint64_t RHSKnownZero, RHSKnownOne; 667 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 668 669 if (LHSKnownZero) { 670 ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne); 671 // If all of the bits are known zero on the LHS or RHS, the add won't 672 // carry. 673 if ((LHSKnownZero | RHSKnownZero) == ~0U) { 674 Base = N.getOperand(0); 675 Index = N.getOperand(1); 676 return true; 677 } 678 } 679 } 680 681 return false; 682} 683 684/// Returns true if the address N can be represented by a base register plus 685/// a signed 16-bit displacement [r+imm], and if it is not better 686/// represented as reg+reg. 687bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, 688 SDOperand &Base, SelectionDAG &DAG){ 689 // If this can be more profitably realized as r+r, fail. 690 if (SelectAddressRegReg(N, Disp, Base, DAG)) 691 return false; 692 693 if (N.getOpcode() == ISD::ADD) { 694 short imm = 0; 695 if (isIntS16Immediate(N.getOperand(1), imm)) { 696 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 697 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 698 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 699 } else { 700 Base = N.getOperand(0); 701 } 702 return true; // [r+i] 703 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 704 // Match LOAD (ADD (X, Lo(G))). 705 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 706 && "Cannot handle constant offsets yet!"); 707 Disp = N.getOperand(1).getOperand(0); // The global address. 708 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 709 Disp.getOpcode() == ISD::TargetConstantPool || 710 Disp.getOpcode() == ISD::TargetJumpTable); 711 Base = N.getOperand(0); 712 return true; // [&g+r] 713 } 714 } else if (N.getOpcode() == ISD::OR) { 715 short imm = 0; 716 if (isIntS16Immediate(N.getOperand(1), imm)) { 717 // If this is an or of disjoint bitfields, we can codegen this as an add 718 // (for better address arithmetic) if the LHS and RHS of the OR are 719 // provably disjoint. 720 uint64_t LHSKnownZero, LHSKnownOne; 721 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 722 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 723 // If all of the bits are known zero on the LHS or RHS, the add won't 724 // carry. 725 Base = N.getOperand(0); 726 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 727 return true; 728 } 729 } 730 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 731 // Loading from a constant address. 732 733 // If this address fits entirely in a 16-bit sext immediate field, codegen 734 // this as "d, 0" 735 short Imm; 736 if (isIntS16Immediate(CN, Imm)) { 737 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 738 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 739 return true; 740 } 741 742 // FIXME: Handle small sext constant offsets in PPC64 mode also! 743 if (CN->getValueType(0) == MVT::i32) { 744 int Addr = (int)CN->getValue(); 745 746 // Otherwise, break this down into an LIS + disp. 747 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 748 Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32); 749 return true; 750 } 751 } 752 753 Disp = DAG.getTargetConstant(0, getPointerTy()); 754 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 755 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 756 else 757 Base = N; 758 return true; // [r+0] 759} 760 761/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 762/// represented as an indexed [r+r] operation. 763bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, 764 SDOperand &Index, 765 SelectionDAG &DAG) { 766 // Check to see if we can easily represent this as an [r+r] address. This 767 // will fail if it thinks that the address is more profitably represented as 768 // reg+imm, e.g. where imm = 0. 769 if (SelectAddressRegReg(N, Base, Index, DAG)) 770 return true; 771 772 // If the operand is an addition, always emit this as [r+r], since this is 773 // better (for code size, and execution, as the memop does the add for free) 774 // than emitting an explicit add. 775 if (N.getOpcode() == ISD::ADD) { 776 Base = N.getOperand(0); 777 Index = N.getOperand(1); 778 return true; 779 } 780 781 // Otherwise, do it the hard way, using R0 as the base register. 782 Base = DAG.getRegister(PPC::R0, N.getValueType()); 783 Index = N; 784 return true; 785} 786 787/// SelectAddressRegImmShift - Returns true if the address N can be 788/// represented by a base register plus a signed 14-bit displacement 789/// [r+imm*4]. Suitable for use by STD and friends. 790bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, 791 SDOperand &Base, 792 SelectionDAG &DAG) { 793 // If this can be more profitably realized as r+r, fail. 794 if (SelectAddressRegReg(N, Disp, Base, DAG)) 795 return false; 796 797 if (N.getOpcode() == ISD::ADD) { 798 short imm = 0; 799 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 800 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 801 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 802 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 803 } else { 804 Base = N.getOperand(0); 805 } 806 return true; // [r+i] 807 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 808 // Match LOAD (ADD (X, Lo(G))). 809 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 810 && "Cannot handle constant offsets yet!"); 811 Disp = N.getOperand(1).getOperand(0); // The global address. 812 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 813 Disp.getOpcode() == ISD::TargetConstantPool || 814 Disp.getOpcode() == ISD::TargetJumpTable); 815 Base = N.getOperand(0); 816 return true; // [&g+r] 817 } 818 } else if (N.getOpcode() == ISD::OR) { 819 short imm = 0; 820 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 821 // If this is an or of disjoint bitfields, we can codegen this as an add 822 // (for better address arithmetic) if the LHS and RHS of the OR are 823 // provably disjoint. 824 uint64_t LHSKnownZero, LHSKnownOne; 825 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 826 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 827 // If all of the bits are known zero on the LHS or RHS, the add won't 828 // carry. 829 Base = N.getOperand(0); 830 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 831 return true; 832 } 833 } 834 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 835 // Loading from a constant address. 836 837 // If this address fits entirely in a 14-bit sext immediate field, codegen 838 // this as "d, 0" 839 short Imm; 840 if (isIntS16Immediate(CN, Imm)) { 841 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 842 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 843 return true; 844 } 845 846 // FIXME: Handle small sext constant offsets in PPC64 mode also! 847 if (CN->getValueType(0) == MVT::i32) { 848 int Addr = (int)CN->getValue(); 849 850 // Otherwise, break this down into an LIS + disp. 851 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 852 Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32); 853 return true; 854 } 855 } 856 857 Disp = DAG.getTargetConstant(0, getPointerTy()); 858 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 859 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 860 else 861 Base = N; 862 return true; // [r+0] 863} 864 865 866/// getPreIndexedAddressParts - returns true by value, base pointer and 867/// offset pointer and addressing mode by reference if the node's address 868/// can be legally represented as pre-indexed load / store address. 869bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 870 SDOperand &Offset, 871 ISD::MemIndexedMode &AM, 872 SelectionDAG &DAG) { 873 // Disabled by default for now. 874 if (!EnablePPCPreinc) return false; 875 876 SDOperand Ptr; 877 MVT::ValueType VT; 878 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 879 Ptr = LD->getBasePtr(); 880 VT = LD->getValueType(0); 881 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 882 ST = ST; 883 Ptr = ST->getBasePtr(); 884 VT = ST->getStoredVT(); 885 return false; // TODO: Stores. 886 } else 887 return false; 888 889 // PowerPC doesn't have preinc load/store instructions for vectors. 890 if (MVT::isVector(VT)) 891 return false; 892 893 // TODO: Handle reg+reg. 894 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 895 return false; 896 897 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 898 // sext i32 to i64 when addr mode is r+i. 899 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 900 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 && 901 LD->getExtensionType() == ISD::SEXTLOAD && 902 isa<ConstantSDNode>(Offset)) 903 return false; 904 } 905 906 AM = ISD::PRE_INC; 907 return true; 908} 909 910//===----------------------------------------------------------------------===// 911// LowerOperation implementation 912//===----------------------------------------------------------------------===// 913 914static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 915 MVT::ValueType PtrVT = Op.getValueType(); 916 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 917 Constant *C = CP->getConstVal(); 918 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 919 SDOperand Zero = DAG.getConstant(0, PtrVT); 920 921 const TargetMachine &TM = DAG.getTarget(); 922 923 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 924 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 925 926 // If this is a non-darwin platform, we don't support non-static relo models 927 // yet. 928 if (TM.getRelocationModel() == Reloc::Static || 929 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 930 // Generate non-pic code that has direct accesses to the constant pool. 931 // The address of the global is just (hi(&g)+lo(&g)). 932 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 933 } 934 935 if (TM.getRelocationModel() == Reloc::PIC_) { 936 // With PIC, the first instruction is actually "GR+hi(&G)". 937 Hi = DAG.getNode(ISD::ADD, PtrVT, 938 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 939 } 940 941 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 942 return Lo; 943} 944 945static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 946 MVT::ValueType PtrVT = Op.getValueType(); 947 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 948 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 949 SDOperand Zero = DAG.getConstant(0, PtrVT); 950 951 const TargetMachine &TM = DAG.getTarget(); 952 953 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 954 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 955 956 // If this is a non-darwin platform, we don't support non-static relo models 957 // yet. 958 if (TM.getRelocationModel() == Reloc::Static || 959 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 960 // Generate non-pic code that has direct accesses to the constant pool. 961 // The address of the global is just (hi(&g)+lo(&g)). 962 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 963 } 964 965 if (TM.getRelocationModel() == Reloc::PIC_) { 966 // With PIC, the first instruction is actually "GR+hi(&G)". 967 Hi = DAG.getNode(ISD::ADD, PtrVT, 968 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 969 } 970 971 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 972 return Lo; 973} 974 975static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 976 MVT::ValueType PtrVT = Op.getValueType(); 977 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 978 GlobalValue *GV = GSDN->getGlobal(); 979 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 980 SDOperand Zero = DAG.getConstant(0, PtrVT); 981 982 const TargetMachine &TM = DAG.getTarget(); 983 984 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); 985 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); 986 987 // If this is a non-darwin platform, we don't support non-static relo models 988 // yet. 989 if (TM.getRelocationModel() == Reloc::Static || 990 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 991 // Generate non-pic code that has direct accesses to globals. 992 // The address of the global is just (hi(&g)+lo(&g)). 993 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 994 } 995 996 if (TM.getRelocationModel() == Reloc::PIC_) { 997 // With PIC, the first instruction is actually "GR+hi(&G)". 998 Hi = DAG.getNode(ISD::ADD, PtrVT, 999 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1000 } 1001 1002 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1003 1004 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() && 1005 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode())) 1006 return Lo; 1007 1008 // If the global is weak or external, we have to go through the lazy 1009 // resolution stub. 1010 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); 1011} 1012 1013static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { 1014 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1015 1016 // If we're comparing for equality to zero, expose the fact that this is 1017 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1018 // fold the new nodes. 1019 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1020 if (C->isNullValue() && CC == ISD::SETEQ) { 1021 MVT::ValueType VT = Op.getOperand(0).getValueType(); 1022 SDOperand Zext = Op.getOperand(0); 1023 if (VT < MVT::i32) { 1024 VT = MVT::i32; 1025 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 1026 } 1027 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 1028 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 1029 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 1030 DAG.getConstant(Log2b, MVT::i32)); 1031 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 1032 } 1033 // Leave comparisons against 0 and -1 alone for now, since they're usually 1034 // optimized. FIXME: revisit this when we can custom lower all setcc 1035 // optimizations. 1036 if (C->isAllOnesValue() || C->isNullValue()) 1037 return SDOperand(); 1038 } 1039 1040 // If we have an integer seteq/setne, turn it into a compare against zero 1041 // by subtracting the rhs from the lhs, which is faster than setting a 1042 // condition register, reading it back out, and masking the correct bit. 1043 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 1044 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1045 MVT::ValueType VT = Op.getValueType(); 1046 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0), 1047 Op.getOperand(1)); 1048 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 1049 } 1050 return SDOperand(); 1051} 1052 1053static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 1054 unsigned VarArgsFrameIndex) { 1055 // vastart just stores the address of the VarArgsFrameIndex slot into the 1056 // memory location argument. 1057 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1058 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1059 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 1060 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 1061 SV->getOffset()); 1062} 1063 1064static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, 1065 int &VarArgsFrameIndex) { 1066 // TODO: add description of PPC stack frame format, or at least some docs. 1067 // 1068 MachineFunction &MF = DAG.getMachineFunction(); 1069 MachineFrameInfo *MFI = MF.getFrameInfo(); 1070 SSARegMap *RegMap = MF.getSSARegMap(); 1071 SmallVector<SDOperand, 8> ArgValues; 1072 SDOperand Root = Op.getOperand(0); 1073 1074 unsigned ArgOffset = 24; 1075 const unsigned Num_GPR_Regs = 8; 1076 const unsigned Num_FPR_Regs = 13; 1077 const unsigned Num_VR_Regs = 12; 1078 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1079 1080 static const unsigned GPR_32[] = { // 32-bit registers. 1081 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1082 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1083 }; 1084 static const unsigned GPR_64[] = { // 64-bit registers. 1085 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1086 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1087 }; 1088 static const unsigned FPR[] = { 1089 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1090 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1091 }; 1092 static const unsigned VR[] = { 1093 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1094 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1095 }; 1096 1097 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1098 bool isPPC64 = PtrVT == MVT::i64; 1099 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1100 1101 // Add DAG nodes to load the arguments or copy them out of registers. On 1102 // entry to a function on PPC, the arguments start at offset 24, although the 1103 // first ones are often in registers. 1104 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { 1105 SDOperand ArgVal; 1106 bool needsLoad = false; 1107 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 1108 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; 1109 1110 unsigned CurArgOffset = ArgOffset; 1111 switch (ObjectVT) { 1112 default: assert(0 && "Unhandled argument type!"); 1113 case MVT::i32: 1114 // All int arguments reserve stack space. 1115 ArgOffset += isPPC64 ? 8 : 4; 1116 1117 if (GPR_idx != Num_GPR_Regs) { 1118 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1119 MF.addLiveIn(GPR[GPR_idx], VReg); 1120 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1121 ++GPR_idx; 1122 } else { 1123 needsLoad = true; 1124 } 1125 break; 1126 case MVT::i64: // PPC64 1127 // All int arguments reserve stack space. 1128 ArgOffset += 8; 1129 1130 if (GPR_idx != Num_GPR_Regs) { 1131 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 1132 MF.addLiveIn(GPR[GPR_idx], VReg); 1133 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1134 ++GPR_idx; 1135 } else { 1136 needsLoad = true; 1137 } 1138 break; 1139 case MVT::f32: 1140 case MVT::f64: 1141 // All FP arguments reserve stack space. 1142 ArgOffset += ObjSize; 1143 1144 // Every 4 bytes of argument space consumes one of the GPRs available for 1145 // argument passing. 1146 if (GPR_idx != Num_GPR_Regs) { 1147 ++GPR_idx; 1148 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs) 1149 ++GPR_idx; 1150 } 1151 if (FPR_idx != Num_FPR_Regs) { 1152 unsigned VReg; 1153 if (ObjectVT == MVT::f32) 1154 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 1155 else 1156 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 1157 MF.addLiveIn(FPR[FPR_idx], VReg); 1158 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1159 ++FPR_idx; 1160 } else { 1161 needsLoad = true; 1162 } 1163 break; 1164 case MVT::v4f32: 1165 case MVT::v4i32: 1166 case MVT::v8i16: 1167 case MVT::v16i8: 1168 // Note that vector arguments in registers don't reserve stack space. 1169 if (VR_idx != Num_VR_Regs) { 1170 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass); 1171 MF.addLiveIn(VR[VR_idx], VReg); 1172 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1173 ++VR_idx; 1174 } else { 1175 // This should be simple, but requires getting 16-byte aligned stack 1176 // values. 1177 assert(0 && "Loading VR argument not implemented yet!"); 1178 needsLoad = true; 1179 } 1180 break; 1181 } 1182 1183 // We need to load the argument to a virtual register if we determined above 1184 // that we ran out of physical registers of the appropriate type 1185 if (needsLoad) { 1186 // If the argument is actually used, emit a load from the right stack 1187 // slot. 1188 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 1189 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset); 1190 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); 1191 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 1192 } else { 1193 // Don't emit a dead load. 1194 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); 1195 } 1196 } 1197 1198 ArgValues.push_back(ArgVal); 1199 } 1200 1201 // If the function takes variable number of arguments, make a frame index for 1202 // the start of the first vararg value... for expansion of llvm.va_start. 1203 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1204 if (isVarArg) { 1205 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1206 ArgOffset); 1207 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1208 // If this function is vararg, store any remaining integer argument regs 1209 // to their spots on the stack so that they may be loaded by deferencing the 1210 // result of va_next. 1211 SmallVector<SDOperand, 8> MemOps; 1212 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 1213 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1214 MF.addLiveIn(GPR[GPR_idx], VReg); 1215 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1216 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1217 MemOps.push_back(Store); 1218 // Increment the address by four for the next argument to store 1219 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1220 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1221 } 1222 if (!MemOps.empty()) 1223 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 1224 } 1225 1226 ArgValues.push_back(Root); 1227 1228 // Return the new list of results. 1229 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1230 Op.Val->value_end()); 1231 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1232} 1233 1234/// isCallCompatibleAddress - Return the immediate to use if the specified 1235/// 32-bit value is representable in the immediate field of a BxA instruction. 1236static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { 1237 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1238 if (!C) return 0; 1239 1240 int Addr = C->getValue(); 1241 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 1242 (Addr << 6 >> 6) != Addr) 1243 return 0; // Top 6 bits have to be sext of immediate. 1244 1245 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val; 1246} 1247 1248 1249static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { 1250 SDOperand Chain = Op.getOperand(0); 1251 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1252 SDOperand Callee = Op.getOperand(4); 1253 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1254 1255 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1256 bool isPPC64 = PtrVT == MVT::i64; 1257 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1258 1259 1260 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 1261 // SelectExpr to use to put the arguments in the appropriate registers. 1262 std::vector<SDOperand> args_to_use; 1263 1264 // Count how many bytes are to be pushed on the stack, including the linkage 1265 // area, and parameter passing area. We start with 24/48 bytes, which is 1266 // prereserved space for [SP][CR][LR][3 x unused]. 1267 unsigned NumBytes = 6*PtrByteSize; 1268 1269 // Add up all the space actually used. 1270 for (unsigned i = 0; i != NumOps; ++i) 1271 NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; 1272 1273 // The prolog code of the callee may store up to 8 GPR argument registers to 1274 // the stack, allowing va_start to index over them in memory if its varargs. 1275 // Because we cannot tell if this is needed on the caller side, we have to 1276 // conservatively assume that it is needed. As such, make sure we have at 1277 // least enough stack space for the caller to store the 8 GPRs. 1278 if (NumBytes < 6*PtrByteSize+8*PtrByteSize) 1279 NumBytes = 6*PtrByteSize+8*PtrByteSize; 1280 1281 // Adjust the stack pointer for the new arguments... 1282 // These operations are automatically eliminated by the prolog/epilog pass 1283 Chain = DAG.getCALLSEQ_START(Chain, 1284 DAG.getConstant(NumBytes, PtrVT)); 1285 1286 // Set up a copy of the stack pointer for use loading and storing any 1287 // arguments that may not fit in the registers available for argument 1288 // passing. 1289 SDOperand StackPtr; 1290 if (isPPC64) 1291 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 1292 else 1293 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 1294 1295 // Figure out which arguments are going to go in registers, and which in 1296 // memory. Also, if this is a vararg function, floating point operations 1297 // must be stored to our stack, and loaded into integer regs as well, if 1298 // any integer regs are available for argument passing. 1299 unsigned ArgOffset = 6*PtrByteSize; 1300 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1301 static const unsigned GPR_32[] = { // 32-bit registers. 1302 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1303 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1304 }; 1305 static const unsigned GPR_64[] = { // 64-bit registers. 1306 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1307 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1308 }; 1309 static const unsigned FPR[] = { 1310 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1311 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1312 }; 1313 static const unsigned VR[] = { 1314 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1315 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1316 }; 1317 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]); 1318 const unsigned NumFPRs = sizeof(FPR)/sizeof(FPR[0]); 1319 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]); 1320 1321 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1322 1323 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1324 SmallVector<SDOperand, 8> MemOpChains; 1325 for (unsigned i = 0; i != NumOps; ++i) { 1326 SDOperand Arg = Op.getOperand(5+2*i); 1327 1328 // PtrOff will be used to store the current argument to the stack if a 1329 // register cannot be found for it. 1330 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 1331 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); 1332 1333 // On PPC64, promote integers to 64-bit values. 1334 if (isPPC64 && Arg.getValueType() == MVT::i32) { 1335 unsigned ExtOp = ISD::ZERO_EXTEND; 1336 if (cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue()) 1337 ExtOp = ISD::SIGN_EXTEND; 1338 Arg = DAG.getNode(ExtOp, MVT::i64, Arg); 1339 } 1340 1341 switch (Arg.getValueType()) { 1342 default: assert(0 && "Unexpected ValueType for argument!"); 1343 case MVT::i32: 1344 case MVT::i64: 1345 if (GPR_idx != NumGPRs) { 1346 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 1347 } else { 1348 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1349 } 1350 ArgOffset += PtrByteSize; 1351 break; 1352 case MVT::f32: 1353 case MVT::f64: 1354 if (FPR_idx != NumFPRs) { 1355 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 1356 1357 if (isVarArg) { 1358 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 1359 MemOpChains.push_back(Store); 1360 1361 // Float varargs are always shadowed in available integer registers 1362 if (GPR_idx != NumGPRs) { 1363 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1364 MemOpChains.push_back(Load.getValue(1)); 1365 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 1366 } 1367 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) { 1368 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 1369 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); 1370 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1371 MemOpChains.push_back(Load.getValue(1)); 1372 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 1373 } 1374 } else { 1375 // If we have any FPRs remaining, we may also have GPRs remaining. 1376 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1377 // GPRs. 1378 if (GPR_idx != NumGPRs) 1379 ++GPR_idx; 1380 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64) 1381 ++GPR_idx; 1382 } 1383 } else { 1384 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1385 } 1386 if (isPPC64) 1387 ArgOffset += 8; 1388 else 1389 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 1390 break; 1391 case MVT::v4f32: 1392 case MVT::v4i32: 1393 case MVT::v8i16: 1394 case MVT::v16i8: 1395 assert(!isVarArg && "Don't support passing vectors to varargs yet!"); 1396 assert(VR_idx != NumVRs && 1397 "Don't support passing more than 12 vector args yet!"); 1398 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 1399 break; 1400 } 1401 } 1402 if (!MemOpChains.empty()) 1403 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1404 &MemOpChains[0], MemOpChains.size()); 1405 1406 // Build a sequence of copy-to-reg nodes chained together with token chain 1407 // and flag operands which copy the outgoing args into the appropriate regs. 1408 SDOperand InFlag; 1409 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1410 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1411 InFlag); 1412 InFlag = Chain.getValue(1); 1413 } 1414 1415 std::vector<MVT::ValueType> NodeTys; 1416 NodeTys.push_back(MVT::Other); // Returns a chain 1417 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1418 1419 SmallVector<SDOperand, 8> Ops; 1420 unsigned CallOpc = PPCISD::CALL; 1421 1422 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1423 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1424 // node so that legalize doesn't hack it. 1425 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1426 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 1427 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1428 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 1429 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 1430 // If this is an absolute destination address, use the munged value. 1431 Callee = SDOperand(Dest, 0); 1432 else { 1433 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 1434 // to do the call, we can't use PPCISD::CALL. 1435 SDOperand MTCTROps[] = {Chain, Callee, InFlag}; 1436 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); 1437 InFlag = Chain.getValue(1); 1438 1439 // Copy the callee address into R12 on darwin. 1440 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag); 1441 InFlag = Chain.getValue(1); 1442 1443 NodeTys.clear(); 1444 NodeTys.push_back(MVT::Other); 1445 NodeTys.push_back(MVT::Flag); 1446 Ops.push_back(Chain); 1447 CallOpc = PPCISD::BCTRL; 1448 Callee.Val = 0; 1449 } 1450 1451 // If this is a direct call, pass the chain and the callee. 1452 if (Callee.Val) { 1453 Ops.push_back(Chain); 1454 Ops.push_back(Callee); 1455 } 1456 1457 // Add argument registers to the end of the list so that they are known live 1458 // into the call. 1459 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1460 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1461 RegsToPass[i].second.getValueType())); 1462 1463 if (InFlag.Val) 1464 Ops.push_back(InFlag); 1465 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 1466 InFlag = Chain.getValue(1); 1467 1468 SDOperand ResultVals[3]; 1469 unsigned NumResults = 0; 1470 NodeTys.clear(); 1471 1472 // If the call has results, copy the values out of the ret val registers. 1473 switch (Op.Val->getValueType(0)) { 1474 default: assert(0 && "Unexpected ret value!"); 1475 case MVT::Other: break; 1476 case MVT::i32: 1477 if (Op.Val->getValueType(1) == MVT::i32) { 1478 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1); 1479 ResultVals[0] = Chain.getValue(0); 1480 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, 1481 Chain.getValue(2)).getValue(1); 1482 ResultVals[1] = Chain.getValue(0); 1483 NumResults = 2; 1484 NodeTys.push_back(MVT::i32); 1485 } else { 1486 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1487 ResultVals[0] = Chain.getValue(0); 1488 NumResults = 1; 1489 } 1490 NodeTys.push_back(MVT::i32); 1491 break; 1492 case MVT::i64: 1493 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); 1494 ResultVals[0] = Chain.getValue(0); 1495 NumResults = 1; 1496 NodeTys.push_back(MVT::i64); 1497 break; 1498 case MVT::f32: 1499 case MVT::f64: 1500 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), 1501 InFlag).getValue(1); 1502 ResultVals[0] = Chain.getValue(0); 1503 NumResults = 1; 1504 NodeTys.push_back(Op.Val->getValueType(0)); 1505 break; 1506 case MVT::v4f32: 1507 case MVT::v4i32: 1508 case MVT::v8i16: 1509 case MVT::v16i8: 1510 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0), 1511 InFlag).getValue(1); 1512 ResultVals[0] = Chain.getValue(0); 1513 NumResults = 1; 1514 NodeTys.push_back(Op.Val->getValueType(0)); 1515 break; 1516 } 1517 1518 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 1519 DAG.getConstant(NumBytes, PtrVT)); 1520 NodeTys.push_back(MVT::Other); 1521 1522 // If the function returns void, just return the chain. 1523 if (NumResults == 0) 1524 return Chain; 1525 1526 // Otherwise, merge everything together with a MERGE_VALUES node. 1527 ResultVals[NumResults++] = Chain; 1528 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1529 ResultVals, NumResults); 1530 return Res.getValue(Op.ResNo); 1531} 1532 1533static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 1534 SDOperand Copy; 1535 switch(Op.getNumOperands()) { 1536 default: 1537 assert(0 && "Do not know how to return this many arguments!"); 1538 abort(); 1539 case 1: 1540 return SDOperand(); // ret void is legal 1541 case 3: { 1542 MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 1543 unsigned ArgReg; 1544 if (ArgVT == MVT::i32) { 1545 ArgReg = PPC::R3; 1546 } else if (ArgVT == MVT::i64) { 1547 ArgReg = PPC::X3; 1548 } else if (MVT::isVector(ArgVT)) { 1549 ArgReg = PPC::V2; 1550 } else { 1551 assert(MVT::isFloatingPoint(ArgVT)); 1552 ArgReg = PPC::F1; 1553 } 1554 1555 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 1556 SDOperand()); 1557 1558 // If we haven't noted the R3/F1 are live out, do so now. 1559 if (DAG.getMachineFunction().liveout_empty()) 1560 DAG.getMachineFunction().addLiveOut(ArgReg); 1561 break; 1562 } 1563 case 5: 1564 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3), 1565 SDOperand()); 1566 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); 1567 // If we haven't noted the R3+R4 are live out, do so now. 1568 if (DAG.getMachineFunction().liveout_empty()) { 1569 DAG.getMachineFunction().addLiveOut(PPC::R3); 1570 DAG.getMachineFunction().addLiveOut(PPC::R4); 1571 } 1572 break; 1573 } 1574 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 1575} 1576 1577/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 1578/// possible. 1579static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 1580 // Not FP? Not a fsel. 1581 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 1582 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 1583 return SDOperand(); 1584 1585 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1586 1587 // Cannot handle SETEQ/SETNE. 1588 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); 1589 1590 MVT::ValueType ResVT = Op.getValueType(); 1591 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 1592 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 1593 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 1594 1595 // If the RHS of the comparison is a 0.0, we don't need to do the 1596 // subtraction at all. 1597 if (isFloatingPointZero(RHS)) 1598 switch (CC) { 1599 default: break; // SETUO etc aren't handled by fsel. 1600 case ISD::SETULT: 1601 case ISD::SETOLT: 1602 case ISD::SETLT: 1603 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 1604 case ISD::SETUGE: 1605 case ISD::SETOGE: 1606 case ISD::SETGE: 1607 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 1608 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 1609 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 1610 case ISD::SETUGT: 1611 case ISD::SETOGT: 1612 case ISD::SETGT: 1613 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 1614 case ISD::SETULE: 1615 case ISD::SETOLE: 1616 case ISD::SETLE: 1617 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 1618 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 1619 return DAG.getNode(PPCISD::FSEL, ResVT, 1620 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 1621 } 1622 1623 SDOperand Cmp; 1624 switch (CC) { 1625 default: break; // SETUO etc aren't handled by fsel. 1626 case ISD::SETULT: 1627 case ISD::SETOLT: 1628 case ISD::SETLT: 1629 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 1630 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1631 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1632 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 1633 case ISD::SETUGE: 1634 case ISD::SETOGE: 1635 case ISD::SETGE: 1636 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 1637 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1638 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1639 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 1640 case ISD::SETUGT: 1641 case ISD::SETOGT: 1642 case ISD::SETGT: 1643 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 1644 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1645 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1646 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 1647 case ISD::SETULE: 1648 case ISD::SETOLE: 1649 case ISD::SETLE: 1650 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 1651 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1652 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1653 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 1654 } 1655 return SDOperand(); 1656} 1657 1658static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 1659 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 1660 SDOperand Src = Op.getOperand(0); 1661 if (Src.getValueType() == MVT::f32) 1662 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 1663 1664 SDOperand Tmp; 1665 switch (Op.getValueType()) { 1666 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 1667 case MVT::i32: 1668 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 1669 break; 1670 case MVT::i64: 1671 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 1672 break; 1673 } 1674 1675 // Convert the FP value to an int value through memory. 1676 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 1677 if (Op.getValueType() == MVT::i32) 1678 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 1679 return Bits; 1680} 1681 1682static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 1683 if (Op.getOperand(0).getValueType() == MVT::i64) { 1684 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 1685 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 1686 if (Op.getValueType() == MVT::f32) 1687 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 1688 return FP; 1689 } 1690 1691 assert(Op.getOperand(0).getValueType() == MVT::i32 && 1692 "Unhandled SINT_TO_FP type in custom expander!"); 1693 // Since we only generate this in 64-bit mode, we can take advantage of 1694 // 64-bit registers. In particular, sign extend the input value into the 1695 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 1696 // then lfd it and fcfid it. 1697 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 1698 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 1699 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1700 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 1701 1702 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 1703 Op.getOperand(0)); 1704 1705 // STD the extended value into the stack slot. 1706 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 1707 DAG.getEntryNode(), Ext64, FIdx, 1708 DAG.getSrcValue(NULL)); 1709 // Load the value as a double. 1710 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); 1711 1712 // FCFID it and return it. 1713 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 1714 if (Op.getValueType() == MVT::f32) 1715 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 1716 return FP; 1717} 1718 1719static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { 1720 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1721 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 1722 1723 // Expand into a bunch of logical ops. Note that these ops 1724 // depend on the PPC behavior for oversized shift amounts. 1725 SDOperand Lo = Op.getOperand(0); 1726 SDOperand Hi = Op.getOperand(1); 1727 SDOperand Amt = Op.getOperand(2); 1728 1729 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 1730 DAG.getConstant(32, MVT::i32), Amt); 1731 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 1732 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 1733 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 1734 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 1735 DAG.getConstant(-32U, MVT::i32)); 1736 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 1737 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 1738 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 1739 SDOperand OutOps[] = { OutLo, OutHi }; 1740 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 1741 OutOps, 2); 1742} 1743 1744static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { 1745 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1746 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!"); 1747 1748 // Otherwise, expand into a bunch of logical ops. Note that these ops 1749 // depend on the PPC behavior for oversized shift amounts. 1750 SDOperand Lo = Op.getOperand(0); 1751 SDOperand Hi = Op.getOperand(1); 1752 SDOperand Amt = Op.getOperand(2); 1753 1754 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 1755 DAG.getConstant(32, MVT::i32), Amt); 1756 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 1757 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 1758 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 1759 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 1760 DAG.getConstant(-32U, MVT::i32)); 1761 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 1762 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 1763 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 1764 SDOperand OutOps[] = { OutLo, OutHi }; 1765 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 1766 OutOps, 2); 1767} 1768 1769static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { 1770 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1771 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 1772 1773 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 1774 SDOperand Lo = Op.getOperand(0); 1775 SDOperand Hi = Op.getOperand(1); 1776 SDOperand Amt = Op.getOperand(2); 1777 1778 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 1779 DAG.getConstant(32, MVT::i32), Amt); 1780 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 1781 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 1782 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 1783 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 1784 DAG.getConstant(-32U, MVT::i32)); 1785 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 1786 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 1787 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 1788 Tmp4, Tmp6, ISD::SETLE); 1789 SDOperand OutOps[] = { OutLo, OutHi }; 1790 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 1791 OutOps, 2); 1792} 1793 1794//===----------------------------------------------------------------------===// 1795// Vector related lowering. 1796// 1797 1798// If this is a vector of constants or undefs, get the bits. A bit in 1799// UndefBits is set if the corresponding element of the vector is an 1800// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 1801// zero. Return true if this is not an array of constants, false if it is. 1802// 1803static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 1804 uint64_t UndefBits[2]) { 1805 // Start with zero'd results. 1806 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 1807 1808 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); 1809 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 1810 SDOperand OpVal = BV->getOperand(i); 1811 1812 unsigned PartNo = i >= e/2; // In the upper 128 bits? 1813 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 1814 1815 uint64_t EltBits = 0; 1816 if (OpVal.getOpcode() == ISD::UNDEF) { 1817 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 1818 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 1819 continue; 1820 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 1821 EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 1822 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 1823 assert(CN->getValueType(0) == MVT::f32 && 1824 "Only one legal FP vector type!"); 1825 EltBits = FloatToBits(CN->getValue()); 1826 } else { 1827 // Nonconstant element. 1828 return true; 1829 } 1830 1831 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 1832 } 1833 1834 //printf("%llx %llx %llx %llx\n", 1835 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 1836 return false; 1837} 1838 1839// If this is a splat (repetition) of a value across the whole vector, return 1840// the smallest size that splats it. For example, "0x01010101010101..." is a 1841// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 1842// SplatSize = 1 byte. 1843static bool isConstantSplat(const uint64_t Bits128[2], 1844 const uint64_t Undef128[2], 1845 unsigned &SplatBits, unsigned &SplatUndef, 1846 unsigned &SplatSize) { 1847 1848 // Don't let undefs prevent splats from matching. See if the top 64-bits are 1849 // the same as the lower 64-bits, ignoring undefs. 1850 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 1851 return false; // Can't be a splat if two pieces don't match. 1852 1853 uint64_t Bits64 = Bits128[0] | Bits128[1]; 1854 uint64_t Undef64 = Undef128[0] & Undef128[1]; 1855 1856 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 1857 // undefs. 1858 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 1859 return false; // Can't be a splat if two pieces don't match. 1860 1861 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 1862 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 1863 1864 // If the top 16-bits are different than the lower 16-bits, ignoring 1865 // undefs, we have an i32 splat. 1866 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 1867 SplatBits = Bits32; 1868 SplatUndef = Undef32; 1869 SplatSize = 4; 1870 return true; 1871 } 1872 1873 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 1874 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 1875 1876 // If the top 8-bits are different than the lower 8-bits, ignoring 1877 // undefs, we have an i16 splat. 1878 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 1879 SplatBits = Bits16; 1880 SplatUndef = Undef16; 1881 SplatSize = 2; 1882 return true; 1883 } 1884 1885 // Otherwise, we have an 8-bit splat. 1886 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 1887 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 1888 SplatSize = 1; 1889 return true; 1890} 1891 1892/// BuildSplatI - Build a canonical splati of Val with an element size of 1893/// SplatSize. Cast the result to VT. 1894static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, 1895 SelectionDAG &DAG) { 1896 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 1897 1898 // Force vspltis[hw] -1 to vspltisb -1. 1899 if (Val == -1) SplatSize = 1; 1900 1901 static const MVT::ValueType VTys[] = { // canonical VT to use for each size. 1902 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 1903 }; 1904 MVT::ValueType CanonicalVT = VTys[SplatSize-1]; 1905 1906 // Build a canonical splat for this value. 1907 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT)); 1908 SmallVector<SDOperand, 8> Ops; 1909 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); 1910 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, 1911 &Ops[0], Ops.size()); 1912 return DAG.getNode(ISD::BIT_CONVERT, VT, Res); 1913} 1914 1915/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 1916/// specified intrinsic ID. 1917static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, 1918 SelectionDAG &DAG, 1919 MVT::ValueType DestVT = MVT::Other) { 1920 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 1921 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 1922 DAG.getConstant(IID, MVT::i32), LHS, RHS); 1923} 1924 1925/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 1926/// specified intrinsic ID. 1927static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, 1928 SDOperand Op2, SelectionDAG &DAG, 1929 MVT::ValueType DestVT = MVT::Other) { 1930 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 1931 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 1932 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 1933} 1934 1935 1936/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 1937/// amount. The result has the specified value type. 1938static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, 1939 MVT::ValueType VT, SelectionDAG &DAG) { 1940 // Force LHS/RHS to be the right type. 1941 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 1942 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 1943 1944 SDOperand Ops[16]; 1945 for (unsigned i = 0; i != 16; ++i) 1946 Ops[i] = DAG.getConstant(i+Amt, MVT::i32); 1947 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 1948 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); 1949 return DAG.getNode(ISD::BIT_CONVERT, VT, T); 1950} 1951 1952// If this is a case we can't handle, return null and let the default 1953// expansion code take care of it. If we CAN select this case, and if it 1954// selects to a single instruction, return Op. Otherwise, if we can codegen 1955// this case more efficiently than a constant pool load, lower it to the 1956// sequence of ops that should be used. 1957static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 1958 // If this is a vector of constants or undefs, get the bits. A bit in 1959 // UndefBits is set if the corresponding element of the vector is an 1960 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 1961 // zero. 1962 uint64_t VectorBits[2]; 1963 uint64_t UndefBits[2]; 1964 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 1965 return SDOperand(); // Not a constant vector. 1966 1967 // If this is a splat (repetition) of a value across the whole vector, return 1968 // the smallest size that splats it. For example, "0x01010101010101..." is a 1969 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 1970 // SplatSize = 1 byte. 1971 unsigned SplatBits, SplatUndef, SplatSize; 1972 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 1973 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 1974 1975 // First, handle single instruction cases. 1976 1977 // All zeros? 1978 if (SplatBits == 0) { 1979 // Canonicalize all zero vectors to be v4i32. 1980 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 1981 SDOperand Z = DAG.getConstant(0, MVT::i32); 1982 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 1983 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 1984 } 1985 return Op; 1986 } 1987 1988 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 1989 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 1990 if (SextVal >= -16 && SextVal <= 15) 1991 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 1992 1993 1994 // Two instruction sequences. 1995 1996 // If this value is in the range [-32,30] and is even, use: 1997 // tmp = VSPLTI[bhw], result = add tmp, tmp 1998 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 1999 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); 2000 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); 2001 } 2002 2003 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 2004 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 2005 // for fneg/fabs. 2006 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 2007 // Make -1 and vspltisw -1: 2008 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 2009 2010 // Make the VSLW intrinsic, computing 0x8000_0000. 2011 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 2012 OnesV, DAG); 2013 2014 // xor by OnesV to invert it. 2015 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 2016 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2017 } 2018 2019 // Check to see if this is a wide variety of vsplti*, binop self cases. 2020 unsigned SplatBitSize = SplatSize*8; 2021 static const char SplatCsts[] = { 2022 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 2023 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 2024 }; 2025 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){ 2026 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 2027 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 2028 int i = SplatCsts[idx]; 2029 2030 // Figure out what shift amount will be used by altivec if shifted by i in 2031 // this splat size. 2032 unsigned TypeShiftAmt = i & (SplatBitSize-1); 2033 2034 // vsplti + shl self. 2035 if (SextVal == (i << (int)TypeShiftAmt)) { 2036 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG); 2037 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2038 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 2039 Intrinsic::ppc_altivec_vslw 2040 }; 2041 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG); 2042 } 2043 2044 // vsplti + srl self. 2045 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2046 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG); 2047 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2048 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 2049 Intrinsic::ppc_altivec_vsrw 2050 }; 2051 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG); 2052 } 2053 2054 // vsplti + sra self. 2055 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2056 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG); 2057 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2058 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 2059 Intrinsic::ppc_altivec_vsraw 2060 }; 2061 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG); 2062 } 2063 2064 // vsplti + rol self. 2065 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 2066 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 2067 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG); 2068 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2069 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 2070 Intrinsic::ppc_altivec_vrlw 2071 }; 2072 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG); 2073 } 2074 2075 // t = vsplti c, result = vsldoi t, t, 1 2076 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 2077 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2078 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 2079 } 2080 // t = vsplti c, result = vsldoi t, t, 2 2081 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 2082 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2083 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 2084 } 2085 // t = vsplti c, result = vsldoi t, t, 3 2086 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 2087 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2088 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 2089 } 2090 } 2091 2092 // Three instruction sequences. 2093 2094 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 2095 if (SextVal >= 0 && SextVal <= 31) { 2096 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG); 2097 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG); 2098 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS); 2099 } 2100 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 2101 if (SextVal >= -31 && SextVal <= 0) { 2102 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG); 2103 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG); 2104 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS); 2105 } 2106 } 2107 2108 return SDOperand(); 2109} 2110 2111/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 2112/// the specified operations to build the shuffle. 2113static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, 2114 SDOperand RHS, SelectionDAG &DAG) { 2115 unsigned OpNum = (PFEntry >> 26) & 0x0F; 2116 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 2117 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 2118 2119 enum { 2120 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 2121 OP_VMRGHW, 2122 OP_VMRGLW, 2123 OP_VSPLTISW0, 2124 OP_VSPLTISW1, 2125 OP_VSPLTISW2, 2126 OP_VSPLTISW3, 2127 OP_VSLDOI4, 2128 OP_VSLDOI8, 2129 OP_VSLDOI12 2130 }; 2131 2132 if (OpNum == OP_COPY) { 2133 if (LHSID == (1*9+2)*9+3) return LHS; 2134 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 2135 return RHS; 2136 } 2137 2138 SDOperand OpLHS, OpRHS; 2139 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 2140 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 2141 2142 unsigned ShufIdxs[16]; 2143 switch (OpNum) { 2144 default: assert(0 && "Unknown i32 permute!"); 2145 case OP_VMRGHW: 2146 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 2147 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 2148 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 2149 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 2150 break; 2151 case OP_VMRGLW: 2152 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 2153 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 2154 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 2155 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 2156 break; 2157 case OP_VSPLTISW0: 2158 for (unsigned i = 0; i != 16; ++i) 2159 ShufIdxs[i] = (i&3)+0; 2160 break; 2161 case OP_VSPLTISW1: 2162 for (unsigned i = 0; i != 16; ++i) 2163 ShufIdxs[i] = (i&3)+4; 2164 break; 2165 case OP_VSPLTISW2: 2166 for (unsigned i = 0; i != 16; ++i) 2167 ShufIdxs[i] = (i&3)+8; 2168 break; 2169 case OP_VSPLTISW3: 2170 for (unsigned i = 0; i != 16; ++i) 2171 ShufIdxs[i] = (i&3)+12; 2172 break; 2173 case OP_VSLDOI4: 2174 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 2175 case OP_VSLDOI8: 2176 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 2177 case OP_VSLDOI12: 2178 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 2179 } 2180 SDOperand Ops[16]; 2181 for (unsigned i = 0; i != 16; ++i) 2182 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); 2183 2184 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 2185 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2186} 2187 2188/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 2189/// is a shuffle we can handle in a single instruction, return it. Otherwise, 2190/// return the code it can be lowered into. Worst case, it can always be 2191/// lowered into a vperm. 2192static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 2193 SDOperand V1 = Op.getOperand(0); 2194 SDOperand V2 = Op.getOperand(1); 2195 SDOperand PermMask = Op.getOperand(2); 2196 2197 // Cases that are handled by instructions that take permute immediates 2198 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 2199 // selected by the instruction selector. 2200 if (V2.getOpcode() == ISD::UNDEF) { 2201 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 2202 PPC::isSplatShuffleMask(PermMask.Val, 2) || 2203 PPC::isSplatShuffleMask(PermMask.Val, 4) || 2204 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 2205 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 2206 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 2207 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 2208 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 2209 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 2210 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 2211 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 2212 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 2213 return Op; 2214 } 2215 } 2216 2217 // Altivec has a variety of "shuffle immediates" that take two vector inputs 2218 // and produce a fixed permutation. If any of these match, do not lower to 2219 // VPERM. 2220 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 2221 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 2222 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 2223 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 2224 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 2225 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 2226 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 2227 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 2228 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 2229 return Op; 2230 2231 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 2232 // perfect shuffle table to emit an optimal matching sequence. 2233 unsigned PFIndexes[4]; 2234 bool isFourElementShuffle = true; 2235 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 2236 unsigned EltNo = 8; // Start out undef. 2237 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 2238 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 2239 continue; // Undef, ignore it. 2240 2241 unsigned ByteSource = 2242 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); 2243 if ((ByteSource & 3) != j) { 2244 isFourElementShuffle = false; 2245 break; 2246 } 2247 2248 if (EltNo == 8) { 2249 EltNo = ByteSource/4; 2250 } else if (EltNo != ByteSource/4) { 2251 isFourElementShuffle = false; 2252 break; 2253 } 2254 } 2255 PFIndexes[i] = EltNo; 2256 } 2257 2258 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 2259 // perfect shuffle vector to determine if it is cost effective to do this as 2260 // discrete instructions, or whether we should use a vperm. 2261 if (isFourElementShuffle) { 2262 // Compute the index in the perfect shuffle table. 2263 unsigned PFTableIndex = 2264 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 2265 2266 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 2267 unsigned Cost = (PFEntry >> 30); 2268 2269 // Determining when to avoid vperm is tricky. Many things affect the cost 2270 // of vperm, particularly how many times the perm mask needs to be computed. 2271 // For example, if the perm mask can be hoisted out of a loop or is already 2272 // used (perhaps because there are multiple permutes with the same shuffle 2273 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 2274 // the loop requires an extra register. 2275 // 2276 // As a compromise, we only emit discrete instructions if the shuffle can be 2277 // generated in 3 or fewer operations. When we have loop information 2278 // available, if this block is within a loop, we should avoid using vperm 2279 // for 3-operation perms and use a constant pool load instead. 2280 if (Cost < 3) 2281 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 2282 } 2283 2284 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 2285 // vector that will get spilled to the constant pool. 2286 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 2287 2288 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 2289 // that it is in input element units, not in bytes. Convert now. 2290 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType()); 2291 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 2292 2293 SmallVector<SDOperand, 16> ResultMask; 2294 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 2295 unsigned SrcElt; 2296 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 2297 SrcElt = 0; 2298 else 2299 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 2300 2301 for (unsigned j = 0; j != BytesPerElement; ++j) 2302 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 2303 MVT::i8)); 2304 } 2305 2306 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 2307 &ResultMask[0], ResultMask.size()); 2308 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 2309} 2310 2311/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 2312/// altivec comparison. If it is, return true and fill in Opc/isDot with 2313/// information about the intrinsic. 2314static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, 2315 bool &isDot) { 2316 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); 2317 CompareOpc = -1; 2318 isDot = false; 2319 switch (IntrinsicID) { 2320 default: return false; 2321 // Comparison predicates. 2322 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 2323 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 2324 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 2325 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 2326 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 2327 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 2328 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 2329 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 2330 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 2331 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 2332 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 2333 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 2334 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 2335 2336 // Normal Comparisons. 2337 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 2338 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 2339 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 2340 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 2341 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 2342 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 2343 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 2344 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 2345 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 2346 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 2347 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 2348 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 2349 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 2350 } 2351 return true; 2352} 2353 2354/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 2355/// lower, do it, otherwise return null. 2356static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 2357 // If this is a lowered altivec predicate compare, CompareOpc is set to the 2358 // opcode number of the comparison. 2359 int CompareOpc; 2360 bool isDot; 2361 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 2362 return SDOperand(); // Don't custom lower most intrinsics. 2363 2364 // If this is a non-dot comparison, make the VCMP node and we are done. 2365 if (!isDot) { 2366 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 2367 Op.getOperand(1), Op.getOperand(2), 2368 DAG.getConstant(CompareOpc, MVT::i32)); 2369 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 2370 } 2371 2372 // Create the PPCISD altivec 'dot' comparison node. 2373 SDOperand Ops[] = { 2374 Op.getOperand(2), // LHS 2375 Op.getOperand(3), // RHS 2376 DAG.getConstant(CompareOpc, MVT::i32) 2377 }; 2378 std::vector<MVT::ValueType> VTs; 2379 VTs.push_back(Op.getOperand(2).getValueType()); 2380 VTs.push_back(MVT::Flag); 2381 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2382 2383 // Now that we have the comparison, emit a copy from the CR to a GPR. 2384 // This is flagged to the above dot comparison. 2385 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 2386 DAG.getRegister(PPC::CR6, MVT::i32), 2387 CompNode.getValue(1)); 2388 2389 // Unpack the result based on how the target uses it. 2390 unsigned BitNo; // Bit # of CR6. 2391 bool InvertBit; // Invert result? 2392 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 2393 default: // Can't happen, don't crash on invalid number though. 2394 case 0: // Return the value of the EQ bit of CR6. 2395 BitNo = 0; InvertBit = false; 2396 break; 2397 case 1: // Return the inverted value of the EQ bit of CR6. 2398 BitNo = 0; InvertBit = true; 2399 break; 2400 case 2: // Return the value of the LT bit of CR6. 2401 BitNo = 2; InvertBit = false; 2402 break; 2403 case 3: // Return the inverted value of the LT bit of CR6. 2404 BitNo = 2; InvertBit = true; 2405 break; 2406 } 2407 2408 // Shift the bit into the low position. 2409 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 2410 DAG.getConstant(8-(3-BitNo), MVT::i32)); 2411 // Isolate the bit. 2412 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 2413 DAG.getConstant(1, MVT::i32)); 2414 2415 // If we are supposed to, toggle the bit. 2416 if (InvertBit) 2417 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 2418 DAG.getConstant(1, MVT::i32)); 2419 return Flags; 2420} 2421 2422static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2423 // Create a stack slot that is 16-byte aligned. 2424 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2425 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 2426 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2427 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2428 2429 // Store the input value into Value#0 of the stack slot. 2430 SDOperand Store = DAG.getStore(DAG.getEntryNode(), 2431 Op.getOperand(0), FIdx, NULL, 0); 2432 // Load it out. 2433 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); 2434} 2435 2436static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { 2437 if (Op.getValueType() == MVT::v4i32) { 2438 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2439 2440 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 2441 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 2442 2443 SDOperand RHSSwap = // = vrlw RHS, 16 2444 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 2445 2446 // Shrinkify inputs to v8i16. 2447 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 2448 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 2449 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 2450 2451 // Low parts multiplied together, generating 32-bit results (we ignore the 2452 // top parts). 2453 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 2454 LHS, RHS, DAG, MVT::v4i32); 2455 2456 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 2457 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 2458 // Shift the high parts up 16 bits. 2459 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 2460 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 2461 } else if (Op.getValueType() == MVT::v8i16) { 2462 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2463 2464 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 2465 2466 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 2467 LHS, RHS, Zero, DAG); 2468 } else if (Op.getValueType() == MVT::v16i8) { 2469 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2470 2471 // Multiply the even 8-bit parts, producing 16-bit sums. 2472 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 2473 LHS, RHS, DAG, MVT::v8i16); 2474 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 2475 2476 // Multiply the odd 8-bit parts, producing 16-bit sums. 2477 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 2478 LHS, RHS, DAG, MVT::v8i16); 2479 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 2480 2481 // Merge the results together. 2482 SDOperand Ops[16]; 2483 for (unsigned i = 0; i != 8; ++i) { 2484 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 2485 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 2486 } 2487 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 2488 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2489 } else { 2490 assert(0 && "Unknown mul to lower!"); 2491 abort(); 2492 } 2493} 2494 2495/// LowerOperation - Provide custom lowering hooks for some operations. 2496/// 2497SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 2498 switch (Op.getOpcode()) { 2499 default: assert(0 && "Wasn't expecting to be able to lower this!"); 2500 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 2501 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 2502 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 2503 case ISD::SETCC: return LowerSETCC(Op, DAG); 2504 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 2505 case ISD::FORMAL_ARGUMENTS: 2506 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex); 2507 case ISD::CALL: return LowerCALL(Op, DAG); 2508 case ISD::RET: return LowerRET(Op, DAG); 2509 2510 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 2511 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 2512 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 2513 2514 // Lower 64-bit shifts. 2515 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 2516 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 2517 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 2518 2519 // Vector-related lowering. 2520 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 2521 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 2522 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 2523 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 2524 case ISD::MUL: return LowerMUL(Op, DAG); 2525 } 2526 return SDOperand(); 2527} 2528 2529//===----------------------------------------------------------------------===// 2530// Other Lowering Code 2531//===----------------------------------------------------------------------===// 2532 2533MachineBasicBlock * 2534PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 2535 MachineBasicBlock *BB) { 2536 assert((MI->getOpcode() == PPC::SELECT_CC_I4 || 2537 MI->getOpcode() == PPC::SELECT_CC_I8 || 2538 MI->getOpcode() == PPC::SELECT_CC_F4 || 2539 MI->getOpcode() == PPC::SELECT_CC_F8 || 2540 MI->getOpcode() == PPC::SELECT_CC_VRRC) && 2541 "Unexpected instr type to insert"); 2542 2543 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 2544 // control-flow pattern. The incoming instruction knows the destination vreg 2545 // to set, the condition code register to branch on, the true/false values to 2546 // select between, and a branch opcode to use. 2547 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2548 ilist<MachineBasicBlock>::iterator It = BB; 2549 ++It; 2550 2551 // thisMBB: 2552 // ... 2553 // TrueVal = ... 2554 // cmpTY ccX, r1, r2 2555 // bCC copy1MBB 2556 // fallthrough --> copy0MBB 2557 MachineBasicBlock *thisMBB = BB; 2558 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 2559 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 2560 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2) 2561 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 2562 MachineFunction *F = BB->getParent(); 2563 F->getBasicBlockList().insert(It, copy0MBB); 2564 F->getBasicBlockList().insert(It, sinkMBB); 2565 // Update machine-CFG edges by first adding all successors of the current 2566 // block to the new block which will contain the Phi node for the select. 2567 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 2568 e = BB->succ_end(); i != e; ++i) 2569 sinkMBB->addSuccessor(*i); 2570 // Next, remove all successors of the current block, and add the true 2571 // and fallthrough blocks as its successors. 2572 while(!BB->succ_empty()) 2573 BB->removeSuccessor(BB->succ_begin()); 2574 BB->addSuccessor(copy0MBB); 2575 BB->addSuccessor(sinkMBB); 2576 2577 // copy0MBB: 2578 // %FalseValue = ... 2579 // # fallthrough to sinkMBB 2580 BB = copy0MBB; 2581 2582 // Update machine-CFG edges 2583 BB->addSuccessor(sinkMBB); 2584 2585 // sinkMBB: 2586 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 2587 // ... 2588 BB = sinkMBB; 2589 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg()) 2590 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 2591 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 2592 2593 delete MI; // The pseudo instruction is gone now. 2594 return BB; 2595} 2596 2597//===----------------------------------------------------------------------===// 2598// Target Optimization Hooks 2599//===----------------------------------------------------------------------===// 2600 2601SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 2602 DAGCombinerInfo &DCI) const { 2603 TargetMachine &TM = getTargetMachine(); 2604 SelectionDAG &DAG = DCI.DAG; 2605 switch (N->getOpcode()) { 2606 default: break; 2607 case PPCISD::SHL: 2608 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 2609 if (C->getValue() == 0) // 0 << V -> 0. 2610 return N->getOperand(0); 2611 } 2612 break; 2613 case PPCISD::SRL: 2614 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 2615 if (C->getValue() == 0) // 0 >>u V -> 0. 2616 return N->getOperand(0); 2617 } 2618 break; 2619 case PPCISD::SRA: 2620 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 2621 if (C->getValue() == 0 || // 0 >>s V -> 0. 2622 C->isAllOnesValue()) // -1 >>s V -> -1. 2623 return N->getOperand(0); 2624 } 2625 break; 2626 2627 case ISD::SINT_TO_FP: 2628 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 2629 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 2630 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 2631 // We allow the src/dst to be either f32/f64, but the intermediate 2632 // type must be i64. 2633 if (N->getOperand(0).getValueType() == MVT::i64) { 2634 SDOperand Val = N->getOperand(0).getOperand(0); 2635 if (Val.getValueType() == MVT::f32) { 2636 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 2637 DCI.AddToWorklist(Val.Val); 2638 } 2639 2640 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 2641 DCI.AddToWorklist(Val.Val); 2642 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 2643 DCI.AddToWorklist(Val.Val); 2644 if (N->getValueType(0) == MVT::f32) { 2645 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); 2646 DCI.AddToWorklist(Val.Val); 2647 } 2648 return Val; 2649 } else if (N->getOperand(0).getValueType() == MVT::i32) { 2650 // If the intermediate type is i32, we can avoid the load/store here 2651 // too. 2652 } 2653 } 2654 } 2655 break; 2656 case ISD::STORE: 2657 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 2658 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 2659 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 2660 N->getOperand(1).getValueType() == MVT::i32) { 2661 SDOperand Val = N->getOperand(1).getOperand(0); 2662 if (Val.getValueType() == MVT::f32) { 2663 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 2664 DCI.AddToWorklist(Val.Val); 2665 } 2666 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 2667 DCI.AddToWorklist(Val.Val); 2668 2669 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 2670 N->getOperand(2), N->getOperand(3)); 2671 DCI.AddToWorklist(Val.Val); 2672 return Val; 2673 } 2674 2675 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 2676 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 2677 N->getOperand(1).Val->hasOneUse() && 2678 (N->getOperand(1).getValueType() == MVT::i32 || 2679 N->getOperand(1).getValueType() == MVT::i16)) { 2680 SDOperand BSwapOp = N->getOperand(1).getOperand(0); 2681 // Do an any-extend to 32-bits if this is a half-word input. 2682 if (BSwapOp.getValueType() == MVT::i16) 2683 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); 2684 2685 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, 2686 N->getOperand(2), N->getOperand(3), 2687 DAG.getValueType(N->getOperand(1).getValueType())); 2688 } 2689 break; 2690 case ISD::BSWAP: 2691 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 2692 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && 2693 N->getOperand(0).hasOneUse() && 2694 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 2695 SDOperand Load = N->getOperand(0); 2696 LoadSDNode *LD = cast<LoadSDNode>(Load); 2697 // Create the byte-swapping load. 2698 std::vector<MVT::ValueType> VTs; 2699 VTs.push_back(MVT::i32); 2700 VTs.push_back(MVT::Other); 2701 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); 2702 SDOperand Ops[] = { 2703 LD->getChain(), // Chain 2704 LD->getBasePtr(), // Ptr 2705 SV, // SrcValue 2706 DAG.getValueType(N->getValueType(0)) // VT 2707 }; 2708 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); 2709 2710 // If this is an i16 load, insert the truncate. 2711 SDOperand ResVal = BSLoad; 2712 if (N->getValueType(0) == MVT::i16) 2713 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); 2714 2715 // First, combine the bswap away. This makes the value produced by the 2716 // load dead. 2717 DCI.CombineTo(N, ResVal); 2718 2719 // Next, combine the load away, we give it a bogus result value but a real 2720 // chain result. The result value is dead because the bswap is dead. 2721 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); 2722 2723 // Return N so it doesn't get rechecked! 2724 return SDOperand(N, 0); 2725 } 2726 2727 break; 2728 case PPCISD::VCMP: { 2729 // If a VCMPo node already exists with exactly the same operands as this 2730 // node, use its result instead of this node (VCMPo computes both a CR6 and 2731 // a normal output). 2732 // 2733 if (!N->getOperand(0).hasOneUse() && 2734 !N->getOperand(1).hasOneUse() && 2735 !N->getOperand(2).hasOneUse()) { 2736 2737 // Scan all of the users of the LHS, looking for VCMPo's that match. 2738 SDNode *VCMPoNode = 0; 2739 2740 SDNode *LHSN = N->getOperand(0).Val; 2741 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 2742 UI != E; ++UI) 2743 if ((*UI)->getOpcode() == PPCISD::VCMPo && 2744 (*UI)->getOperand(1) == N->getOperand(1) && 2745 (*UI)->getOperand(2) == N->getOperand(2) && 2746 (*UI)->getOperand(0) == N->getOperand(0)) { 2747 VCMPoNode = *UI; 2748 break; 2749 } 2750 2751 // If there is no VCMPo node, or if the flag value has a single use, don't 2752 // transform this. 2753 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 2754 break; 2755 2756 // Look at the (necessarily single) use of the flag value. If it has a 2757 // chain, this transformation is more complex. Note that multiple things 2758 // could use the value result, which we should ignore. 2759 SDNode *FlagUser = 0; 2760 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 2761 FlagUser == 0; ++UI) { 2762 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 2763 SDNode *User = *UI; 2764 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2765 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { 2766 FlagUser = User; 2767 break; 2768 } 2769 } 2770 } 2771 2772 // If the user is a MFCR instruction, we know this is safe. Otherwise we 2773 // give up for right now. 2774 if (FlagUser->getOpcode() == PPCISD::MFCR) 2775 return SDOperand(VCMPoNode, 0); 2776 } 2777 break; 2778 } 2779 case ISD::BR_CC: { 2780 // If this is a branch on an altivec predicate comparison, lower this so 2781 // that we don't have to do a MFCR: instead, branch directly on CR6. This 2782 // lowering is done pre-legalize, because the legalizer lowers the predicate 2783 // compare down to code that is difficult to reassemble. 2784 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2785 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); 2786 int CompareOpc; 2787 bool isDot; 2788 2789 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 2790 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 2791 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 2792 assert(isDot && "Can't compare against a vector result!"); 2793 2794 // If this is a comparison against something other than 0/1, then we know 2795 // that the condition is never/always true. 2796 unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); 2797 if (Val != 0 && Val != 1) { 2798 if (CC == ISD::SETEQ) // Cond never true, remove branch. 2799 return N->getOperand(0); 2800 // Always !=, turn it into an unconditional branch. 2801 return DAG.getNode(ISD::BR, MVT::Other, 2802 N->getOperand(0), N->getOperand(4)); 2803 } 2804 2805 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 2806 2807 // Create the PPCISD altivec 'dot' comparison node. 2808 std::vector<MVT::ValueType> VTs; 2809 SDOperand Ops[] = { 2810 LHS.getOperand(2), // LHS of compare 2811 LHS.getOperand(3), // RHS of compare 2812 DAG.getConstant(CompareOpc, MVT::i32) 2813 }; 2814 VTs.push_back(LHS.getOperand(2).getValueType()); 2815 VTs.push_back(MVT::Flag); 2816 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2817 2818 // Unpack the result based on how the target uses it. 2819 unsigned CompOpc; 2820 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { 2821 default: // Can't happen, don't crash on invalid number though. 2822 case 0: // Branch on the value of the EQ bit of CR6. 2823 CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE; 2824 break; 2825 case 1: // Branch on the inverted value of the EQ bit of CR6. 2826 CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ; 2827 break; 2828 case 2: // Branch on the value of the LT bit of CR6. 2829 CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE; 2830 break; 2831 case 3: // Branch on the inverted value of the LT bit of CR6. 2832 CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT; 2833 break; 2834 } 2835 2836 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 2837 DAG.getRegister(PPC::CR6, MVT::i32), 2838 DAG.getConstant(CompOpc, MVT::i32), 2839 N->getOperand(4), CompNode.getValue(1)); 2840 } 2841 break; 2842 } 2843 } 2844 2845 return SDOperand(); 2846} 2847 2848//===----------------------------------------------------------------------===// 2849// Inline Assembly Support 2850//===----------------------------------------------------------------------===// 2851 2852void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 2853 uint64_t Mask, 2854 uint64_t &KnownZero, 2855 uint64_t &KnownOne, 2856 unsigned Depth) const { 2857 KnownZero = 0; 2858 KnownOne = 0; 2859 switch (Op.getOpcode()) { 2860 default: break; 2861 case PPCISD::LBRX: { 2862 // lhbrx is known to have the top bits cleared out. 2863 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 2864 KnownZero = 0xFFFF0000; 2865 break; 2866 } 2867 case ISD::INTRINSIC_WO_CHAIN: { 2868 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 2869 default: break; 2870 case Intrinsic::ppc_altivec_vcmpbfp_p: 2871 case Intrinsic::ppc_altivec_vcmpeqfp_p: 2872 case Intrinsic::ppc_altivec_vcmpequb_p: 2873 case Intrinsic::ppc_altivec_vcmpequh_p: 2874 case Intrinsic::ppc_altivec_vcmpequw_p: 2875 case Intrinsic::ppc_altivec_vcmpgefp_p: 2876 case Intrinsic::ppc_altivec_vcmpgtfp_p: 2877 case Intrinsic::ppc_altivec_vcmpgtsb_p: 2878 case Intrinsic::ppc_altivec_vcmpgtsh_p: 2879 case Intrinsic::ppc_altivec_vcmpgtsw_p: 2880 case Intrinsic::ppc_altivec_vcmpgtub_p: 2881 case Intrinsic::ppc_altivec_vcmpgtuh_p: 2882 case Intrinsic::ppc_altivec_vcmpgtuw_p: 2883 KnownZero = ~1U; // All bits but the low one are known to be zero. 2884 break; 2885 } 2886 } 2887 } 2888} 2889 2890 2891/// getConstraintType - Given a constraint letter, return the type of 2892/// constraint it is for this target. 2893PPCTargetLowering::ConstraintType 2894PPCTargetLowering::getConstraintType(char ConstraintLetter) const { 2895 switch (ConstraintLetter) { 2896 default: break; 2897 case 'b': 2898 case 'r': 2899 case 'f': 2900 case 'v': 2901 case 'y': 2902 return C_RegisterClass; 2903 } 2904 return TargetLowering::getConstraintType(ConstraintLetter); 2905} 2906 2907std::pair<unsigned, const TargetRegisterClass*> 2908PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 2909 MVT::ValueType VT) const { 2910 if (Constraint.size() == 1) { 2911 // GCC RS6000 Constraint Letters 2912 switch (Constraint[0]) { 2913 case 'b': // R1-R31 2914 case 'r': // R0-R31 2915 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 2916 return std::make_pair(0U, PPC::G8RCRegisterClass); 2917 return std::make_pair(0U, PPC::GPRCRegisterClass); 2918 case 'f': 2919 if (VT == MVT::f32) 2920 return std::make_pair(0U, PPC::F4RCRegisterClass); 2921 else if (VT == MVT::f64) 2922 return std::make_pair(0U, PPC::F8RCRegisterClass); 2923 break; 2924 case 'v': 2925 return std::make_pair(0U, PPC::VRRCRegisterClass); 2926 case 'y': // crrc 2927 return std::make_pair(0U, PPC::CRRCRegisterClass); 2928 } 2929 } 2930 2931 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2932} 2933 2934 2935// isOperandValidForConstraint 2936SDOperand PPCTargetLowering:: 2937isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) { 2938 switch (Letter) { 2939 default: break; 2940 case 'I': 2941 case 'J': 2942 case 'K': 2943 case 'L': 2944 case 'M': 2945 case 'N': 2946 case 'O': 2947 case 'P': { 2948 if (!isa<ConstantSDNode>(Op)) return SDOperand(0,0);// Must be an immediate. 2949 unsigned Value = cast<ConstantSDNode>(Op)->getValue(); 2950 switch (Letter) { 2951 default: assert(0 && "Unknown constraint letter!"); 2952 case 'I': // "I" is a signed 16-bit constant. 2953 if ((short)Value == (int)Value) return Op; 2954 break; 2955 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 2956 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 2957 if ((short)Value == 0) return Op; 2958 break; 2959 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 2960 if ((Value >> 16) == 0) return Op; 2961 break; 2962 case 'M': // "M" is a constant that is greater than 31. 2963 if (Value > 31) return Op; 2964 break; 2965 case 'N': // "N" is a positive constant that is an exact power of two. 2966 if ((int)Value > 0 && isPowerOf2_32(Value)) return Op; 2967 break; 2968 case 'O': // "O" is the constant zero. 2969 if (Value == 0) return Op; 2970 break; 2971 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 2972 if ((short)-Value == (int)-Value) return Op; 2973 break; 2974 } 2975 break; 2976 } 2977 } 2978 2979 // Handle standard constraint letters. 2980 return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG); 2981} 2982 2983/// isLegalAddressImmediate - Return true if the integer value can be used 2984/// as the offset of the target addressing mode. 2985bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const { 2986 // PPC allows a sign-extended 16-bit immediate field. 2987 return (V > -(1 << 16) && V < (1 << 16)-1); 2988} 2989 2990bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 2991 return TargetLowering::isLegalAddressImmediate(GV); 2992} 2993