PPCISelLowering.cpp revision 6de08f4377302cb73ca6a378410889be423af20f 
1//===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Implementation ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the PPC32ISelLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPC32ISelLowering.h"
15#include "PPC32TargetMachine.h"
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "llvm/Constants.h"
21#include "llvm/Function.h"
22using namespace llvm;
23
24PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
25  : TargetLowering(TM) {
26
27  // Fold away setcc operations if possible.
28  setSetCCIsExpensive();
29
30  // Set up the register classes.
31  addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
32  addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
33  addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
34
35  // PowerPC has no intrinsics for these particular operations
36  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
37  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
38  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
39
40  // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
41  setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
42  setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
43
44  // PowerPC has no SREM/UREM instructions
45  setOperationAction(ISD::SREM, MVT::i32, Expand);
46  setOperationAction(ISD::UREM, MVT::i32, Expand);
47
48  // We don't support sin/cos/sqrt/fmod
49  setOperationAction(ISD::FSIN , MVT::f64, Expand);
50  setOperationAction(ISD::FCOS , MVT::f64, Expand);
51  setOperationAction(ISD::SREM , MVT::f64, Expand);
52  setOperationAction(ISD::FSIN , MVT::f32, Expand);
53  setOperationAction(ISD::FCOS , MVT::f32, Expand);
54  setOperationAction(ISD::SREM , MVT::f32, Expand);
55
56  // If we're enabling GP optimizations, use hardware square root
57  if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) {
58    setOperationAction(ISD::FSQRT, MVT::f64, Expand);
59    setOperationAction(ISD::FSQRT, MVT::f32, Expand);
60  }
61
62  // PowerPC does not have CTPOP or CTTZ
63  setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
64  setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
65
66  // PowerPC does not have Select
67  setOperationAction(ISD::SELECT, MVT::i32, Expand);
68  setOperationAction(ISD::SELECT, MVT::f32, Expand);
69  setOperationAction(ISD::SELECT, MVT::f64, Expand);
70
71  // PowerPC wants to turn select_cc of FP into fsel when possible.
72  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
73  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
74
75  // PowerPC does not have BRCOND* which requires SetCC
76  setOperationAction(ISD::BRCOND,       MVT::Other, Expand);
77  setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
78
79  // PowerPC does not have FP_TO_UINT
80  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
81
82  // PowerPC does not have [U|S]INT_TO_FP
83  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
84  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
85
86  setSetCCResultContents(ZeroOrOneSetCCResult);
87
88  computeRegisterProperties();
89}
90
91/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
92static bool isFloatingPointZero(SDOperand Op) {
93  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
94    return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
95  else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
96    // Maybe this has already been legalized into the constant pool?
97    if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
98      if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
99        return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
100  }
101  return false;
102}
103
104/// LowerOperation - Provide custom lowering hooks for some operations.
105///
106SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
107  switch (Op.getOpcode()) {
108  default: assert(0 && "Wasn't expecting to be able to lower this!");
109  case ISD::SELECT_CC:
110    // Turn FP only select_cc's into fsel instructions.
111    if (MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
112        MVT::isFloatingPoint(Op.getOperand(2).getValueType())) {
113      ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
114
115      // Cannot handle SETEQ/SETNE.
116      if (CC == ISD::SETEQ || CC == ISD::SETNE) break;
117
118      MVT::ValueType ResVT = Op.getValueType();
119      MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
120      SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
121      SDOperand TV  = Op.getOperand(2), FV  = Op.getOperand(3);
122
123      // If the RHS of the comparison is a 0.0, we don't need to do the
124      // subtraction at all.
125      if (isFloatingPointZero(RHS))
126        switch (CC) {
127        default: assert(0 && "Invalid FSEL condition"); abort();
128        case ISD::SETULT:
129        case ISD::SETLT:
130          std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
131        case ISD::SETUGE:
132        case ISD::SETGE:
133          return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
134        case ISD::SETUGT:
135        case ISD::SETGT:
136          std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
137        case ISD::SETULE:
138        case ISD::SETLE:
139          return DAG.getNode(PPCISD::FSEL, ResVT,
140                             DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
141        }
142
143      switch (CC) {
144      default: assert(0 && "Invalid FSEL condition"); abort();
145      case ISD::SETULT:
146      case ISD::SETLT:
147        return DAG.getNode(PPCISD::FSEL, ResVT,
148                           DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV, TV);
149      case ISD::SETUGE:
150      case ISD::SETGE:
151        return DAG.getNode(PPCISD::FSEL, ResVT,
152                           DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV, FV);
153      case ISD::SETUGT:
154      case ISD::SETGT:
155        return DAG.getNode(PPCISD::FSEL, ResVT,
156                           DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV, TV);
157      case ISD::SETULE:
158      case ISD::SETLE:
159        return DAG.getNode(PPCISD::FSEL, ResVT,
160                           DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV, FV);
161      }
162    }
163    break;
164  }
165  return SDOperand();
166}
167
168std::vector<SDOperand>
169PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
170  //
171  // add beautiful description of PPC stack frame format, or at least some docs
172  //
173  MachineFunction &MF = DAG.getMachineFunction();
174  MachineFrameInfo *MFI = MF.getFrameInfo();
175  MachineBasicBlock& BB = MF.front();
176  std::vector<SDOperand> ArgValues;
177
178  // Due to the rather complicated nature of the PowerPC ABI, rather than a
179  // fixed size array of physical args, for the sake of simplicity let the STL
180  // handle tracking them for us.
181  std::vector<unsigned> argVR, argPR, argOp;
182  unsigned ArgOffset = 24;
183  unsigned GPR_remaining = 8;
184  unsigned FPR_remaining = 13;
185  unsigned GPR_idx = 0, FPR_idx = 0;
186  static const unsigned GPR[] = {
187    PPC::R3, PPC::R4, PPC::R5, PPC::R6,
188    PPC::R7, PPC::R8, PPC::R9, PPC::R10,
189  };
190  static const unsigned FPR[] = {
191    PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
192    PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
193  };
194
195  // Add DAG nodes to load the arguments...  On entry to a function on PPC,
196  // the arguments start at offset 24, although they are likely to be passed
197  // in registers.
198  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
199    SDOperand newroot, argt;
200    unsigned ObjSize;
201    bool needsLoad = false;
202    bool ArgLive = !I->use_empty();
203    MVT::ValueType ObjectVT = getValueType(I->getType());
204
205    switch (ObjectVT) {
206    default: assert(0 && "Unhandled argument type!");
207    case MVT::i1:
208    case MVT::i8:
209    case MVT::i16:
210    case MVT::i32:
211      ObjSize = 4;
212      if (!ArgLive) break;
213      if (GPR_remaining > 0) {
214        MF.addLiveIn(GPR[GPR_idx]);
215        argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
216                                            GPR[GPR_idx], MVT::i32);
217        if (ObjectVT != MVT::i32)
218          argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
219      } else {
220        needsLoad = true;
221      }
222      break;
223    case MVT::i64: ObjSize = 8;
224      if (!ArgLive) break;
225      if (GPR_remaining > 0) {
226        SDOperand argHi, argLo;
227        MF.addLiveIn(GPR[GPR_idx]);
228        argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
229        // If we have two or more remaining argument registers, then both halves
230        // of the i64 can be sourced from there.  Otherwise, the lower half will
231        // have to come off the stack.  This can happen when an i64 is preceded
232        // by 28 bytes of arguments.
233        if (GPR_remaining > 1) {
234          MF.addLiveIn(GPR[GPR_idx+1]);
235          argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32);
236        } else {
237          int FI = MFI->CreateFixedObject(4, ArgOffset+4);
238          SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
239          argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
240                              DAG.getSrcValue(NULL));
241        }
242        // Build the outgoing arg thingy
243        argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
244        newroot = argLo;
245      } else {
246        needsLoad = true;
247      }
248      break;
249    case MVT::f32:
250    case MVT::f64:
251      ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
252      if (!ArgLive) break;
253      if (FPR_remaining > 0) {
254        MF.addLiveIn(FPR[FPR_idx]);
255        argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
256                                            FPR[FPR_idx], ObjectVT);
257        --FPR_remaining;
258        ++FPR_idx;
259      } else {
260        needsLoad = true;
261      }
262      break;
263    }
264
265    // We need to load the argument to a virtual register if we determined above
266    // that we ran out of physical registers of the appropriate type
267    if (needsLoad) {
268      unsigned SubregOffset = 0;
269      if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
270      if (ObjectVT == MVT::i16) SubregOffset = 2;
271      int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
272      SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
273      FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
274                        DAG.getConstant(SubregOffset, MVT::i32));
275      argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
276                                   DAG.getSrcValue(NULL));
277    }
278
279    // Every 4 bytes of argument space consumes one of the GPRs available for
280    // argument passing.
281    if (GPR_remaining > 0) {
282      unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
283      GPR_remaining -= delta;
284      GPR_idx += delta;
285    }
286    ArgOffset += ObjSize;
287    if (newroot.Val)
288      DAG.setRoot(newroot.getValue(1));
289
290    ArgValues.push_back(argt);
291  }
292
293  // If the function takes variable number of arguments, make a frame index for
294  // the start of the first vararg value... for expansion of llvm.va_start.
295  if (F.isVarArg()) {
296    VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
297    SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
298    // If this function is vararg, store any remaining integer argument regs
299    // to their spots on the stack so that they may be loaded by deferencing the
300    // result of va_next.
301    std::vector<SDOperand> MemOps;
302    for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
303      MF.addLiveIn(GPR[GPR_idx]);
304      SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
305      SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
306                                    Val, FIN, DAG.getSrcValue(NULL));
307      MemOps.push_back(Store);
308      // Increment the address by four for the next argument to store
309      SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
310      FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
311    }
312    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
313  }
314
315  // Finally, inform the code generator which regs we return values in.
316  switch (getValueType(F.getReturnType())) {
317    default: assert(0 && "Unknown type!");
318    case MVT::isVoid: break;
319    case MVT::i1:
320    case MVT::i8:
321    case MVT::i16:
322    case MVT::i32:
323      MF.addLiveOut(PPC::R3);
324      break;
325    case MVT::i64:
326      MF.addLiveOut(PPC::R3);
327      MF.addLiveOut(PPC::R4);
328      break;
329    case MVT::f32:
330    case MVT::f64:
331      MF.addLiveOut(PPC::F1);
332      break;
333  }
334
335  return ArgValues;
336}
337
338std::pair<SDOperand, SDOperand>
339PPC32TargetLowering::LowerCallTo(SDOperand Chain,
340                                 const Type *RetTy, bool isVarArg,
341                                 unsigned CallingConv, bool isTailCall,
342                                 SDOperand Callee, ArgListTy &Args,
343                                 SelectionDAG &DAG) {
344  // args_to_use will accumulate outgoing args for the ISD::CALL case in
345  // SelectExpr to use to put the arguments in the appropriate registers.
346  std::vector<SDOperand> args_to_use;
347
348  // Count how many bytes are to be pushed on the stack, including the linkage
349  // area, and parameter passing area.
350  unsigned NumBytes = 24;
351
352  if (Args.empty()) {
353    Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
354                        DAG.getConstant(NumBytes, getPointerTy()));
355  } else {
356    for (unsigned i = 0, e = Args.size(); i != e; ++i) {
357      switch (getValueType(Args[i].second)) {
358      default: assert(0 && "Unknown value type!");
359      case MVT::i1:
360      case MVT::i8:
361      case MVT::i16:
362      case MVT::i32:
363      case MVT::f32:
364        NumBytes += 4;
365        break;
366      case MVT::i64:
367      case MVT::f64:
368        NumBytes += 8;
369        break;
370      }
371    }
372
373    // Just to be safe, we'll always reserve the full 24 bytes of linkage area
374    // plus 32 bytes of argument space in case any called code gets funky on us.
375    // (Required by ABI to support var arg)
376    if (NumBytes < 56) NumBytes = 56;
377
378    // Adjust the stack pointer for the new arguments...
379    // These operations are automatically eliminated by the prolog/epilog pass
380    Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
381                        DAG.getConstant(NumBytes, getPointerTy()));
382
383    // Set up a copy of the stack pointer for use loading and storing any
384    // arguments that may not fit in the registers available for argument
385    // passing.
386    SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
387                                            PPC::R1, MVT::i32);
388
389    // Figure out which arguments are going to go in registers, and which in
390    // memory.  Also, if this is a vararg function, floating point operations
391    // must be stored to our stack, and loaded into integer regs as well, if
392    // any integer regs are available for argument passing.
393    unsigned ArgOffset = 24;
394    unsigned GPR_remaining = 8;
395    unsigned FPR_remaining = 13;
396
397    std::vector<SDOperand> MemOps;
398    for (unsigned i = 0, e = Args.size(); i != e; ++i) {
399      // PtrOff will be used to store the current argument to the stack if a
400      // register cannot be found for it.
401      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
402      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
403      MVT::ValueType ArgVT = getValueType(Args[i].second);
404
405      switch (ArgVT) {
406      default: assert(0 && "Unexpected ValueType for argument!");
407      case MVT::i1:
408      case MVT::i8:
409      case MVT::i16:
410        // Promote the integer to 32 bits.  If the input type is signed use a
411        // sign extend, otherwise use a zero extend.
412        if (Args[i].second->isSigned())
413          Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
414        else
415          Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
416        // FALL THROUGH
417      case MVT::i32:
418        if (GPR_remaining > 0) {
419          args_to_use.push_back(Args[i].first);
420          --GPR_remaining;
421        } else {
422          MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
423                                       Args[i].first, PtrOff,
424                                       DAG.getSrcValue(NULL)));
425        }
426        ArgOffset += 4;
427        break;
428      case MVT::i64:
429        // If we have one free GPR left, we can place the upper half of the i64
430        // in it, and store the other half to the stack.  If we have two or more
431        // free GPRs, then we can pass both halves of the i64 in registers.
432        if (GPR_remaining > 0) {
433          SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
434                                     Args[i].first, DAG.getConstant(1, MVT::i32));
435          SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
436                                     Args[i].first, DAG.getConstant(0, MVT::i32));
437          args_to_use.push_back(Hi);
438          --GPR_remaining;
439          if (GPR_remaining > 0) {
440            args_to_use.push_back(Lo);
441            --GPR_remaining;
442          } else {
443            SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
444            PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
445            MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
446                                         Lo, PtrOff, DAG.getSrcValue(NULL)));
447          }
448        } else {
449          MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
450                                       Args[i].first, PtrOff,
451                                       DAG.getSrcValue(NULL)));
452        }
453        ArgOffset += 8;
454        break;
455      case MVT::f32:
456      case MVT::f64:
457        if (FPR_remaining > 0) {
458          args_to_use.push_back(Args[i].first);
459          --FPR_remaining;
460          if (isVarArg) {
461            SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
462                                          Args[i].first, PtrOff,
463                                          DAG.getSrcValue(NULL));
464            MemOps.push_back(Store);
465            // Float varargs are always shadowed in available integer registers
466            if (GPR_remaining > 0) {
467              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
468                                           DAG.getSrcValue(NULL));
469              MemOps.push_back(Load);
470              args_to_use.push_back(Load);
471              --GPR_remaining;
472            }
473            if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
474              SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
475              PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
476              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
477                                           DAG.getSrcValue(NULL));
478              MemOps.push_back(Load);
479              args_to_use.push_back(Load);
480              --GPR_remaining;
481            }
482          } else {
483            // If we have any FPRs remaining, we may also have GPRs remaining.
484            // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
485            // GPRs.
486            if (GPR_remaining > 0) {
487              args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
488              --GPR_remaining;
489            }
490            if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
491              args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
492              --GPR_remaining;
493            }
494          }
495        } else {
496          MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
497                                       Args[i].first, PtrOff,
498                                       DAG.getSrcValue(NULL)));
499        }
500        ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
501        break;
502      }
503    }
504    if (!MemOps.empty())
505      Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
506  }
507
508  std::vector<MVT::ValueType> RetVals;
509  MVT::ValueType RetTyVT = getValueType(RetTy);
510  if (RetTyVT != MVT::isVoid)
511    RetVals.push_back(RetTyVT);
512  RetVals.push_back(MVT::Other);
513
514  SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
515                                            Chain, Callee, args_to_use), 0);
516  Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
517  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
518                      DAG.getConstant(NumBytes, getPointerTy()));
519  return std::make_pair(TheCall, Chain);
520}
521
522SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
523                                            Value *VAListV, SelectionDAG &DAG) {
524  // vastart just stores the address of the VarArgsFrameIndex slot into the
525  // memory location argument.
526  SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
527  return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
528                     DAG.getSrcValue(VAListV));
529}
530
531std::pair<SDOperand,SDOperand>
532PPC32TargetLowering::LowerVAArg(SDOperand Chain,
533                                SDOperand VAListP, Value *VAListV,
534                                const Type *ArgTy, SelectionDAG &DAG) {
535  MVT::ValueType ArgVT = getValueType(ArgTy);
536
537  SDOperand VAList =
538    DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
539  SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
540  unsigned Amt;
541  if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
542    Amt = 4;
543  else {
544    assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
545           "Other types should have been promoted for varargs!");
546    Amt = 8;
547  }
548  VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
549                       DAG.getConstant(Amt, VAList.getValueType()));
550  Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
551                      VAList, VAListP, DAG.getSrcValue(VAListV));
552  return std::make_pair(Result, Chain);
553}
554
555
556std::pair<SDOperand, SDOperand> PPC32TargetLowering::
557LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
558                        SelectionDAG &DAG) {
559  assert(0 && "LowerFrameReturnAddress unimplemented");
560  abort();
561}
562
563MachineBasicBlock *
564PPC32TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
565                                             MachineBasicBlock *BB) {
566  assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
567          MI->getOpcode() == PPC::SELECT_CC_FP) &&
568         "Unexpected instr type to insert");
569
570  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
571  // control-flow pattern.  The incoming instruction knows the destination vreg
572  // to set, the condition code register to branch on, the true/false values to
573  // select between, and a branch opcode to use.
574  const BasicBlock *LLVM_BB = BB->getBasicBlock();
575  ilist<MachineBasicBlock>::iterator It = BB;
576  ++It;
577
578  //  thisMBB:
579  //  ...
580  //   TrueVal = ...
581  //   cmpTY ccX, r1, r2
582  //   bCC copy1MBB
583  //   fallthrough --> copy0MBB
584  MachineBasicBlock *thisMBB = BB;
585  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
586  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
587  BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
588    .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
589  MachineFunction *F = BB->getParent();
590  F->getBasicBlockList().insert(It, copy0MBB);
591  F->getBasicBlockList().insert(It, sinkMBB);
592  // Update machine-CFG edges
593  BB->addSuccessor(copy0MBB);
594  BB->addSuccessor(sinkMBB);
595
596  //  copy0MBB:
597  //   %FalseValue = ...
598  //   # fallthrough to sinkMBB
599  BB = copy0MBB;
600
601  // Update machine-CFG edges
602  BB->addSuccessor(sinkMBB);
603
604  //  sinkMBB:
605  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
606  //  ...
607  BB = sinkMBB;
608  BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
609    .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
610    .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
611
612  delete MI;   // The pseudo instruction is gone now.
613  return BB;
614}
615
616