PPCISelLowering.cpp revision 7c5a3d390a463fb50a6eee7ae3174817925e6d28 
1//===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Implementation ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the PPC32ISelLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPC32ISelLowering.h"
15#include "PPC32TargetMachine.h"
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/SelectionDAG.h"
19#include "llvm/Function.h"
20
21using namespace llvm;
22
23PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
24  : TargetLowering(TM) {
25
26  // Fold away setcc operations if possible.
27  setSetCCIsExpensive();
28
29  // Set up the register classes.
30  addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
31  addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
32  addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
33
34  // PowerPC has no intrinsics for these particular operations
35  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
36  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
37  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
38
39  // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
40  setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
41  setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
42
43  // PowerPC has no SREM/UREM instructions
44  setOperationAction(ISD::SREM, MVT::i32, Expand);
45  setOperationAction(ISD::UREM, MVT::i32, Expand);
46
47  // We don't support sin/cos/sqrt/fmod
48  setOperationAction(ISD::FSIN , MVT::f64, Expand);
49  setOperationAction(ISD::FCOS , MVT::f64, Expand);
50  setOperationAction(ISD::SREM , MVT::f64, Expand);
51  setOperationAction(ISD::FSIN , MVT::f32, Expand);
52  setOperationAction(ISD::FCOS , MVT::f32, Expand);
53  setOperationAction(ISD::SREM , MVT::f32, Expand);
54
55  // If we're enabling GP optimizations, use hardware square root
56  if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) {
57    setOperationAction(ISD::FSQRT, MVT::f64, Expand);
58    setOperationAction(ISD::FSQRT, MVT::f32, Expand);
59  }
60
61  // PowerPC does not have CTPOP or CTTZ
62  setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
63  setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
64
65  // PowerPC does not have Select
66  setOperationAction(ISD::SELECT, MVT::i32, Expand);
67  setOperationAction(ISD::SELECT, MVT::f32, Expand);
68  setOperationAction(ISD::SELECT, MVT::f64, Expand);
69
70  // PowerPC does not have FP_TO_UINT
71  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
72
73  setSetCCResultContents(ZeroOrOneSetCCResult);
74  addLegalFPImmediate(+0.0); // Necessary for FSEL
75  addLegalFPImmediate(-0.0); //
76
77  computeRegisterProperties();
78}
79
80std::vector<SDOperand>
81PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
82  //
83  // add beautiful description of PPC stack frame format, or at least some docs
84  //
85  MachineFunction &MF = DAG.getMachineFunction();
86  MachineFrameInfo *MFI = MF.getFrameInfo();
87  MachineBasicBlock& BB = MF.front();
88  std::vector<SDOperand> ArgValues;
89
90  // Due to the rather complicated nature of the PowerPC ABI, rather than a
91  // fixed size array of physical args, for the sake of simplicity let the STL
92  // handle tracking them for us.
93  std::vector<unsigned> argVR, argPR, argOp;
94  unsigned ArgOffset = 24;
95  unsigned GPR_remaining = 8;
96  unsigned FPR_remaining = 13;
97  unsigned GPR_idx = 0, FPR_idx = 0;
98  static const unsigned GPR[] = {
99    PPC::R3, PPC::R4, PPC::R5, PPC::R6,
100    PPC::R7, PPC::R8, PPC::R9, PPC::R10,
101  };
102  static const unsigned FPR[] = {
103    PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
104    PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
105  };
106
107  // Add DAG nodes to load the arguments...  On entry to a function on PPC,
108  // the arguments start at offset 24, although they are likely to be passed
109  // in registers.
110  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
111    SDOperand newroot, argt;
112    unsigned ObjSize;
113    bool needsLoad = false;
114    bool ArgLive = !I->use_empty();
115    MVT::ValueType ObjectVT = getValueType(I->getType());
116
117    switch (ObjectVT) {
118      default: assert(0 && "Unhandled argument type!");
119      case MVT::i1:
120      case MVT::i8:
121      case MVT::i16:
122      case MVT::i32:
123        ObjSize = 4;
124        if (!ArgLive) break;
125          if (GPR_remaining > 0) {
126            MF.addLiveIn(GPR[GPR_idx]);
127            argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
128                                                DAG.getRoot());
129            if (ObjectVT != MVT::i32)
130              argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
131          } else {
132            needsLoad = true;
133          }
134            break;
135      case MVT::i64: ObjSize = 8;
136        if (!ArgLive) break;
137          if (GPR_remaining > 0) {
138            SDOperand argHi, argLo;
139            MF.addLiveIn(GPR[GPR_idx]);
140            argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
141            // If we have two or more remaining argument registers, then both halves
142            // of the i64 can be sourced from there.  Otherwise, the lower half will
143            // have to come off the stack.  This can happen when an i64 is preceded
144            // by 28 bytes of arguments.
145            if (GPR_remaining > 1) {
146              MF.addLiveIn(GPR[GPR_idx+1]);
147              argLo = DAG.getCopyFromReg(GPR[GPR_idx+1], MVT::i32, argHi);
148            } else {
149              int FI = MFI->CreateFixedObject(4, ArgOffset+4);
150              SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
151              argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
152                                  DAG.getSrcValue(NULL));
153            }
154            // Build the outgoing arg thingy
155            argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
156            newroot = argLo;
157          } else {
158            needsLoad = true;
159          }
160            break;
161      case MVT::f32:
162      case MVT::f64:
163        ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
164        if (!ArgLive) break;
165          if (FPR_remaining > 0) {
166            MF.addLiveIn(FPR[FPR_idx]);
167            argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
168                                                DAG.getRoot());
169            --FPR_remaining;
170            ++FPR_idx;
171          } else {
172            needsLoad = true;
173          }
174            break;
175    }
176
177    // We need to load the argument to a virtual register if we determined above
178    // that we ran out of physical registers of the appropriate type
179    if (needsLoad) {
180      unsigned SubregOffset = 0;
181      if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
182      if (ObjectVT == MVT::i16) SubregOffset = 2;
183      int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
184      SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
185      FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
186                        DAG.getConstant(SubregOffset, MVT::i32));
187      argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
188                                   DAG.getSrcValue(NULL));
189    }
190
191    // Every 4 bytes of argument space consumes one of the GPRs available for
192    // argument passing.
193    if (GPR_remaining > 0) {
194      unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
195      GPR_remaining -= delta;
196      GPR_idx += delta;
197    }
198    ArgOffset += ObjSize;
199    if (newroot.Val)
200      DAG.setRoot(newroot.getValue(1));
201
202    ArgValues.push_back(argt);
203  }
204
205  // If the function takes variable number of arguments, make a frame index for
206  // the start of the first vararg value... for expansion of llvm.va_start.
207  if (F.isVarArg()) {
208    VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
209    SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
210    // If this function is vararg, store any remaining integer argument regs
211    // to their spots on the stack so that they may be loaded by deferencing the
212    // result of va_next.
213    std::vector<SDOperand> MemOps;
214    for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
215      MF.addLiveIn(GPR[GPR_idx]);
216      SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
217      SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
218                                    Val, FIN, DAG.getSrcValue(NULL));
219      MemOps.push_back(Store);
220      // Increment the address by four for the next argument to store
221      SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
222      FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
223    }
224    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
225  }
226
227  // Finally, inform the code generator which regs we return values in.
228  switch (getValueType(F.getReturnType())) {
229    default: assert(0 && "Unknown type!");
230    case MVT::isVoid: break;
231    case MVT::i1:
232    case MVT::i8:
233    case MVT::i16:
234    case MVT::i32:
235      MF.addLiveOut(PPC::R3);
236      break;
237    case MVT::i64:
238      MF.addLiveOut(PPC::R3);
239      MF.addLiveOut(PPC::R4);
240      break;
241    case MVT::f32:
242    case MVT::f64:
243      MF.addLiveOut(PPC::F1);
244      break;
245  }
246
247  return ArgValues;
248}
249
250std::pair<SDOperand, SDOperand>
251PPC32TargetLowering::LowerCallTo(SDOperand Chain,
252                                 const Type *RetTy, bool isVarArg,
253                                 unsigned CallingConv, bool isTailCall,
254                                 SDOperand Callee, ArgListTy &Args,
255                                 SelectionDAG &DAG) {
256  // args_to_use will accumulate outgoing args for the ISD::CALL case in
257  // SelectExpr to use to put the arguments in the appropriate registers.
258  std::vector<SDOperand> args_to_use;
259
260  // Count how many bytes are to be pushed on the stack, including the linkage
261  // area, and parameter passing area.
262  unsigned NumBytes = 24;
263
264  if (Args.empty()) {
265    Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
266                        DAG.getConstant(NumBytes, getPointerTy()));
267  } else {
268    for (unsigned i = 0, e = Args.size(); i != e; ++i)
269      switch (getValueType(Args[i].second)) {
270        default: assert(0 && "Unknown value type!");
271        case MVT::i1:
272        case MVT::i8:
273        case MVT::i16:
274        case MVT::i32:
275        case MVT::f32:
276          NumBytes += 4;
277          break;
278        case MVT::i64:
279        case MVT::f64:
280          NumBytes += 8;
281          break;
282      }
283
284        // Just to be safe, we'll always reserve the full 24 bytes of linkage area
285        // plus 32 bytes of argument space in case any called code gets funky on us.
286        // (Required by ABI to support var arg)
287        if (NumBytes < 56) NumBytes = 56;
288
289    // Adjust the stack pointer for the new arguments...
290    // These operations are automatically eliminated by the prolog/epilog pass
291    Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
292                        DAG.getConstant(NumBytes, getPointerTy()));
293
294    // Set up a copy of the stack pointer for use loading and storing any
295    // arguments that may not fit in the registers available for argument
296    // passing.
297    SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
298                                            DAG.getEntryNode());
299
300    // Figure out which arguments are going to go in registers, and which in
301    // memory.  Also, if this is a vararg function, floating point operations
302    // must be stored to our stack, and loaded into integer regs as well, if
303    // any integer regs are available for argument passing.
304    unsigned ArgOffset = 24;
305    unsigned GPR_remaining = 8;
306    unsigned FPR_remaining = 13;
307
308    std::vector<SDOperand> MemOps;
309    for (unsigned i = 0, e = Args.size(); i != e; ++i) {
310      // PtrOff will be used to store the current argument to the stack if a
311      // register cannot be found for it.
312      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
313      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
314      MVT::ValueType ArgVT = getValueType(Args[i].second);
315
316      switch (ArgVT) {
317        default: assert(0 && "Unexpected ValueType for argument!");
318        case MVT::i1:
319        case MVT::i8:
320        case MVT::i16:
321          // Promote the integer to 32 bits.  If the input type is signed use a
322          // sign extend, otherwise use a zero extend.
323          if (Args[i].second->isSigned())
324            Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
325          else
326            Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
327          // FALL THROUGH
328        case MVT::i32:
329          if (GPR_remaining > 0) {
330            args_to_use.push_back(Args[i].first);
331            --GPR_remaining;
332          } else {
333            MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
334                                         Args[i].first, PtrOff,
335                                         DAG.getSrcValue(NULL)));
336          }
337          ArgOffset += 4;
338          break;
339        case MVT::i64:
340          // If we have one free GPR left, we can place the upper half of the i64
341          // in it, and store the other half to the stack.  If we have two or more
342          // free GPRs, then we can pass both halves of the i64 in registers.
343          if (GPR_remaining > 0) {
344            SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
345                                       Args[i].first, DAG.getConstant(1, MVT::i32));
346            SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
347                                       Args[i].first, DAG.getConstant(0, MVT::i32));
348            args_to_use.push_back(Hi);
349            --GPR_remaining;
350            if (GPR_remaining > 0) {
351              args_to_use.push_back(Lo);
352              --GPR_remaining;
353            } else {
354              SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
355              PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
356              MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
357                                           Lo, PtrOff, DAG.getSrcValue(NULL)));
358            }
359          } else {
360            MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
361                                         Args[i].first, PtrOff,
362                                         DAG.getSrcValue(NULL)));
363          }
364          ArgOffset += 8;
365          break;
366        case MVT::f32:
367        case MVT::f64:
368          if (FPR_remaining > 0) {
369            args_to_use.push_back(Args[i].first);
370            --FPR_remaining;
371            if (isVarArg) {
372              SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
373                                            Args[i].first, PtrOff,
374                                            DAG.getSrcValue(NULL));
375              MemOps.push_back(Store);
376              // Float varargs are always shadowed in available integer registers
377              if (GPR_remaining > 0) {
378                SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
379                                             DAG.getSrcValue(NULL));
380                MemOps.push_back(Load);
381                args_to_use.push_back(Load);
382                --GPR_remaining;
383              }
384              if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
385                SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
386                PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
387                SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
388                                             DAG.getSrcValue(NULL));
389                MemOps.push_back(Load);
390                args_to_use.push_back(Load);
391                --GPR_remaining;
392              }
393            } else {
394              // If we have any FPRs remaining, we may also have GPRs remaining.
395              // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
396              // GPRs.
397              if (GPR_remaining > 0) {
398                args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
399                --GPR_remaining;
400              }
401              if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
402                args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
403                --GPR_remaining;
404              }
405            }
406          } else {
407            MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
408                                         Args[i].first, PtrOff,
409                                         DAG.getSrcValue(NULL)));
410          }
411          ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
412          break;
413      }
414    }
415    if (!MemOps.empty())
416      Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
417  }
418
419  std::vector<MVT::ValueType> RetVals;
420  MVT::ValueType RetTyVT = getValueType(RetTy);
421  if (RetTyVT != MVT::isVoid)
422    RetVals.push_back(RetTyVT);
423  RetVals.push_back(MVT::Other);
424
425  SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
426                                            Chain, Callee, args_to_use), 0);
427  Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
428  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
429                      DAG.getConstant(NumBytes, getPointerTy()));
430  return std::make_pair(TheCall, Chain);
431}
432
433SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
434                                            Value *VAListV, SelectionDAG &DAG) {
435  // vastart just stores the address of the VarArgsFrameIndex slot into the
436  // memory location argument.
437  SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
438  return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
439                     DAG.getSrcValue(VAListV));
440}
441
442std::pair<SDOperand,SDOperand>
443PPC32TargetLowering::LowerVAArg(SDOperand Chain,
444                                SDOperand VAListP, Value *VAListV,
445                                const Type *ArgTy, SelectionDAG &DAG) {
446  MVT::ValueType ArgVT = getValueType(ArgTy);
447
448  SDOperand VAList =
449    DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
450  SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
451  unsigned Amt;
452  if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
453    Amt = 4;
454  else {
455    assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
456           "Other types should have been promoted for varargs!");
457    Amt = 8;
458  }
459  VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
460                       DAG.getConstant(Amt, VAList.getValueType()));
461  Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
462                      VAList, VAListP, DAG.getSrcValue(VAListV));
463  return std::make_pair(Result, Chain);
464}
465
466
467std::pair<SDOperand, SDOperand> PPC32TargetLowering::
468LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
469                        SelectionDAG &DAG) {
470  assert(0 && "LowerFrameReturnAddress unimplemented");
471  abort();
472}
473