PPCISelLowering.h revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb
1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that PPC uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17 18#include "PPC.h" 19#include "PPCInstrInfo.h" 20#include "PPCRegisterInfo.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/Target/TargetLowering.h" 24 25namespace llvm { 26 namespace PPCISD { 27 enum NodeType { 28 // Start the numbering where the builtin ops and target ops leave off. 29 FIRST_NUMBER = ISD::BUILTIN_OP_END, 30 31 /// FSEL - Traditional three-operand fsel node. 32 /// 33 FSEL, 34 35 /// FCFID - The FCFID instruction, taking an f64 operand and producing 36 /// and f64 value containing the FP representation of the integer that 37 /// was temporarily in the f64 operand. 38 FCFID, 39 40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 41 /// unsigned integers and single-precision outputs. 42 FCFIDU, FCFIDS, FCFIDUS, 43 44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 45 /// operand, producing an f64 value containing the integer representation 46 /// of that FP value. 47 FCTIDZ, FCTIWZ, 48 49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 50 /// unsigned integers. 51 FCTIDUZ, FCTIWUZ, 52 53 /// Reciprocal estimate instructions (unary FP ops). 54 FRE, FRSQRTE, 55 56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 57 // three v4f32 operands and producing a v4f32 result. 58 VMADDFP, VNMSUBFP, 59 60 /// VPERM - The PPC VPERM Instruction. 61 /// 62 VPERM, 63 64 /// Hi/Lo - These represent the high and low 16-bit parts of a global 65 /// address respectively. These nodes have two operands, the first of 66 /// which must be a TargetGlobalAddress, and the second of which must be a 67 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 68 /// though these are usually folded into other nodes. 69 Hi, Lo, 70 71 TOC_ENTRY, 72 73 /// The following two target-specific nodes are used for calls through 74 /// function pointers in the 64-bit SVR4 ABI. 75 76 /// Like a regular LOAD but additionally taking/producing a flag. 77 LOAD, 78 79 /// Like LOAD (taking/producing a flag), but using r2 as hard-coded 80 /// destination. 81 LOAD_TOC, 82 83 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 84 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 85 /// compute an allocation on the stack. 86 DYNALLOC, 87 88 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 89 /// at function entry, used for PIC code. 90 GlobalBaseReg, 91 92 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 93 /// shift amounts. These nodes are generated by the multi-precision shift 94 /// code. 95 SRL, SRA, SHL, 96 97 /// CALL - A direct function call. 98 /// CALL_NOP is a call with the special NOP which follows 64-bit 99 /// SVR4 calls. 100 CALL, CALL_NOP, 101 102 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 103 /// MTCTR instruction. 104 MTCTR, 105 106 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 107 /// BCTRL instruction. 108 BCTRL, 109 110 /// Return with a flag operand, matched by 'blr' 111 RET_FLAG, 112 113 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 114 /// This copies the bits corresponding to the specified CRREG into the 115 /// resultant GPR. Bits corresponding to other CR regs are undefined. 116 MFOCRF, 117 118 // FIXME: Remove these once the ANDI glue bug is fixed: 119 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 120 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to 121 /// implement truncation of i32 or i64 to i1. 122 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT, 123 124 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 125 EH_SJLJ_SETJMP, 126 127 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 128 EH_SJLJ_LONGJMP, 129 130 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 131 /// instructions. For lack of better number, we use the opcode number 132 /// encoding for the OPC field to identify the compare. For example, 838 133 /// is VCMPGTSH. 134 VCMP, 135 136 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 137 /// altivec VCMP*o instructions. For lack of better number, we use the 138 /// opcode number encoding for the OPC field to identify the compare. For 139 /// example, 838 is VCMPGTSH. 140 VCMPo, 141 142 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 143 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 144 /// condition register to branch on, OPC is the branch opcode to use (e.g. 145 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 146 /// an optional input flag argument. 147 COND_BRANCH, 148 149 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 150 /// loops. 151 BDNZ, BDZ, 152 153 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 154 /// towards zero. Used only as part of the long double-to-int 155 /// conversion sequence. 156 FADDRTZ, 157 158 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 159 MFFS, 160 161 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and 162 /// reserve indexed. This is used to implement atomic operations. 163 LARX, 164 165 /// STCX = This corresponds to PPC stcx. instrcution: store conditional 166 /// indexed. This is used to implement atomic operations. 167 STCX, 168 169 /// TC_RETURN - A tail call return. 170 /// operand #0 chain 171 /// operand #1 callee (register or absolute) 172 /// operand #2 stack adjustment 173 /// operand #3 optional in flag 174 TC_RETURN, 175 176 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 177 CR6SET, 178 CR6UNSET, 179 180 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 181 /// on PPC32. 182 PPC32_GOT, 183 184 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec 185 /// TLS model, produces an ADDIS8 instruction that adds the GOT 186 /// base to sym\@got\@tprel\@ha. 187 ADDIS_GOT_TPREL_HA, 188 189 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 190 /// TLS model, produces a LD instruction with base register G8RReg 191 /// and offset sym\@got\@tprel\@l. This completes the addition that 192 /// finds the offset of "sym" relative to the thread pointer. 193 LD_GOT_TPREL_L, 194 195 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 196 /// model, produces an ADD instruction that adds the contents of 197 /// G8RReg to the thread pointer. Symbol contains a relocation 198 /// sym\@tls which is to be replaced by the thread pointer and 199 /// identifies to the linker that the instruction is part of a 200 /// TLS sequence. 201 ADD_TLS, 202 203 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS 204 /// model, produces an ADDIS8 instruction that adds the GOT base 205 /// register to sym\@got\@tlsgd\@ha. 206 ADDIS_TLSGD_HA, 207 208 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 209 /// model, produces an ADDI8 instruction that adds G8RReg to 210 /// sym\@got\@tlsgd\@l. 211 ADDI_TLSGD_L, 212 213 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS 214 /// model, produces a call to __tls_get_addr(sym\@tlsgd). 215 GET_TLS_ADDR, 216 217 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS 218 /// model, produces an ADDIS8 instruction that adds the GOT base 219 /// register to sym\@got\@tlsld\@ha. 220 ADDIS_TLSLD_HA, 221 222 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 223 /// model, produces an ADDI8 instruction that adds G8RReg to 224 /// sym\@got\@tlsld\@l. 225 ADDI_TLSLD_L, 226 227 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS 228 /// model, produces a call to __tls_get_addr(sym\@tlsld). 229 GET_TLSLD_ADDR, 230 231 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the 232 /// local-dynamic TLS model, produces an ADDIS8 instruction 233 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed 234 /// to tie this in place following a copy to %X3 from the result 235 /// of a GET_TLSLD_ADDR. 236 ADDIS_DTPREL_HA, 237 238 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 239 /// model, produces an ADDI8 instruction that adds G8RReg to 240 /// sym\@got\@dtprel\@l. 241 ADDI_DTPREL_L, 242 243 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 244 /// during instruction selection to optimize a BUILD_VECTOR into 245 /// operations on splats. This is necessary to avoid losing these 246 /// optimizations due to constant folding. 247 VADD_SPLAT, 248 249 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 250 /// operand identifies the operating system entry point. 251 SC, 252 253 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 254 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 255 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 256 /// i32. 257 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 258 259 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 260 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 261 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 262 /// or i32. 263 LBRX, 264 265 /// STFIWX - The STFIWX instruction. The first operand is an input token 266 /// chain, then an f64 value to store, then an address to store it to. 267 STFIWX, 268 269 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 270 /// load which sign-extends from a 32-bit integer value into the 271 /// destination 64-bit register. 272 LFIWAX, 273 274 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 275 /// load which zero-extends from a 32-bit integer value into the 276 /// destination 64-bit register. 277 LFIWZX, 278 279 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model, 280 /// produces an ADDIS8 instruction that adds the TOC base register to 281 /// sym\@toc\@ha. 282 ADDIS_TOC_HA, 283 284 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model, 285 /// produces a LD instruction with base register G8RReg and offset 286 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 287 LD_TOC_L, 288 289 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces 290 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l. 291 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 292 ADDI_TOC_L 293 }; 294 } 295 296 /// Define some predicates that are used for node matching. 297 namespace PPC { 298 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 299 /// VPKUHUM instruction. 300 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary, 301 SelectionDAG &DAG); 302 303 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 304 /// VPKUWUM instruction. 305 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary, 306 SelectionDAG &DAG); 307 308 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 309 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 310 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 311 bool isUnary, SelectionDAG &DAG); 312 313 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 314 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 315 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 316 bool isUnary, SelectionDAG &DAG); 317 318 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 319 /// amount, otherwise return -1. 320 int isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG); 321 322 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 323 /// specifies a splat of a single element that is suitable for input to 324 /// VSPLTB/VSPLTH/VSPLTW. 325 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 326 327 /// isAllNegativeZeroVector - Returns true if all elements of build_vector 328 /// are -0.0. 329 bool isAllNegativeZeroVector(SDNode *N); 330 331 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 332 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 333 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG); 334 335 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 336 /// formed by using a vspltis[bhw] instruction of the specified element 337 /// size, return the constant being splatted. The ByteSize field indicates 338 /// the number of bytes of each element [124] -> [bhw]. 339 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 340 } 341 342 class PPCSubtarget; 343 class PPCTargetLowering : public TargetLowering { 344 const PPCSubtarget &Subtarget; 345 346 public: 347 explicit PPCTargetLowering(PPCTargetMachine &TM); 348 349 /// getTargetNodeName() - This method returns the name of a target specific 350 /// DAG node. 351 const char *getTargetNodeName(unsigned Opcode) const override; 352 353 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; } 354 355 /// getSetCCResultType - Return the ISD::SETCC ValueType 356 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; 357 358 /// getPreIndexedAddressParts - returns true by value, base pointer and 359 /// offset pointer and addressing mode by reference if the node's address 360 /// can be legally represented as pre-indexed load / store address. 361 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 362 SDValue &Offset, 363 ISD::MemIndexedMode &AM, 364 SelectionDAG &DAG) const override; 365 366 /// SelectAddressRegReg - Given the specified addressed, check to see if it 367 /// can be represented as an indexed [r+r] operation. Returns false if it 368 /// can be more efficiently represented with [r+imm]. 369 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 370 SelectionDAG &DAG) const; 371 372 /// SelectAddressRegImm - Returns true if the address N can be represented 373 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 374 /// is not better represented as reg+reg. If Aligned is true, only accept 375 /// displacements suitable for STD and friends, i.e. multiples of 4. 376 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 377 SelectionDAG &DAG, bool Aligned) const; 378 379 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 380 /// represented as an indexed [r+r] operation. 381 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 382 SelectionDAG &DAG) const; 383 384 Sched::Preference getSchedulingPreference(SDNode *N) const override; 385 386 /// LowerOperation - Provide custom lowering hooks for some operations. 387 /// 388 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 389 390 /// ReplaceNodeResults - Replace the results of node with an illegal result 391 /// type with new values built out of custom code. 392 /// 393 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 394 SelectionDAG &DAG) const override; 395 396 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 397 398 unsigned getRegisterByName(const char* RegName, EVT VT) const override; 399 400 void computeKnownBitsForTargetNode(const SDValue Op, 401 APInt &KnownZero, 402 APInt &KnownOne, 403 const SelectionDAG &DAG, 404 unsigned Depth = 0) const override; 405 406 MachineBasicBlock * 407 EmitInstrWithCustomInserter(MachineInstr *MI, 408 MachineBasicBlock *MBB) const override; 409 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 410 MachineBasicBlock *MBB, bool is64Bit, 411 unsigned BinOpcode) const; 412 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 413 MachineBasicBlock *MBB, 414 bool is8bit, unsigned Opcode) const; 415 416 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, 417 MachineBasicBlock *MBB) const; 418 419 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, 420 MachineBasicBlock *MBB) const; 421 422 ConstraintType 423 getConstraintType(const std::string &Constraint) const override; 424 425 /// Examine constraint string and operand type and determine a weight value. 426 /// The operand object must already have been set up with the operand type. 427 ConstraintWeight getSingleConstraintMatchWeight( 428 AsmOperandInfo &info, const char *constraint) const override; 429 430 std::pair<unsigned, const TargetRegisterClass*> 431 getRegForInlineAsmConstraint(const std::string &Constraint, 432 MVT VT) const override; 433 434 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 435 /// function arguments in the caller parameter area. This is the actual 436 /// alignment, not its logarithm. 437 unsigned getByValTypeAlignment(Type *Ty) const override; 438 439 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 440 /// vector. If it is invalid, don't add anything to Ops. 441 void LowerAsmOperandForConstraint(SDValue Op, 442 std::string &Constraint, 443 std::vector<SDValue> &Ops, 444 SelectionDAG &DAG) const override; 445 446 /// isLegalAddressingMode - Return true if the addressing mode represented 447 /// by AM is legal for this target, for a load/store of the specified type. 448 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override; 449 450 /// isLegalICmpImmediate - Return true if the specified immediate is legal 451 /// icmp immediate, that is the target has icmp instructions which can 452 /// compare a register against the immediate without having to materialize 453 /// the immediate into a register. 454 bool isLegalICmpImmediate(int64_t Imm) const override; 455 456 /// isLegalAddImmediate - Return true if the specified immediate is legal 457 /// add immediate, that is the target has add instructions which can 458 /// add a register and the immediate without having to materialize 459 /// the immediate into a register. 460 bool isLegalAddImmediate(int64_t Imm) const override; 461 462 /// isTruncateFree - Return true if it's free to truncate a value of 463 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in 464 /// register X1 to i32 by referencing its sub-register R1. 465 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 466 bool isTruncateFree(EVT VT1, EVT VT2) const override; 467 468 /// \brief Returns true if it is beneficial to convert a load of a constant 469 /// to just the constant itself. 470 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 471 Type *Ty) const override; 472 473 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 474 475 /// getOptimalMemOpType - Returns the target specific optimal type for load 476 /// and store operations as a result of memset, memcpy, and memmove 477 /// lowering. If DstAlign is zero that means it's safe to destination 478 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 479 /// means there isn't a need to check it against alignment requirement, 480 /// probably because the source does not need to be loaded. If 'IsMemset' is 481 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 482 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 483 /// source is constant so it does not need to be loaded. 484 /// It returns EVT::Other if the type should be determined using generic 485 /// target-independent logic. 486 EVT 487 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 488 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 489 MachineFunction &MF) const override; 490 491 /// Is unaligned memory access allowed for the given type, and is it fast 492 /// relative to software emulation. 493 bool allowsUnalignedMemoryAccesses(EVT VT, 494 unsigned AddrSpace, 495 bool *Fast = nullptr) const override; 496 497 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 498 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 499 /// expanded to FMAs when this method returns true, otherwise fmuladd is 500 /// expanded to fmul + fadd. 501 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 502 503 // Should we expand the build vector with shuffles? 504 bool 505 shouldExpandBuildVectorWithShuffles(EVT VT, 506 unsigned DefinedValues) const override; 507 508 /// createFastISel - This method returns a target-specific FastISel object, 509 /// or null if the target does not support "fast" instruction selection. 510 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 511 const TargetLibraryInfo *LibInfo) const override; 512 513 private: 514 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 515 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 516 517 bool 518 IsEligibleForTailCallOptimization(SDValue Callee, 519 CallingConv::ID CalleeCC, 520 bool isVarArg, 521 const SmallVectorImpl<ISD::InputArg> &Ins, 522 SelectionDAG& DAG) const; 523 524 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 525 int SPDiff, 526 SDValue Chain, 527 SDValue &LROpOut, 528 SDValue &FPOpOut, 529 bool isDarwinABI, 530 SDLoc dl) const; 531 532 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 533 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 534 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 535 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 536 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 537 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 538 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 539 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 540 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 541 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 542 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 543 const PPCSubtarget &Subtarget) const; 544 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, 545 const PPCSubtarget &Subtarget) const; 546 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG, 547 const PPCSubtarget &Subtarget) const; 548 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 549 const PPCSubtarget &Subtarget) const; 550 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 551 const PPCSubtarget &Subtarget) const; 552 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 553 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 554 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 555 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 556 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const; 557 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 558 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 559 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 560 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 561 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 562 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 563 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 564 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 565 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 566 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 567 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 568 569 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 570 CallingConv::ID CallConv, bool isVarArg, 571 const SmallVectorImpl<ISD::InputArg> &Ins, 572 SDLoc dl, SelectionDAG &DAG, 573 SmallVectorImpl<SDValue> &InVals) const; 574 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, 575 bool isVarArg, 576 SelectionDAG &DAG, 577 SmallVector<std::pair<unsigned, SDValue>, 8> 578 &RegsToPass, 579 SDValue InFlag, SDValue Chain, 580 SDValue &Callee, 581 int SPDiff, unsigned NumBytes, 582 const SmallVectorImpl<ISD::InputArg> &Ins, 583 SmallVectorImpl<SDValue> &InVals) const; 584 585 SDValue 586 LowerFormalArguments(SDValue Chain, 587 CallingConv::ID CallConv, bool isVarArg, 588 const SmallVectorImpl<ISD::InputArg> &Ins, 589 SDLoc dl, SelectionDAG &DAG, 590 SmallVectorImpl<SDValue> &InVals) const override; 591 592 SDValue 593 LowerCall(TargetLowering::CallLoweringInfo &CLI, 594 SmallVectorImpl<SDValue> &InVals) const override; 595 596 bool 597 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 598 bool isVarArg, 599 const SmallVectorImpl<ISD::OutputArg> &Outs, 600 LLVMContext &Context) const override; 601 602 SDValue 603 LowerReturn(SDValue Chain, 604 CallingConv::ID CallConv, bool isVarArg, 605 const SmallVectorImpl<ISD::OutputArg> &Outs, 606 const SmallVectorImpl<SDValue> &OutVals, 607 SDLoc dl, SelectionDAG &DAG) const override; 608 609 SDValue 610 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, 611 SDValue ArgVal, SDLoc dl) const; 612 613 SDValue 614 LowerFormalArguments_Darwin(SDValue Chain, 615 CallingConv::ID CallConv, bool isVarArg, 616 const SmallVectorImpl<ISD::InputArg> &Ins, 617 SDLoc dl, SelectionDAG &DAG, 618 SmallVectorImpl<SDValue> &InVals) const; 619 SDValue 620 LowerFormalArguments_64SVR4(SDValue Chain, 621 CallingConv::ID CallConv, bool isVarArg, 622 const SmallVectorImpl<ISD::InputArg> &Ins, 623 SDLoc dl, SelectionDAG &DAG, 624 SmallVectorImpl<SDValue> &InVals) const; 625 SDValue 626 LowerFormalArguments_32SVR4(SDValue Chain, 627 CallingConv::ID CallConv, bool isVarArg, 628 const SmallVectorImpl<ISD::InputArg> &Ins, 629 SDLoc dl, SelectionDAG &DAG, 630 SmallVectorImpl<SDValue> &InVals) const; 631 632 SDValue 633 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 634 SDValue CallSeqStart, ISD::ArgFlagsTy Flags, 635 SelectionDAG &DAG, SDLoc dl) const; 636 637 SDValue 638 LowerCall_Darwin(SDValue Chain, SDValue Callee, 639 CallingConv::ID CallConv, 640 bool isVarArg, bool isTailCall, 641 const SmallVectorImpl<ISD::OutputArg> &Outs, 642 const SmallVectorImpl<SDValue> &OutVals, 643 const SmallVectorImpl<ISD::InputArg> &Ins, 644 SDLoc dl, SelectionDAG &DAG, 645 SmallVectorImpl<SDValue> &InVals) const; 646 SDValue 647 LowerCall_64SVR4(SDValue Chain, SDValue Callee, 648 CallingConv::ID CallConv, 649 bool isVarArg, bool isTailCall, 650 const SmallVectorImpl<ISD::OutputArg> &Outs, 651 const SmallVectorImpl<SDValue> &OutVals, 652 const SmallVectorImpl<ISD::InputArg> &Ins, 653 SDLoc dl, SelectionDAG &DAG, 654 SmallVectorImpl<SDValue> &InVals) const; 655 SDValue 656 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, 657 bool isVarArg, bool isTailCall, 658 const SmallVectorImpl<ISD::OutputArg> &Outs, 659 const SmallVectorImpl<SDValue> &OutVals, 660 const SmallVectorImpl<ISD::InputArg> &Ins, 661 SDLoc dl, SelectionDAG &DAG, 662 SmallVectorImpl<SDValue> &InVals) const; 663 664 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 665 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 666 667 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const; 668 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const; 669 SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const; 670 SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const; 671 672 CCAssignFn *useFastISelCCs(unsigned Flag) const; 673 }; 674 675 namespace PPC { 676 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 677 const TargetLibraryInfo *LibInfo); 678 } 679 680 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 681 CCValAssign::LocInfo &LocInfo, 682 ISD::ArgFlagsTy &ArgFlags, 683 CCState &State); 684 685 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 686 MVT &LocVT, 687 CCValAssign::LocInfo &LocInfo, 688 ISD::ArgFlagsTy &ArgFlags, 689 CCState &State); 690 691 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 692 MVT &LocVT, 693 CCValAssign::LocInfo &LocInfo, 694 ISD::ArgFlagsTy &ArgFlags, 695 CCState &State); 696} 697 698#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 699