PPCInstr64Bit.td revision 059ca0f5b712e5460dcbccfa802b7adb3bccbac9 
1//===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10// This file describes the PowerPC 64-bit instructions.  These patterns are used
11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
12//
13//===----------------------------------------------------------------------===//
14
15
16//===----------------------------------------------------------------------===//
17// Fixed point instructions.
18//
19
20let PPC970_Unit = 1 in {  // FXU Operations.
21
22def OR8  : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
23                   "or $rA, $rS, $rB", IntGeneral,
24                   [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
25def OR4To8  : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
26                   "or $rA, $rS, $rB", IntGeneral,
27                   []>;
28def OR8To4  : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
29                   "or $rA, $rS, $rB", IntGeneral,
30                   []>;
31                   
32def ADD8  : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
33                     "add $rT, $rA, $rB", IntGeneral,
34                     [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
35def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
36                     "mulhd $rT, $rA, $rB", IntMulHW,
37                     [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
38def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
39                     "mulhdu $rT, $rA, $rB", IntMulHWU,
40                     [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
41
42def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
43                        "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
44
45def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
46                         "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
47def CMPD   : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
48                          "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
49def CMPLD  : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
50                          "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
51
52def SLD  : XForm_6<31,  27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
53                   "sld $rA, $rS, $rB", IntRotateD,
54                   [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
55def SRD  : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
56                   "srd $rA, $rS, $rB", IntRotateD,
57                   [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
58def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
59                   "srad $rA, $rS, $rB", IntRotateD,
60                   [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
61def EXTSW  : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
62                      "extsw $rA, $rS", IntGeneral,
63                      [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
64/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
65def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
66                      "extsw $rA, $rS", IntGeneral,
67                      [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
68
69def SRADI  : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
70                      "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
71def DIVD  : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
72                     "divd $rT, $rA, $rB", IntDivD,
73                     [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
74                     PPC970_DGroup_First, PPC970_DGroup_Cracked;
75def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
76                     "divdu $rT, $rA, $rB", IntDivD,
77                     [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
78                     PPC970_DGroup_First, PPC970_DGroup_Cracked;
79def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
80                     "mulld $rT, $rA, $rB", IntMulHD,
81                     [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
82
83let isTwoAddress = 1, isCommutable = 1 in {
84def RLDIMI : MDForm_1<30, 3,
85                      (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
86                      "rldimi $rA, $rS, $SH, $MB", IntRotateD,
87                      []>, isPPC64;
88}
89
90// Rotate instructions.
91def RLDICL : MDForm_1<30, 0,
92                      (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
93                      "rldicl $rA, $rS, $SH, $MB", IntRotateD,
94                      []>, isPPC64;
95def RLDICR : MDForm_1<30, 1,
96                      (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
97                      "rldicr $rA, $rS, $SH, $ME", IntRotateD,
98                      []>, isPPC64;
99}
100
101
102//===----------------------------------------------------------------------===//
103// Load/Store instructions.
104//
105
106
107let isLoad = 1, PPC970_Unit = 2 in {
108def LWA  : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
109                    "lwa $rT, $DS($rA)", LdStLWA,
110                    []>, isPPC64, PPC970_DGroup_Cracked;
111def LD   : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
112                    "ld $rT, $DS($rA)", LdStLD,
113                    []>, isPPC64;
114
115def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
116                   "lwax $rD, $src", LdStLHA,
117                   [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64,
118                   PPC970_DGroup_Cracked;
119def LDX  : XForm_1<31,  21, (ops G8RC:$rD, memrr:$src),
120                   "ldx $rD, $src", LdStLD,
121                   [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
122}
123let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
124def STD  : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
125                    "std $rT, $DS($rA)", LdStSTD,
126                    []>, isPPC64;
127
128def STDX  : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
129                   "stdx $rS, $rA, $rB", LdStSTD,
130                   []>, isPPC64, PPC970_DGroup_Cracked;
131def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
132                   "stdux $rS, $rA, $rB", LdStSTD,
133                   []>, isPPC64;
134                   
135// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
136def STD_32  : DSForm_2<62, 0, (ops GPRC:$rT, memrix:$dst),
137                       "std $rT, $dst", LdStSTD,
138                       [(PPCstd_32  GPRC:$rT, ixaddr:$dst)]>, isPPC64;
139def STDX_32  : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
140                       "stdx $rT, $dst", LdStSTD,
141                       [(PPCstd_32  GPRC:$rT, xaddr:$dst)]>, isPPC64,
142                       PPC970_DGroup_Cracked;
143}
144
145
146
147//===----------------------------------------------------------------------===//
148// Floating point instructions.
149//
150
151
152let PPC970_Unit = 3 in {  // FPU Operations.
153def FCFID  : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
154                      "fcfid $frD, $frB", FPGeneral,
155                      [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
156def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
157                      "fctidz $frD, $frB", FPGeneral,
158                      [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
159}
160
161
162//===----------------------------------------------------------------------===//
163// Instruction Patterns
164//
165
166// Extensions and truncates to/from 32-bit regs.
167def : Pat<(i64 (zext GPRC:$in)),
168          (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
169def : Pat<(i64 (anyext GPRC:$in)),
170          (OR4To8 GPRC:$in, GPRC:$in)>;
171def : Pat<(i32 (trunc G8RC:$in)),
172          (OR8To4 G8RC:$in, G8RC:$in)>;
173
174// SHL/SRL
175def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
176          (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
177def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
178          (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
179