PPCInstr64Bit.td revision 142b531e024c7b814df74951b378b9e3e11d0d42
1//===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20} 21def u16imm64 : Operand<i64> { 22 let PrintMethod = "printU16ImmOperand"; 23} 24def symbolHi64 : Operand<i64> { 25 let PrintMethod = "printSymbolHi"; 26} 27def symbolLo64 : Operand<i64> { 28 let PrintMethod = "printSymbolLo"; 29} 30 31//===----------------------------------------------------------------------===// 32// 64-bit transformation functions. 33// 34 35def SHL64 : SDNodeXForm<imm, [{ 36 // Transformation function: 63 - imm 37 return getI32Imm(63 - N->getZExtValue()); 38}]>; 39 40def SRL64 : SDNodeXForm<imm, [{ 41 // Transformation function: 64 - imm 42 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 43}]>; 44 45def HI32_48 : SDNodeXForm<imm, [{ 46 // Transformation function: shift the immediate value down into the low bits. 47 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 48}]>; 49 50def HI48_64 : SDNodeXForm<imm, [{ 51 // Transformation function: shift the immediate value down into the low bits. 52 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 53}]>; 54 55 56//===----------------------------------------------------------------------===// 57// Calls. 58// 59 60let Defs = [LR8] in 61 def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>, 62 PPC970_Unit_BRU; 63 64// Darwin ABI Calls. 65let isCall = 1, PPC970_Unit = 7, 66 // All calls clobber the PPC64 non-callee saved registers. 67 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12, 68 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 69 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 70 LR8,CTR8, 71 CR0,CR1,CR5,CR6,CR7,CARRY] in { 72 // Convenient aliases for call instructions 73 let Uses = [RM] in { 74 def BL8_Darwin : IForm<18, 0, 1, 75 (outs), (ins calltarget:$func, variable_ops), 76 "bl $func", BrB, []>; // See Pat patterns below. 77 def BLA8_Darwin : IForm<18, 1, 1, 78 (outs), (ins aaddr:$func, variable_ops), 79 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>; 80 } 81 let Uses = [CTR8, RM] in { 82 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 83 (outs), (ins variable_ops), 84 "bctrl", BrB, 85 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>; 86 } 87} 88 89// ELF 64 ABI Calls = Darwin ABI Calls 90// Used to define BL8_ELF and BLA8_ELF 91let isCall = 1, PPC970_Unit = 7, 92 // All calls clobber the PPC64 non-callee saved registers. 93 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12, 94 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 95 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 96 LR8,CTR8, 97 CR0,CR1,CR5,CR6,CR7,CARRY] in { 98 // Convenient aliases for call instructions 99 let Uses = [RM] in { 100 def BL8_ELF : IForm<18, 0, 1, 101 (outs), (ins calltarget:$func, variable_ops), 102 "bl $func", BrB, []>; // See Pat patterns below. 103 def BLA8_ELF : IForm<18, 1, 1, 104 (outs), (ins aaddr:$func, variable_ops), 105 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; 106 } 107 let Uses = [CTR8, RM] in { 108 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 109 (outs), (ins variable_ops), 110 "bctrl", BrB, 111 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>; 112 } 113} 114 115 116// Calls 117def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)), 118 (BL8_Darwin tglobaladdr:$dst)>; 119def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)), 120 (BL8_Darwin texternalsym:$dst)>; 121 122def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)), 123 (BL8_ELF tglobaladdr:$dst)>; 124def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)), 125 (BL8_ELF texternalsym:$dst)>; 126def : Pat<(PPCnop), 127 (NOP)>; 128 129// Atomic operations 130let usesCustomInserter = 1 in { 131 let Uses = [CR0] in { 132 def ATOMIC_LOAD_ADD_I64 : Pseudo< 133 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 134 "${:comment} ATOMIC_LOAD_ADD_I64 PSEUDO!", 135 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 136 def ATOMIC_LOAD_SUB_I64 : Pseudo< 137 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 138 "${:comment} ATOMIC_LOAD_SUB_I64 PSEUDO!", 139 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 140 def ATOMIC_LOAD_OR_I64 : Pseudo< 141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 142 "${:comment} ATOMIC_LOAD_OR_I64 PSEUDO!", 143 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 144 def ATOMIC_LOAD_XOR_I64 : Pseudo< 145 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 146 "${:comment} ATOMIC_LOAD_XOR_I64 PSEUDO!", 147 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 148 def ATOMIC_LOAD_AND_I64 : Pseudo< 149 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 150 "${:comment} ATOMIC_LOAD_AND_I64 PSEUDO!", 151 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 152 def ATOMIC_LOAD_NAND_I64 : Pseudo< 153 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 154 "${:comment} ATOMIC_LOAD_NAND_I64 PSEUDO!", 155 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 156 157 def ATOMIC_CMP_SWAP_I64 : Pseudo< 158 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), 159 "${:comment} ATOMIC_CMP_SWAP_I64 PSEUDO!", 160 [(set G8RC:$dst, 161 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 162 163 def ATOMIC_SWAP_I64 : Pseudo< 164 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), 165 "${:comment} ATOMIC_SWAP_I64 PSEUDO!", 166 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 167 } 168} 169 170// Instructions to support atomic operations 171def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 172 "ldarx $rD, $ptr", LdStLDARX, 173 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 174 175let Defs = [CR0] in 176def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 177 "stdcx. $rS, $dst", LdStSTDCX, 178 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 179 isDOT; 180 181let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 182def TCRETURNdi8 :Pseudo< (outs), 183 (ins calltarget:$dst, i32imm:$offset, variable_ops), 184 "#TC_RETURNd8 $dst $offset", 185 []>; 186 187let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 188def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), 189 "#TC_RETURNa8 $func $offset", 190 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 191 192let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 193def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops), 194 "#TC_RETURNr8 $dst $offset", 195 []>; 196 197 198let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 199 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 200def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 201 Requires<[In64BitMode]>; 202 203 204 205let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 206 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 207def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 208 "b $dst", BrB, 209 []>; 210 211 212let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 213 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 214def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 215 "ba $dst", BrB, 216 []>; 217 218def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 219 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 220 221def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 222 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 223 224def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 225 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 226 227 228//===----------------------------------------------------------------------===// 229// 64-bit SPR manipulation instrs. 230 231let Uses = [CTR8] in { 232def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 233 "mfctr $rT", SprMFSPR>, 234 PPC970_DGroup_First, PPC970_Unit_FXU; 235} 236let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in { 237def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 238 "mtctr $rS", SprMTSPR>, 239 PPC970_DGroup_First, PPC970_Unit_FXU; 240} 241 242let Defs = [X1], Uses = [X1] in 243def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi), 244 "${:comment} DYNALLOC8 $result, $negsize, $fpsi", 245 [(set G8RC:$result, 246 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 247 248let Defs = [LR8] in { 249def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 250 "mtlr $rS", SprMTSPR>, 251 PPC970_DGroup_First, PPC970_Unit_FXU; 252} 253let Uses = [LR8] in { 254def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 255 "mflr $rT", SprMFSPR>, 256 PPC970_DGroup_First, PPC970_Unit_FXU; 257} 258 259//===----------------------------------------------------------------------===// 260// Fixed point instructions. 261// 262 263let PPC970_Unit = 1 in { // FXU Operations. 264 265// Copies, extends, truncates. 266def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB), 267 "or $rA, $rS, $rB", IntGeneral, 268 []>; 269def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB), 270 "or $rA, $rS, $rB", IntGeneral, 271 []>; 272 273def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 274 "li $rD, $imm", IntGeneral, 275 [(set G8RC:$rD, immSExt16:$imm)]>; 276def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 277 "lis $rD, $imm", IntGeneral, 278 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 279 280// Logical ops. 281def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 282 "nand $rA, $rS, $rB", IntGeneral, 283 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 284def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 285 "and $rA, $rS, $rB", IntGeneral, 286 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 287def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 288 "andc $rA, $rS, $rB", IntGeneral, 289 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 290def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 291 "or $rA, $rS, $rB", IntGeneral, 292 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 293def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 294 "nor $rA, $rS, $rB", IntGeneral, 295 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 296def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 297 "orc $rA, $rS, $rB", IntGeneral, 298 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 299def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 300 "eqv $rA, $rS, $rB", IntGeneral, 301 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 302def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 303 "xor $rA, $rS, $rB", IntGeneral, 304 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 305 306// Logical ops with immediate. 307def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 308 "andi. $dst, $src1, $src2", IntGeneral, 309 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 310 isDOT; 311def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 312 "andis. $dst, $src1, $src2", IntGeneral, 313 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 314 isDOT; 315def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 316 "ori $dst, $src1, $src2", IntGeneral, 317 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 318def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 319 "oris $dst, $src1, $src2", IntGeneral, 320 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 321def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 322 "xori $dst, $src1, $src2", IntGeneral, 323 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 324def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 325 "xoris $dst, $src1, $src2", IntGeneral, 326 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 327 328def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 329 "add $rT, $rA, $rB", IntGeneral, 330 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 331 332let Defs = [CARRY] in { 333def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 334 "addc $rT, $rA, $rB", IntGeneral, 335 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 336 PPC970_DGroup_Cracked; 337def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 338 "addic $rD, $rA, $imm", IntGeneral, 339 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>; 340} 341def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 342 "addi $rD, $rA, $imm", IntGeneral, 343 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 344def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), 345 "addis $rD, $rA, $imm", IntGeneral, 346 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 347 348let Defs = [CARRY] in { 349def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 350 "subfic $rD, $rA, $imm", IntGeneral, 351 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 352def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 353 "subfc $rT, $rA, $rB", IntGeneral, 354 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 355 PPC970_DGroup_Cracked; 356} 357def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 358 "subf $rT, $rA, $rB", IntGeneral, 359 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 360def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 361 "neg $rT, $rA", IntGeneral, 362 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 363let Uses = [CARRY], Defs = [CARRY] in { 364def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 365 "adde $rT, $rA, $rB", IntGeneral, 366 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 367def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 368 "addme $rT, $rA", IntGeneral, 369 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>; 370def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 371 "addze $rT, $rA", IntGeneral, 372 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 373def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 374 "subfe $rT, $rA, $rB", IntGeneral, 375 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 376def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 377 "subfme $rT, $rA", IntGeneral, 378 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>; 379def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 380 "subfze $rT, $rA", IntGeneral, 381 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 382} 383 384 385def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 386 "mulhd $rT, $rA, $rB", IntMulHW, 387 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 388def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 389 "mulhdu $rT, $rA, $rB", IntMulHWU, 390 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 391 392def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 393 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 394def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 395 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 396def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 397 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 398def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 399 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 400 401def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 402 "sld $rA, $rS, $rB", IntRotateD, 403 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 404def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 405 "srd $rA, $rS, $rB", IntRotateD, 406 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 407let Defs = [CARRY] in { 408def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 409 "srad $rA, $rS, $rB", IntRotateD, 410 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 411} 412 413def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 414 "extsb $rA, $rS", IntGeneral, 415 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 416def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 417 "extsh $rA, $rS", IntGeneral, 418 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 419 420def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 421 "extsw $rA, $rS", IntGeneral, 422 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 423/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 424def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 425 "extsw $rA, $rS", IntGeneral, 426 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 427def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 428 "extsw $rA, $rS", IntGeneral, 429 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 430 431let Defs = [CARRY] in { 432def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 433 "sradi $rA, $rS, $SH", IntRotateD, 434 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 435} 436def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 437 "cntlzd $rA, $rS", IntGeneral, 438 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 439 440def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 441 "divd $rT, $rA, $rB", IntDivD, 442 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 443 PPC970_DGroup_First, PPC970_DGroup_Cracked; 444def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 445 "divdu $rT, $rA, $rB", IntDivD, 446 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 447 PPC970_DGroup_First, PPC970_DGroup_Cracked; 448def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 449 "mulld $rT, $rA, $rB", IntMulHD, 450 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 451 452 453let isCommutable = 1 in { 454def RLDIMI : MDForm_1<30, 3, 455 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 456 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 457 []>, isPPC64, RegConstraint<"$rSi = $rA">, 458 NoEncode<"$rSi">; 459} 460 461// Rotate instructions. 462def RLDCL : MDForm_1<30, 0, 463 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB), 464 "rldcl $rA, $rS, $rB, $MB", IntRotateD, 465 []>, isPPC64; 466def RLDICL : MDForm_1<30, 0, 467 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB), 468 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 469 []>, isPPC64; 470def RLDICR : MDForm_1<30, 1, 471 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME), 472 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 473 []>, isPPC64; 474} // End FXU Operations. 475 476 477//===----------------------------------------------------------------------===// 478// Load/Store instructions. 479// 480 481 482// Sign extending loads. 483let canFoldAsLoad = 1, PPC970_Unit = 2 in { 484def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 485 "lha $rD, $src", LdStLHA, 486 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 487 PPC970_DGroup_Cracked; 488def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 489 "lwa $rD, $src", LdStLWA, 490 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, 491 PPC970_DGroup_Cracked; 492def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 493 "lhax $rD, $src", LdStLHA, 494 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 495 PPC970_DGroup_Cracked; 496def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 497 "lwax $rD, $src", LdStLHA, 498 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 499 PPC970_DGroup_Cracked; 500 501// Update forms. 502let mayLoad = 1 in 503def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, 504 ptr_rc:$rA), 505 "lhau $rD, $disp($rA)", LdStGeneral, 506 []>, RegConstraint<"$rA = $ea_result">, 507 NoEncode<"$ea_result">; 508// NO LWAU! 509 510} 511 512// Zero extending loads. 513let canFoldAsLoad = 1, PPC970_Unit = 2 in { 514def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 515 "lbz $rD, $src", LdStGeneral, 516 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 517def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 518 "lhz $rD, $src", LdStGeneral, 519 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 520def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 521 "lwz $rD, $src", LdStGeneral, 522 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 523 524def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 525 "lbzx $rD, $src", LdStGeneral, 526 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 527def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 528 "lhzx $rD, $src", LdStGeneral, 529 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 530def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 531 "lwzx $rD, $src", LdStGeneral, 532 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 533 534 535// Update forms. 536let mayLoad = 1 in { 537def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 538 "lbzu $rD, $addr", LdStGeneral, 539 []>, RegConstraint<"$addr.reg = $ea_result">, 540 NoEncode<"$ea_result">; 541def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 542 "lhzu $rD, $addr", LdStGeneral, 543 []>, RegConstraint<"$addr.reg = $ea_result">, 544 NoEncode<"$ea_result">; 545def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 546 "lwzu $rD, $addr", LdStGeneral, 547 []>, RegConstraint<"$addr.reg = $ea_result">, 548 NoEncode<"$ea_result">; 549} 550} 551 552 553// Full 8-byte loads. 554let canFoldAsLoad = 1, PPC970_Unit = 2 in { 555def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 556 "ld $rD, $src", LdStLD, 557 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; 558// FIXME: This is a pseudo instruction. When the JIT switches to MC, remove its 559// encoding information. 560def LDtoc: DSForm_1<58, 0, (outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 561 "ld $rD, $disp($reg)", LdStLD, 562 [(set G8RC:$rD, 563 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 564let RST = 2, DS = 8 in 565def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg), 566 "ld 2, 8($reg)", LdStLD, 567 [(PPCload_toc G8RC:$reg)]>, isPPC64; 568 569let RST = 2, DS = 40, RA = 1 in 570def LDtoc_restore : DSForm_1<58, 0, (outs), (ins), 571 "ld 2, 40(1)", LdStLD, 572 [(PPCtoc_restore)]>, isPPC64; 573def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 574 "ldx $rD, $src", LdStLD, 575 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 576 577let mayLoad = 1 in 578def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), 579 "ldu $rD, $addr", LdStLD, 580 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 581 NoEncode<"$ea_result">; 582 583} 584 585def : Pat<(PPCload ixaddr:$src), 586 (LD ixaddr:$src)>; 587def : Pat<(PPCload xaddr:$src), 588 (LDX xaddr:$src)>; 589 590let PPC970_Unit = 2 in { 591// Truncating stores. 592def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 593 "stb $rS, $src", LdStGeneral, 594 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 595def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 596 "sth $rS, $src", LdStGeneral, 597 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 598def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 599 "stw $rS, $src", LdStGeneral, 600 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 601def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 602 "stbx $rS, $dst", LdStGeneral, 603 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 604 PPC970_DGroup_Cracked; 605def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 606 "sthx $rS, $dst", LdStGeneral, 607 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 608 PPC970_DGroup_Cracked; 609def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 610 "stwx $rS, $dst", LdStGeneral, 611 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 612 PPC970_DGroup_Cracked; 613// Normal 8-byte stores. 614def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 615 "std $rS, $dst", LdStSTD, 616 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 617def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 618 "stdx $rS, $dst", LdStSTD, 619 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 620 PPC970_DGroup_Cracked; 621} 622 623let PPC970_Unit = 2 in { 624 625def STBU8 : DForm_1<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 626 symbolLo:$ptroff, ptr_rc:$ptrreg), 627 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 628 [(set ptr_rc:$ea_res, 629 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, 630 iaddroff:$ptroff))]>, 631 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 632def STHU8 : DForm_1<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 633 symbolLo:$ptroff, ptr_rc:$ptrreg), 634 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 635 [(set ptr_rc:$ea_res, 636 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, 637 iaddroff:$ptroff))]>, 638 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 639 640def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 641 s16immX4:$ptroff, ptr_rc:$ptrreg), 642 "stdu $rS, $ptroff($ptrreg)", LdStSTD, 643 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, 644 iaddroff:$ptroff))]>, 645 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">, 646 isPPC64; 647 648let mayStore = 1 in 649def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst), 650 "stdux $rS, $dst", LdStSTD, 651 []>, isPPC64; 652 653// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 654def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 655 "std $rT, $dst", LdStSTD, 656 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 657def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 658 "stdx $rT, $dst", LdStSTD, 659 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 660 PPC970_DGroup_Cracked; 661} 662 663 664 665//===----------------------------------------------------------------------===// 666// Floating point instructions. 667// 668 669 670let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations. 671def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 672 "fcfid $frD, $frB", FPGeneral, 673 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 674def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 675 "fctidz $frD, $frB", FPGeneral, 676 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 677} 678 679 680//===----------------------------------------------------------------------===// 681// Instruction Patterns 682// 683 684// Extensions and truncates to/from 32-bit regs. 685def : Pat<(i64 (zext GPRC:$in)), 686 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; 687def : Pat<(i64 (anyext GPRC:$in)), 688 (OR4To8 GPRC:$in, GPRC:$in)>; 689def : Pat<(i32 (trunc G8RC:$in)), 690 (OR8To4 G8RC:$in, G8RC:$in)>; 691 692// Extending loads with i64 targets. 693def : Pat<(zextloadi1 iaddr:$src), 694 (LBZ8 iaddr:$src)>; 695def : Pat<(zextloadi1 xaddr:$src), 696 (LBZX8 xaddr:$src)>; 697def : Pat<(extloadi1 iaddr:$src), 698 (LBZ8 iaddr:$src)>; 699def : Pat<(extloadi1 xaddr:$src), 700 (LBZX8 xaddr:$src)>; 701def : Pat<(extloadi8 iaddr:$src), 702 (LBZ8 iaddr:$src)>; 703def : Pat<(extloadi8 xaddr:$src), 704 (LBZX8 xaddr:$src)>; 705def : Pat<(extloadi16 iaddr:$src), 706 (LHZ8 iaddr:$src)>; 707def : Pat<(extloadi16 xaddr:$src), 708 (LHZX8 xaddr:$src)>; 709def : Pat<(extloadi32 iaddr:$src), 710 (LWZ8 iaddr:$src)>; 711def : Pat<(extloadi32 xaddr:$src), 712 (LWZX8 xaddr:$src)>; 713 714// Standard shifts. These are represented separately from the real shifts above 715// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 716// amounts. 717def : Pat<(sra G8RC:$rS, GPRC:$rB), 718 (SRAD G8RC:$rS, GPRC:$rB)>; 719def : Pat<(srl G8RC:$rS, GPRC:$rB), 720 (SRD G8RC:$rS, GPRC:$rB)>; 721def : Pat<(shl G8RC:$rS, GPRC:$rB), 722 (SLD G8RC:$rS, GPRC:$rB)>; 723 724// SHL/SRL 725def : Pat<(shl G8RC:$in, (i32 imm:$imm)), 726 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 727def : Pat<(srl G8RC:$in, (i32 imm:$imm)), 728 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 729 730// ROTL 731def : Pat<(rotl G8RC:$in, GPRC:$sh), 732 (RLDCL G8RC:$in, GPRC:$sh, 0)>; 733def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), 734 (RLDICL G8RC:$in, imm:$imm, 0)>; 735 736// Hi and Lo for Darwin Global Addresses. 737def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 738def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 739def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 740def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 741def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 742def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 743def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 744def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 745def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 746 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 747def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 748 (ADDIS8 G8RC:$in, tconstpool:$g)>; 749def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 750 (ADDIS8 G8RC:$in, tjumptable:$g)>; 751def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)), 752 (ADDIS8 G8RC:$in, tblockaddress:$g)>; 753