PPCInstr64Bit.td revision 1492a4e5185d963cb79786311b882153fce6718a
1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20} 21def u16imm64 : Operand<i64> { 22 let PrintMethod = "printU16ImmOperand"; 23} 24def symbolHi64 : Operand<i64> { 25 let PrintMethod = "printSymbolHi"; 26 let EncoderMethod = "getHA16Encoding"; 27} 28def symbolLo64 : Operand<i64> { 29 let PrintMethod = "printSymbolLo"; 30 let EncoderMethod = "getLO16Encoding"; 31} 32def tocentry : Operand<iPTR> { 33 let MIOperandInfo = (ops i64imm:$imm); 34} 35def memrs : Operand<iPTR> { // memri where the immediate is a symbolLo64 36 let PrintMethod = "printMemRegImm"; 37 let EncoderMethod = "getMemRIXEncoding"; 38 let MIOperandInfo = (ops symbolLo64:$off, ptr_rc_nor0:$reg); 39} 40def tlsreg : Operand<i64> { 41 let EncoderMethod = "getTLSRegEncoding"; 42} 43def tlsgd : Operand<i64> {} 44 45//===----------------------------------------------------------------------===// 46// 64-bit transformation functions. 47// 48 49def SHL64 : SDNodeXForm<imm, [{ 50 // Transformation function: 63 - imm 51 return getI32Imm(63 - N->getZExtValue()); 52}]>; 53 54def SRL64 : SDNodeXForm<imm, [{ 55 // Transformation function: 64 - imm 56 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 57}]>; 58 59def HI32_48 : SDNodeXForm<imm, [{ 60 // Transformation function: shift the immediate value down into the low bits. 61 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 62}]>; 63 64def HI48_64 : SDNodeXForm<imm, [{ 65 // Transformation function: shift the immediate value down into the low bits. 66 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 67}]>; 68 69 70//===----------------------------------------------------------------------===// 71// Calls. 72// 73 74let Defs = [LR8] in 75 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 76 PPC970_Unit_BRU; 77 78let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 79 // Convenient aliases for call instructions 80 let Uses = [RM] in { 81 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 82 "bl $func", BrB, []>; // See Pat patterns below. 83 84 def BLA8 : IForm<18, 1, 1, (outs), (ins aaddr:$func), 85 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>; 86 } 87 let Uses = [RM], isCodeGenOnly = 1 in { 88 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 89 (outs), (ins calltarget:$func), 90 "bl $func\n\tnop", BrB, []>; 91 92 def BL8_NOP_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24, 93 (outs), (ins calltarget:$func, tlsgd:$sym), 94 "bl $func($sym)\n\tnop", BrB, []>; 95 96 def BL8_NOP_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24, 97 (outs), (ins calltarget:$func, tlsgd:$sym), 98 "bl $func($sym)\n\tnop", BrB, []>; 99 100 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 101 (outs), (ins aaddr:$func), 102 "bla $func\n\tnop", BrB, 103 [(PPCcall_nop (i64 imm:$func))]>; 104 } 105 let Uses = [CTR8, RM] in { 106 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 107 "bctrl", BrB, [(PPCbctrl)]>, 108 Requires<[In64BitMode]>; 109 } 110} 111 112 113// Calls 114def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 115 (BL8 tglobaladdr:$dst)>; 116def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 117 (BL8_NOP tglobaladdr:$dst)>; 118 119def : Pat<(PPCcall (i64 texternalsym:$dst)), 120 (BL8 texternalsym:$dst)>; 121def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 122 (BL8_NOP texternalsym:$dst)>; 123 124// Atomic operations 125let usesCustomInserter = 1 in { 126 let Defs = [CR0] in { 127 def ATOMIC_LOAD_ADD_I64 : Pseudo< 128 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64", 129 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 130 def ATOMIC_LOAD_SUB_I64 : Pseudo< 131 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64", 132 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 133 def ATOMIC_LOAD_OR_I64 : Pseudo< 134 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64", 135 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 136 def ATOMIC_LOAD_XOR_I64 : Pseudo< 137 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64", 138 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 139 def ATOMIC_LOAD_AND_I64 : Pseudo< 140 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64", 141 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 142 def ATOMIC_LOAD_NAND_I64 : Pseudo< 143 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64", 144 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 145 146 def ATOMIC_CMP_SWAP_I64 : Pseudo< 147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64", 148 [(set G8RC:$dst, 149 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 150 151 def ATOMIC_SWAP_I64 : Pseudo< 152 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64", 153 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 154 } 155} 156 157// Instructions to support atomic operations 158def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 159 "ldarx $rD, $ptr", LdStLDARX, 160 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 161 162let Defs = [CR0] in 163def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 164 "stdcx. $rS, $dst", LdStSTDCX, 165 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 166 isDOT; 167 168let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 169def TCRETURNdi8 :Pseudo< (outs), 170 (ins calltarget:$dst, i32imm:$offset), 171 "#TC_RETURNd8 $dst $offset", 172 []>; 173 174let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 175def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), 176 "#TC_RETURNa8 $func $offset", 177 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 178 179let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 180def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 181 "#TC_RETURNr8 $dst $offset", 182 []>; 183 184 185let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 186 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in { 187 let isReturn = 1 in { 188 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 189 Requires<[In64BitMode]>; 190 } 191 192 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 193 Requires<[In64BitMode]>; 194} 195 196 197let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 198 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 199def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 200 "b $dst", BrB, 201 []>; 202 203 204let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 205 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 206def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 207 "ba $dst", BrB, 208 []>; 209 210def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 211 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 212 213def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 214 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 215 216def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 217 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 218 219let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 220 let Defs = [CTR8], Uses = [CTR8] in { 221 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 222 "bdz $dst">; 223 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 224 "bdnz $dst">; 225 } 226} 227 228// 64-but CR instructions 229def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS), 230 "mtcrf $FXM, $rS", BrMCRX>, 231 PPC970_MicroCode, PPC970_Unit_CRU; 232 233def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM), 234 "#MFCR8pseud", SprMFCR>, 235 PPC970_MicroCode, PPC970_Unit_CRU; 236 237def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins), 238 "mfcr $rT", SprMFCR>, 239 PPC970_MicroCode, PPC970_Unit_CRU; 240 241let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 242 usesCustomInserter = 1 in { 243 def EH_SjLj_SetJmp64 : Pseudo<(outs GPRC:$dst), (ins memr:$buf), 244 "#EH_SJLJ_SETJMP64", 245 [(set GPRC:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 246 Requires<[In64BitMode]>; 247 let isTerminator = 1 in 248 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 249 "#EH_SJLJ_LONGJMP64", 250 [(PPCeh_sjlj_longjmp addr:$buf)]>, 251 Requires<[In64BitMode]>; 252} 253 254//===----------------------------------------------------------------------===// 255// 64-bit SPR manipulation instrs. 256 257let Uses = [CTR8] in { 258def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 259 "mfctr $rT", SprMFSPR>, 260 PPC970_DGroup_First, PPC970_Unit_FXU; 261} 262let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in { 263def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 264 "mtctr $rS", SprMTSPR>, 265 PPC970_DGroup_First, PPC970_Unit_FXU; 266} 267 268let Pattern = [(set G8RC:$rT, readcyclecounter)] in 269def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins), 270 "mfspr $rT, 268", SprMFTB>, 271 PPC970_DGroup_First, PPC970_Unit_FXU; 272// Note that encoding mftb using mfspr is now the preferred form, 273// and has been since at least ISA v2.03. The mftb instruction has 274// now been phased out. Using mfspr, however, is known not to work on 275// the POWER3. 276 277let Defs = [X1], Uses = [X1] in 278def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8", 279 [(set G8RC:$result, 280 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 281 282let Defs = [LR8] in { 283def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 284 "mtlr $rS", SprMTSPR>, 285 PPC970_DGroup_First, PPC970_Unit_FXU; 286} 287let Uses = [LR8] in { 288def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 289 "mflr $rT", SprMFSPR>, 290 PPC970_DGroup_First, PPC970_Unit_FXU; 291} 292 293//===----------------------------------------------------------------------===// 294// Fixed point instructions. 295// 296 297let PPC970_Unit = 1 in { // FXU Operations. 298 299let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 300def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 301 "li $rD, $imm", IntSimple, 302 [(set G8RC:$rD, immSExt16:$imm)]>; 303def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 304 "lis $rD, $imm", IntSimple, 305 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 306} 307 308// Logical ops. 309def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 310 "nand $rA, $rS, $rB", IntSimple, 311 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 312def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 313 "and $rA, $rS, $rB", IntSimple, 314 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 315def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 316 "andc $rA, $rS, $rB", IntSimple, 317 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 318def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 319 "or $rA, $rS, $rB", IntSimple, 320 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 321def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 322 "nor $rA, $rS, $rB", IntSimple, 323 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 324def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 325 "orc $rA, $rS, $rB", IntSimple, 326 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 327def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 328 "eqv $rA, $rS, $rB", IntSimple, 329 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 330def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 331 "xor $rA, $rS, $rB", IntSimple, 332 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 333 334// Logical ops with immediate. 335def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 336 "andi. $dst, $src1, $src2", IntGeneral, 337 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 338 isDOT; 339def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 340 "andis. $dst, $src1, $src2", IntGeneral, 341 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 342 isDOT; 343def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 344 "ori $dst, $src1, $src2", IntSimple, 345 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 346def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 347 "oris $dst, $src1, $src2", IntSimple, 348 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 349def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 350 "xori $dst, $src1, $src2", IntSimple, 351 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 352def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 353 "xoris $dst, $src1, $src2", IntSimple, 354 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 355 356def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 357 "add $rT, $rA, $rB", IntSimple, 358 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 359// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 360// initial-exec thread-local storage model. 361def ADD8TLS : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, tlsreg:$rB), 362 "add $rT, $rA, $rB@tls", IntSimple, 363 [(set G8RC:$rT, (add G8RC:$rA, tglobaltlsaddr:$rB))]>; 364 365let Defs = [CARRY] in { 366def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 367 "addc $rT, $rA, $rB", IntGeneral, 368 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 369 PPC970_DGroup_Cracked; 370def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 371 "addic $rD, $rA, $imm", IntGeneral, 372 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>; 373} 374def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, s16imm64:$imm), 375 "addi $rD, $rA, $imm", IntSimple, 376 [(set G8RC:$rD, (add G8RC_NOX0:$rA, immSExt16:$imm))]>; 377def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolLo64:$imm), 378 "addi $rD, $rA, $imm", IntSimple, 379 [(set G8RC:$rD, (add G8RC_NOX0:$rA, immSExt16:$imm))]>; 380def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolHi64:$imm), 381 "addis $rD, $rA, $imm", IntSimple, 382 [(set G8RC:$rD, (add G8RC_NOX0:$rA, 383 imm16ShiftedSExt:$imm))]>; 384 385let Defs = [CARRY] in { 386def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 387 "subfic $rD, $rA, $imm", IntGeneral, 388 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 389def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 390 "subfc $rT, $rA, $rB", IntGeneral, 391 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 392 PPC970_DGroup_Cracked; 393} 394def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 395 "subf $rT, $rA, $rB", IntGeneral, 396 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 397def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 398 "neg $rT, $rA", IntSimple, 399 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 400let Uses = [CARRY], Defs = [CARRY] in { 401def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 402 "adde $rT, $rA, $rB", IntGeneral, 403 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 404def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 405 "addme $rT, $rA", IntGeneral, 406 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>; 407def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 408 "addze $rT, $rA", IntGeneral, 409 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 410def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 411 "subfe $rT, $rA, $rB", IntGeneral, 412 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 413def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 414 "subfme $rT, $rA", IntGeneral, 415 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>; 416def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 417 "subfze $rT, $rA", IntGeneral, 418 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 419} 420 421 422def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 423 "mulhd $rT, $rA, $rB", IntMulHW, 424 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 425def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 426 "mulhdu $rT, $rA, $rB", IntMulHWU, 427 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 428 429def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 430 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 431def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 432 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 433def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 434 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 435def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 436 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 437 438def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 439 "sld $rA, $rS, $rB", IntRotateD, 440 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 441def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 442 "srd $rA, $rS, $rB", IntRotateD, 443 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 444let Defs = [CARRY] in { 445def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 446 "srad $rA, $rS, $rB", IntRotateD, 447 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 448} 449 450def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 451 "extsb $rA, $rS", IntSimple, 452 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 453def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 454 "extsh $rA, $rS", IntSimple, 455 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 456 457def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 458 "extsw $rA, $rS", IntSimple, 459 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 460/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 461def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 462 "extsw $rA, $rS", IntSimple, 463 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 464def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 465 "extsw $rA, $rS", IntSimple, 466 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 467 468let Defs = [CARRY] in { 469def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 470 "sradi $rA, $rS, $SH", IntRotateDI, 471 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 472} 473def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 474 "cntlzd $rA, $rS", IntGeneral, 475 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 476 477def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 478 "divd $rT, $rA, $rB", IntDivD, 479 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 480 PPC970_DGroup_First, PPC970_DGroup_Cracked; 481def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 482 "divdu $rT, $rA, $rB", IntDivD, 483 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 484 PPC970_DGroup_First, PPC970_DGroup_Cracked; 485def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 486 "mulld $rT, $rA, $rB", IntMulHD, 487 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 488 489 490let isCommutable = 1 in { 491def RLDIMI : MDForm_1<30, 3, 492 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 493 "rldimi $rA, $rS, $SH, $MB", IntRotateDI, 494 []>, isPPC64, RegConstraint<"$rSi = $rA">, 495 NoEncode<"$rSi">; 496} 497 498// Rotate instructions. 499def RLDCL : MDForm_1<30, 0, 500 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE), 501 "rldcl $rA, $rS, $rB, $MBE", IntRotateD, 502 []>, isPPC64; 503def RLDICL : MDForm_1<30, 0, 504 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE), 505 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI, 506 []>, isPPC64; 507def RLDICR : MDForm_1<30, 1, 508 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE), 509 "rldicr $rA, $rS, $SH, $MBE", IntRotateDI, 510 []>, isPPC64; 511 512def RLWINM8 : MForm_2<21, 513 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 514 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 515 []>; 516 517def ISEL8 : AForm_4<31, 15, 518 (outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB, pred:$cond), 519 "isel $rT, $rA, $rB, $cond", IntGeneral, 520 []>; 521} // End FXU Operations. 522 523 524//===----------------------------------------------------------------------===// 525// Load/Store instructions. 526// 527 528 529// Sign extending loads. 530let canFoldAsLoad = 1, PPC970_Unit = 2 in { 531def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 532 "lha $rD, $src", LdStLHA, 533 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 534 PPC970_DGroup_Cracked; 535def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 536 "lwa $rD, $src", LdStLWA, 537 [(set G8RC:$rD, 538 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 539 PPC970_DGroup_Cracked; 540def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 541 "lhax $rD, $src", LdStLHA, 542 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 543 PPC970_DGroup_Cracked; 544def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 545 "lwax $rD, $src", LdStLHA, 546 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 547 PPC970_DGroup_Cracked; 548 549// Update forms. 550let mayLoad = 1 in { 551def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 552 (ins memri:$addr), 553 "lhau $rD, $addr", LdStLHAU, 554 []>, RegConstraint<"$addr.reg = $ea_result">, 555 NoEncode<"$ea_result">; 556// NO LWAU! 557 558def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 559 (ins memrr:$addr), 560 "lhaux $rD, $addr", LdStLHAU, 561 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 562 NoEncode<"$ea_result">; 563def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 564 (ins memrr:$addr), 565 "lwaux $rD, $addr", LdStLHAU, 566 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 567 NoEncode<"$ea_result">, isPPC64; 568} 569} 570 571// Zero extending loads. 572let canFoldAsLoad = 1, PPC970_Unit = 2 in { 573def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 574 "lbz $rD, $src", LdStLoad, 575 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 576def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 577 "lhz $rD, $src", LdStLoad, 578 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 579def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 580 "lwz $rD, $src", LdStLoad, 581 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 582 583def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 584 "lbzx $rD, $src", LdStLoad, 585 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 586def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 587 "lhzx $rD, $src", LdStLoad, 588 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 589def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 590 "lwzx $rD, $src", LdStLoad, 591 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 592 593 594// Update forms. 595let mayLoad = 1 in { 596def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 597 "lbzu $rD, $addr", LdStLoadUpd, 598 []>, RegConstraint<"$addr.reg = $ea_result">, 599 NoEncode<"$ea_result">; 600def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 601 "lhzu $rD, $addr", LdStLoadUpd, 602 []>, RegConstraint<"$addr.reg = $ea_result">, 603 NoEncode<"$ea_result">; 604def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 605 "lwzu $rD, $addr", LdStLoadUpd, 606 []>, RegConstraint<"$addr.reg = $ea_result">, 607 NoEncode<"$ea_result">; 608 609def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 610 (ins memrr:$addr), 611 "lbzux $rD, $addr", LdStLoadUpd, 612 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 613 NoEncode<"$ea_result">; 614def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 615 (ins memrr:$addr), 616 "lhzux $rD, $addr", LdStLoadUpd, 617 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 618 NoEncode<"$ea_result">; 619def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 620 (ins memrr:$addr), 621 "lwzux $rD, $addr", LdStLoadUpd, 622 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 623 NoEncode<"$ea_result">; 624} 625} 626 627 628// Full 8-byte loads. 629let canFoldAsLoad = 1, PPC970_Unit = 2 in { 630def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 631 "ld $rD, $src", LdStLD, 632 [(set G8RC:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 633def LDrs : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrs:$src), 634 "ld $rD, $src", LdStLD, 635 []>, isPPC64; 636// The following three definitions are selected for small code model only. 637// Otherwise, we need to create two instructions to form a 32-bit offset, 638// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 639def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 640 "#LDtoc", 641 [(set G8RC:$rD, 642 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 643def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 644 "#LDtocJTI", 645 [(set G8RC:$rD, 646 (PPCtoc_entry tjumptable:$disp, G8RC:$reg))]>, isPPC64; 647def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 648 "#LDtocCPT", 649 [(set G8RC:$rD, 650 (PPCtoc_entry tconstpool:$disp, G8RC:$reg))]>, isPPC64; 651 652let hasSideEffects = 1 in { 653let RST = 2, DS = 2 in 654def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg), 655 "ld 2, 8($reg)", LdStLD, 656 [(PPCload_toc G8RC:$reg)]>, isPPC64; 657 658let RST = 2, DS = 10, RA = 1 in 659def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), 660 "ld 2, 40(1)", LdStLD, 661 [(PPCtoc_restore)]>, isPPC64; 662} 663def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 664 "ldx $rD, $src", LdStLD, 665 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 666 667let mayLoad = 1 in 668def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 669 "ldu $rD, $addr", LdStLDU, 670 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 671 NoEncode<"$ea_result">; 672 673def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 674 (ins memrr:$addr), 675 "ldux $rD, $addr", LdStLDU, 676 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 677 NoEncode<"$ea_result">, isPPC64; 678} 679 680def : Pat<(PPCload ixaddr:$src), 681 (LD ixaddr:$src)>; 682def : Pat<(PPCload xaddr:$src), 683 (LDX xaddr:$src)>; 684 685// Support for medium and large code model. 686def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp), 687 "#ADDIStocHA", 688 [(set G8RC:$rD, 689 (PPCaddisTocHA G8RC:$reg, tglobaladdr:$disp))]>, 690 isPPC64; 691def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 692 "#LDtocL", 693 [(set G8RC:$rD, 694 (PPCldTocL tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 695def ADDItocL: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp), 696 "#ADDItocL", 697 [(set G8RC:$rD, 698 (PPCaddiTocL G8RC:$reg, tglobaladdr:$disp))]>, isPPC64; 699 700// Support for thread-local storage. 701def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 702 "#ADDISgotTprelHA", 703 [(set G8RC:$rD, 704 (PPCaddisGotTprelHA G8RC:$reg, 705 tglobaltlsaddr:$disp))]>, 706 isPPC64; 707def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC:$reg), 708 "#LDgotTprelL", 709 [(set G8RC:$rD, 710 (PPCldGotTprelL tglobaltlsaddr:$disp, G8RC:$reg))]>, 711 isPPC64; 712def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 713 (ADD8TLS $in, tglobaltlsaddr:$g)>; 714def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 715 "#ADDIStlsgdHA", 716 [(set G8RC:$rD, 717 (PPCaddisTlsgdHA G8RC:$reg, tglobaltlsaddr:$disp))]>, 718 isPPC64; 719def ADDItlsgdL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp), 720 "#ADDItlsgdL", 721 [(set G8RC:$rD, 722 (PPCaddiTlsgdL G8RC:$reg, tglobaltlsaddr:$disp))]>, 723 isPPC64; 724def GETtlsADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym), 725 "#GETtlsADDR", 726 [(set G8RC:$rD, 727 (PPCgetTlsAddr G8RC:$reg, tglobaltlsaddr:$sym))]>, 728 isPPC64; 729def ADDIStlsldHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 730 "#ADDIStlsldHA", 731 [(set G8RC:$rD, 732 (PPCaddisTlsldHA G8RC:$reg, tglobaltlsaddr:$disp))]>, 733 isPPC64; 734def ADDItlsldL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp), 735 "#ADDItlsldL", 736 [(set G8RC:$rD, 737 (PPCaddiTlsldL G8RC:$reg, tglobaltlsaddr:$disp))]>, 738 isPPC64; 739def GETtlsldADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym), 740 "#GETtlsldADDR", 741 [(set G8RC:$rD, 742 (PPCgetTlsldAddr G8RC:$reg, tglobaltlsaddr:$sym))]>, 743 isPPC64; 744def ADDISdtprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 745 "#ADDISdtprelHA", 746 [(set G8RC:$rD, 747 (PPCaddisDtprelHA G8RC:$reg, 748 tglobaltlsaddr:$disp))]>, 749 isPPC64; 750def ADDIdtprelL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp), 751 "#ADDIdtprelL", 752 [(set G8RC:$rD, 753 (PPCaddiDtprelL G8RC:$reg, tglobaltlsaddr:$disp))]>, 754 isPPC64; 755 756let PPC970_Unit = 2 in { 757// Truncating stores. 758def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 759 "stb $rS, $src", LdStStore, 760 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 761def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 762 "sth $rS, $src", LdStStore, 763 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 764def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 765 "stw $rS, $src", LdStStore, 766 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 767def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 768 "stbx $rS, $dst", LdStStore, 769 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 770 PPC970_DGroup_Cracked; 771def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 772 "sthx $rS, $dst", LdStStore, 773 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 774 PPC970_DGroup_Cracked; 775def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 776 "stwx $rS, $dst", LdStStore, 777 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 778 PPC970_DGroup_Cracked; 779// Normal 8-byte stores. 780def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 781 "std $rS, $dst", LdStSTD, 782 [(aligned4store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 783def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 784 "stdx $rS, $dst", LdStSTD, 785 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 786 PPC970_DGroup_Cracked; 787// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 788def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 789 "std $rT, $dst", LdStSTD, 790 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 791def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 792 "stdx $rT, $dst", LdStSTD, 793 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 794 PPC970_DGroup_Cracked; 795} 796 797// Stores with Update (pre-inc). 798let PPC970_Unit = 2, mayStore = 1 in { 799def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst), 800 "stbu $rS, $dst", LdStStoreUpd, []>, 801 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 802def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst), 803 "sthu $rS, $dst", LdStStoreUpd, []>, 804 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 805def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst), 806 "stwu $rS, $dst", LdStStoreUpd, []>, 807 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 808def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrix:$dst), 809 "stdu $rS, $dst", LdStSTDU, []>, 810 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 811 isPPC64; 812 813def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst), 814 "stbux $rS, $dst", LdStStoreUpd, []>, 815 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 816 PPC970_DGroup_Cracked; 817def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst), 818 "sthux $rS, $dst", LdStStoreUpd, []>, 819 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 820 PPC970_DGroup_Cracked; 821def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst), 822 "stwux $rS, $dst", LdStStoreUpd, []>, 823 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 824 PPC970_DGroup_Cracked; 825def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst), 826 "stdux $rS, $dst", LdStSTDU, []>, 827 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 828 PPC970_DGroup_Cracked, isPPC64; 829} 830 831// Patterns to match the pre-inc stores. We can't put the patterns on 832// the instruction definitions directly as ISel wants the address base 833// and offset to be separate operands, not a single complex operand. 834def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 835 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 836def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 837 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 838def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 839 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 840def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 841 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 842 843def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 844 (STBUX8 $rS, $ptrreg, $ptroff)>; 845def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 846 (STHUX8 $rS, $ptrreg, $ptroff)>; 847def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 848 (STWUX8 $rS, $ptrreg, $ptroff)>; 849def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 850 (STDUX $rS, $ptrreg, $ptroff)>; 851 852 853//===----------------------------------------------------------------------===// 854// Floating point instructions. 855// 856 857 858let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations. 859def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 860 "fcfid $frD, $frB", FPGeneral, 861 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 862def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 863 "fctidz $frD, $frB", FPGeneral, 864 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 865} 866 867 868//===----------------------------------------------------------------------===// 869// Instruction Patterns 870// 871 872// Extensions and truncates to/from 32-bit regs. 873def : Pat<(i64 (zext i32:$in)), 874 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 875 0, 32)>; 876def : Pat<(i64 (anyext i32:$in)), 877 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 878def : Pat<(i32 (trunc i64:$in)), 879 (EXTRACT_SUBREG $in, sub_32)>; 880 881// Extending loads with i64 targets. 882def : Pat<(zextloadi1 iaddr:$src), 883 (LBZ8 iaddr:$src)>; 884def : Pat<(zextloadi1 xaddr:$src), 885 (LBZX8 xaddr:$src)>; 886def : Pat<(extloadi1 iaddr:$src), 887 (LBZ8 iaddr:$src)>; 888def : Pat<(extloadi1 xaddr:$src), 889 (LBZX8 xaddr:$src)>; 890def : Pat<(extloadi8 iaddr:$src), 891 (LBZ8 iaddr:$src)>; 892def : Pat<(extloadi8 xaddr:$src), 893 (LBZX8 xaddr:$src)>; 894def : Pat<(extloadi16 iaddr:$src), 895 (LHZ8 iaddr:$src)>; 896def : Pat<(extloadi16 xaddr:$src), 897 (LHZX8 xaddr:$src)>; 898def : Pat<(extloadi32 iaddr:$src), 899 (LWZ8 iaddr:$src)>; 900def : Pat<(extloadi32 xaddr:$src), 901 (LWZX8 xaddr:$src)>; 902 903// Standard shifts. These are represented separately from the real shifts above 904// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 905// amounts. 906def : Pat<(sra i64:$rS, i32:$rB), 907 (SRAD $rS, $rB)>; 908def : Pat<(srl i64:$rS, i32:$rB), 909 (SRD $rS, $rB)>; 910def : Pat<(shl i64:$rS, i32:$rB), 911 (SLD $rS, $rB)>; 912 913// SHL/SRL 914def : Pat<(shl i64:$in, (i32 imm:$imm)), 915 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 916def : Pat<(srl i64:$in, (i32 imm:$imm)), 917 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 918 919// ROTL 920def : Pat<(rotl i64:$in, i32:$sh), 921 (RLDCL $in, $sh, 0)>; 922def : Pat<(rotl i64:$in, (i32 imm:$imm)), 923 (RLDICL $in, imm:$imm, 0)>; 924 925// Hi and Lo for Darwin Global Addresses. 926def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 927def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 928def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 929def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 930def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 931def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 932def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 933def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 934def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 935 (ADDIS8 $in, tglobaltlsaddr:$g)>; 936def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 937 (ADDI8L $in, tglobaltlsaddr:$g)>; 938def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 939 (ADDIS8 $in, tglobaladdr:$g)>; 940def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 941 (ADDIS8 $in, tconstpool:$g)>; 942def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 943 (ADDIS8 $in, tjumptable:$g)>; 944def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 945 (ADDIS8 $in, tblockaddress:$g)>; 946 947// Patterns to match r+r indexed loads and stores for 948// addresses without at least 4-byte alignment. 949def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 950 (LWAX xoaddr:$src)>; 951def : Pat<(i64 (unaligned4load xoaddr:$src)), 952 (LDX xoaddr:$src)>; 953def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 954 (STDX $rS, xoaddr:$dst)>; 955 956