PPCInstr64Bit.td revision ade90c9f1d01f3401a5db183a33b5a6380476a35
1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22} 23def u16imm64 : Operand<i64> { 24 let PrintMethod = "printU16ImmOperand"; 25 let EncoderMethod = "getImm16Encoding"; 26 let ParserMatchClass = PPCU16ImmAsmOperand; 27} 28def s17imm64 : Operand<i64> { 29 // This operand type is used for addis/lis to allow the assembler parser 30 // to accept immediates in the range -65536..65535 for compatibility with 31 // the GNU assembler. The operand is treated as 16-bit otherwise. 32 let PrintMethod = "printS16ImmOperand"; 33 let EncoderMethod = "getImm16Encoding"; 34 let ParserMatchClass = PPCS17ImmAsmOperand; 35} 36def tocentry : Operand<iPTR> { 37 let MIOperandInfo = (ops i64imm:$imm); 38} 39def PPCTLSRegOperand : AsmOperandClass { 40 let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; 41 let RenderMethod = "addTLSRegOperands"; 42} 43def tlsreg : Operand<i64> { 44 let EncoderMethod = "getTLSRegEncoding"; 45 let ParserMatchClass = PPCTLSRegOperand; 46} 47def tlsgd : Operand<i64> {} 48def tlscall : Operand<i64> { 49 let PrintMethod = "printTLSCall"; 50 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 51 let EncoderMethod = "getTLSCallEncoding"; 52} 53 54//===----------------------------------------------------------------------===// 55// 64-bit transformation functions. 56// 57 58def SHL64 : SDNodeXForm<imm, [{ 59 // Transformation function: 63 - imm 60 return getI32Imm(63 - N->getZExtValue()); 61}]>; 62 63def SRL64 : SDNodeXForm<imm, [{ 64 // Transformation function: 64 - imm 65 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 66}]>; 67 68def HI32_48 : SDNodeXForm<imm, [{ 69 // Transformation function: shift the immediate value down into the low bits. 70 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 71}]>; 72 73def HI48_64 : SDNodeXForm<imm, [{ 74 // Transformation function: shift the immediate value down into the low bits. 75 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 76}]>; 77 78 79//===----------------------------------------------------------------------===// 80// Calls. 81// 82 83let Interpretation64Bit = 1 in { 84let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 85 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 86 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 87 Requires<[In64BitMode]>; 88 89 let isCodeGenOnly = 1 in 90 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 91 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>, 92 Requires<[In64BitMode]>; 93 } 94} 95 96let Defs = [LR8] in 97 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 98 PPC970_Unit_BRU; 99 100let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 101 let Defs = [CTR8], Uses = [CTR8] in { 102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 103 "bdz $dst">; 104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 105 "bdnz $dst">; 106 } 107 108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 110 "bdzlr", BrB, []>; 111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 112 "bdnzlr", BrB, []>; 113 } 114} 115 116 117 118let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 119 // Convenient aliases for call instructions 120 let Uses = [RM] in { 121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 122 "bl $func", BrB, []>; // See Pat patterns below. 123 124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 125 "bl $func", BrB, []>; 126 127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 128 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>; 129 } 130 let Uses = [RM], isCodeGenOnly = 1 in { 131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 132 (outs), (ins calltarget:$func), 133 "bl $func\n\tnop", BrB, []>; 134 135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 136 (outs), (ins tlscall:$func), 137 "bl $func\n\tnop", BrB, []>; 138 139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 140 (outs), (ins abscalltarget:$func), 141 "bla $func\n\tnop", BrB, 142 [(PPCcall_nop (i64 imm:$func))]>; 143 } 144 let Uses = [CTR8, RM] in { 145 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 146 "bctrl", BrB, [(PPCbctrl)]>, 147 Requires<[In64BitMode]>; 148 149 let isCodeGenOnly = 1 in 150 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 151 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>, 152 Requires<[In64BitMode]>; 153 } 154} 155} // Interpretation64Bit 156 157// Calls 158def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 159 (BL8 tglobaladdr:$dst)>; 160def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 161 (BL8_NOP tglobaladdr:$dst)>; 162 163def : Pat<(PPCcall (i64 texternalsym:$dst)), 164 (BL8 texternalsym:$dst)>; 165def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 166 (BL8_NOP texternalsym:$dst)>; 167 168// Atomic operations 169let usesCustomInserter = 1 in { 170 let Defs = [CR0] in { 171 def ATOMIC_LOAD_ADD_I64 : Pseudo< 172 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 173 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 174 def ATOMIC_LOAD_SUB_I64 : Pseudo< 175 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 176 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 177 def ATOMIC_LOAD_OR_I64 : Pseudo< 178 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 179 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 180 def ATOMIC_LOAD_XOR_I64 : Pseudo< 181 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 182 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 183 def ATOMIC_LOAD_AND_I64 : Pseudo< 184 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 185 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 186 def ATOMIC_LOAD_NAND_I64 : Pseudo< 187 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 188 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 189 190 def ATOMIC_CMP_SWAP_I64 : Pseudo< 191 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 192 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 193 194 def ATOMIC_SWAP_I64 : Pseudo< 195 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 196 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 197 } 198} 199 200// Instructions to support atomic operations 201def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 202 "ldarx $rD, $ptr", LdStLDARX, 203 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>; 204 205let Defs = [CR0] in 206def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 207 "stdcx. $rS, $dst", LdStSTDCX, 208 [(PPCstcx i64:$rS, xoaddr:$dst)]>, 209 isDOT; 210 211let Interpretation64Bit = 1 in { 212let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 213def TCRETURNdi8 :Pseudo< (outs), 214 (ins calltarget:$dst, i32imm:$offset), 215 "#TC_RETURNd8 $dst $offset", 216 []>; 217 218let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 219def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 220 "#TC_RETURNa8 $func $offset", 221 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 222 223let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 224def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 225 "#TC_RETURNr8 $dst $offset", 226 []>; 227 228let isCodeGenOnly = 1 in { 229 230let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 231 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 232def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 233 Requires<[In64BitMode]>; 234 235 236let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 237 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 238def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 239 "b $dst", BrB, 240 []>; 241 242 243let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 244 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 245def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 246 "ba $dst", BrB, 247 []>; 248 249} 250} // Interpretation64Bit 251 252def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 253 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 254 255def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 256 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 257 258def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 259 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 260 261 262// 64-bit CR instructions 263let Interpretation64Bit = 1 in { 264let neverHasSideEffects = 1 in { 265def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 266 "mtocrf $FXM, $ST", BrMCRX>, 267 PPC970_DGroup_First, PPC970_Unit_CRU; 268 269def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 270 "mtcrf $FXM, $rS", BrMCRX>, 271 PPC970_MicroCode, PPC970_Unit_CRU; 272 273let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking. 274def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 275 "mfocrf $rT, $FXM", SprMFCR>, 276 PPC970_DGroup_First, PPC970_Unit_CRU; 277 278def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 279 "mfcr $rT", SprMFCR>, 280 PPC970_MicroCode, PPC970_Unit_CRU; 281} // neverHasSideEffects = 1 282 283let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 284 let Defs = [CTR8] in 285 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 286 "#EH_SJLJ_SETJMP64", 287 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 288 Requires<[In64BitMode]>; 289 let isTerminator = 1 in 290 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 291 "#EH_SJLJ_LONGJMP64", 292 [(PPCeh_sjlj_longjmp addr:$buf)]>, 293 Requires<[In64BitMode]>; 294} 295 296//===----------------------------------------------------------------------===// 297// 64-bit SPR manipulation instrs. 298 299let Uses = [CTR8] in { 300def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 301 "mfctr $rT", SprMFSPR>, 302 PPC970_DGroup_First, PPC970_Unit_FXU; 303} 304let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 305def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 306 "mtctr $rS", SprMTSPR>, 307 PPC970_DGroup_First, PPC970_Unit_FXU; 308} 309let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in { 310let Pattern = [(int_ppc_mtctr i64:$rS)] in 311def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 312 "mtctr $rS", SprMTSPR>, 313 PPC970_DGroup_First, PPC970_Unit_FXU; 314} 315 316let isCodeGenOnly = 1, Pattern = [(set i64:$rT, readcyclecounter)] in 317def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 318 "mfspr $rT, 268", SprMFTB>, 319 PPC970_DGroup_First, PPC970_Unit_FXU; 320// Note that encoding mftb using mfspr is now the preferred form, 321// and has been since at least ISA v2.03. The mftb instruction has 322// now been phased out. Using mfspr, however, is known not to work on 323// the POWER3. 324 325let Defs = [X1], Uses = [X1] in 326def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 327 [(set i64:$result, 328 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 329 330let Defs = [LR8] in { 331def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 332 "mtlr $rS", SprMTSPR>, 333 PPC970_DGroup_First, PPC970_Unit_FXU; 334} 335let Uses = [LR8] in { 336def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 337 "mflr $rT", SprMFSPR>, 338 PPC970_DGroup_First, PPC970_Unit_FXU; 339} 340} // Interpretation64Bit 341 342//===----------------------------------------------------------------------===// 343// Fixed point instructions. 344// 345 346let PPC970_Unit = 1 in { // FXU Operations. 347let Interpretation64Bit = 1 in { 348let neverHasSideEffects = 1 in { 349 350let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 351def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 352 "li $rD, $imm", IntSimple, 353 [(set i64:$rD, imm64SExt16:$imm)]>; 354def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 355 "lis $rD, $imm", IntSimple, 356 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 357} 358 359// Logical ops. 360defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 361 "nand", "$rA, $rS, $rB", IntSimple, 362 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 363defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 364 "and", "$rA, $rS, $rB", IntSimple, 365 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 366defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 367 "andc", "$rA, $rS, $rB", IntSimple, 368 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 369defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 370 "or", "$rA, $rS, $rB", IntSimple, 371 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 372defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 373 "nor", "$rA, $rS, $rB", IntSimple, 374 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 375defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 376 "orc", "$rA, $rS, $rB", IntSimple, 377 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 378defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 379 "eqv", "$rA, $rS, $rB", IntSimple, 380 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 381defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 382 "xor", "$rA, $rS, $rB", IntSimple, 383 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 384 385// Logical ops with immediate. 386let Defs = [CR0] in { 387def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 388 "andi. $dst, $src1, $src2", IntGeneral, 389 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 390 isDOT; 391def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 392 "andis. $dst, $src1, $src2", IntGeneral, 393 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 394 isDOT; 395} 396def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 397 "ori $dst, $src1, $src2", IntSimple, 398 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 399def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 400 "oris $dst, $src1, $src2", IntSimple, 401 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 402def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 403 "xori $dst, $src1, $src2", IntSimple, 404 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 405def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 406 "xoris $dst, $src1, $src2", IntSimple, 407 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 408 409defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 410 "add", "$rT, $rA, $rB", IntSimple, 411 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 412// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 413// initial-exec thread-local storage model. 414def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 415 "add $rT, $rA, $rB", IntSimple, 416 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 417 418defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 419 "addc", "$rT, $rA, $rB", IntGeneral, 420 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 421 PPC970_DGroup_Cracked; 422let Defs = [CARRY] in 423def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 424 "addic $rD, $rA, $imm", IntGeneral, 425 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 426def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 427 "addi $rD, $rA, $imm", IntSimple, 428 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 429def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 430 "addis $rD, $rA, $imm", IntSimple, 431 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 432 433let Defs = [CARRY] in { 434def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 435 "subfic $rD, $rA, $imm", IntGeneral, 436 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 437defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 438 "subfc", "$rT, $rA, $rB", IntGeneral, 439 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 440 PPC970_DGroup_Cracked; 441} 442defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 443 "subf", "$rT, $rA, $rB", IntGeneral, 444 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 445defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 446 "neg", "$rT, $rA", IntSimple, 447 [(set i64:$rT, (ineg i64:$rA))]>; 448let Uses = [CARRY] in { 449defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 450 "adde", "$rT, $rA, $rB", IntGeneral, 451 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 452defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 453 "addme", "$rT, $rA", IntGeneral, 454 [(set i64:$rT, (adde i64:$rA, -1))]>; 455defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 456 "addze", "$rT, $rA", IntGeneral, 457 [(set i64:$rT, (adde i64:$rA, 0))]>; 458defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 459 "subfe", "$rT, $rA, $rB", IntGeneral, 460 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 461defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 462 "subfme", "$rT, $rA", IntGeneral, 463 [(set i64:$rT, (sube -1, i64:$rA))]>; 464defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 465 "subfze", "$rT, $rA", IntGeneral, 466 [(set i64:$rT, (sube 0, i64:$rA))]>; 467} 468 469 470defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 471 "mulhd", "$rT, $rA, $rB", IntMulHW, 472 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 473defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 474 "mulhdu", "$rT, $rA, $rB", IntMulHWU, 475 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 476} 477} // Interpretation64Bit 478 479let isCompare = 1, neverHasSideEffects = 1 in { 480 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 481 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 482 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 483 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 484 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm), 485 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 486 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2), 487 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 488} 489 490let neverHasSideEffects = 1 in { 491defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 492 "sld", "$rA, $rS, $rB", IntRotateD, 493 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 494defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 495 "srd", "$rA, $rS, $rB", IntRotateD, 496 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 497defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 498 "srad", "$rA, $rS, $rB", IntRotateD, 499 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 500 501let Interpretation64Bit = 1 in { 502defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 503 "extsb", "$rA, $rS", IntSimple, 504 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 505defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 506 "extsh", "$rA, $rS", IntSimple, 507 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 508} // Interpretation64Bit 509 510// For fast-isel: 511let isCodeGenOnly = 1 in { 512def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 513 "extsb $rA, $rS", IntSimple, []>, isPPC64; 514def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 515 "extsh $rA, $rS", IntSimple, []>, isPPC64; 516} // isCodeGenOnly for fast-isel 517 518defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 519 "extsw", "$rA, $rS", IntSimple, 520 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 521let Interpretation64Bit = 1 in 522defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 523 "extsw", "$rA, $rS", IntSimple, 524 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 525 526defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 527 "sradi", "$rA, $rS, $SH", IntRotateDI, 528 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 529defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 530 "cntlzd", "$rA, $rS", IntGeneral, 531 [(set i64:$rA, (ctlz i64:$rS))]>; 532def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 533 "popcntd $rA, $rS", IntGeneral, 534 [(set i64:$rA, (ctpop i64:$rS))]>; 535 536// popcntw also does a population count on the high 32 bits (storing the 537// results in the high 32-bits of the output). We'll ignore that here (which is 538// safe because we never separately use the high part of the 64-bit registers). 539def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 540 "popcntw $rA, $rS", IntGeneral, 541 [(set i32:$rA, (ctpop i32:$rS))]>; 542 543defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 544 "divd", "$rT, $rA, $rB", IntDivD, 545 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64, 546 PPC970_DGroup_First, PPC970_DGroup_Cracked; 547defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 548 "divdu", "$rT, $rA, $rB", IntDivD, 549 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64, 550 PPC970_DGroup_First, PPC970_DGroup_Cracked; 551defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 552 "mulld", "$rT, $rA, $rB", IntMulHD, 553 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 554def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 555 "mulli $rD, $rA, $imm", IntMulLI, 556 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 557} 558 559let neverHasSideEffects = 1 in { 560let isCommutable = 1 in { 561defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 562 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 563 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI, 564 []>, isPPC64, RegConstraint<"$rSi = $rA">, 565 NoEncode<"$rSi">; 566} 567 568// Rotate instructions. 569defm RLDCL : MDSForm_1r<30, 8, 570 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 571 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD, 572 []>, isPPC64; 573defm RLDCR : MDSForm_1r<30, 9, 574 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 575 "rldcr", "$rA, $rS, $rB, $MBE", IntRotateD, 576 []>, isPPC64; 577defm RLDICL : MDForm_1r<30, 0, 578 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 579 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI, 580 []>, isPPC64; 581// For fast-isel: 582let isCodeGenOnly = 1 in 583def RLDICL_32_64 : MDForm_1<30, 0, 584 (outs g8rc:$rA), 585 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 586 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI, 587 []>, isPPC64; 588// End fast-isel. 589defm RLDICR : MDForm_1r<30, 1, 590 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 591 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI, 592 []>, isPPC64; 593defm RLDIC : MDForm_1r<30, 2, 594 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 595 "rldic", "$rA, $rS, $SH, $MBE", IntRotateDI, 596 []>, isPPC64; 597 598let Interpretation64Bit = 1 in { 599defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 600 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 601 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral, 602 []>; 603 604let isSelect = 1 in 605def ISEL8 : AForm_4<31, 15, 606 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 607 "isel $rT, $rA, $rB, $cond", IntGeneral, 608 []>; 609} // Interpretation64Bit 610} // neverHasSideEffects = 1 611} // End FXU Operations. 612 613 614//===----------------------------------------------------------------------===// 615// Load/Store instructions. 616// 617 618 619// Sign extending loads. 620let canFoldAsLoad = 1, PPC970_Unit = 2 in { 621let Interpretation64Bit = 1 in 622def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 623 "lha $rD, $src", LdStLHA, 624 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 625 PPC970_DGroup_Cracked; 626def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 627 "lwa $rD, $src", LdStLWA, 628 [(set i64:$rD, 629 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 630 PPC970_DGroup_Cracked; 631let Interpretation64Bit = 1 in 632def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 633 "lhax $rD, $src", LdStLHA, 634 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 635 PPC970_DGroup_Cracked; 636def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 637 "lwax $rD, $src", LdStLHA, 638 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 639 PPC970_DGroup_Cracked; 640// For fast-isel: 641let isCodeGenOnly = 1, mayLoad = 1 in { 642def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 643 "lwa $rD, $src", LdStLWA, []>, isPPC64, 644 PPC970_DGroup_Cracked; 645def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src), 646 "lwax $rD, $src", LdStLHA, []>, isPPC64, 647 PPC970_DGroup_Cracked; 648} // end fast-isel isCodeGenOnly 649 650// Update forms. 651let mayLoad = 1, neverHasSideEffects = 1 in { 652let Interpretation64Bit = 1 in 653def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 654 (ins memri:$addr), 655 "lhau $rD, $addr", LdStLHAU, 656 []>, RegConstraint<"$addr.reg = $ea_result">, 657 NoEncode<"$ea_result">; 658// NO LWAU! 659 660let Interpretation64Bit = 1 in 661def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 662 (ins memrr:$addr), 663 "lhaux $rD, $addr", LdStLHAU, 664 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 665 NoEncode<"$ea_result">; 666def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 667 (ins memrr:$addr), 668 "lwaux $rD, $addr", LdStLHAU, 669 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 670 NoEncode<"$ea_result">, isPPC64; 671} 672} 673 674let Interpretation64Bit = 1 in { 675// Zero extending loads. 676let canFoldAsLoad = 1, PPC970_Unit = 2 in { 677def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 678 "lbz $rD, $src", LdStLoad, 679 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 680def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 681 "lhz $rD, $src", LdStLoad, 682 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 683def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 684 "lwz $rD, $src", LdStLoad, 685 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 686 687def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 688 "lbzx $rD, $src", LdStLoad, 689 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 690def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 691 "lhzx $rD, $src", LdStLoad, 692 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 693def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 694 "lwzx $rD, $src", LdStLoad, 695 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 696 697 698// Update forms. 699let mayLoad = 1, neverHasSideEffects = 1 in { 700def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 701 "lbzu $rD, $addr", LdStLoadUpd, 702 []>, RegConstraint<"$addr.reg = $ea_result">, 703 NoEncode<"$ea_result">; 704def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 705 "lhzu $rD, $addr", LdStLoadUpd, 706 []>, RegConstraint<"$addr.reg = $ea_result">, 707 NoEncode<"$ea_result">; 708def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 709 "lwzu $rD, $addr", LdStLoadUpd, 710 []>, RegConstraint<"$addr.reg = $ea_result">, 711 NoEncode<"$ea_result">; 712 713def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 714 (ins memrr:$addr), 715 "lbzux $rD, $addr", LdStLoadUpd, 716 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 717 NoEncode<"$ea_result">; 718def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 719 (ins memrr:$addr), 720 "lhzux $rD, $addr", LdStLoadUpd, 721 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 722 NoEncode<"$ea_result">; 723def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 724 (ins memrr:$addr), 725 "lwzux $rD, $addr", LdStLoadUpd, 726 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 727 NoEncode<"$ea_result">; 728} 729} 730} // Interpretation64Bit 731 732 733// Full 8-byte loads. 734let canFoldAsLoad = 1, PPC970_Unit = 2 in { 735def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 736 "ld $rD, $src", LdStLD, 737 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 738// The following three definitions are selected for small code model only. 739// Otherwise, we need to create two instructions to form a 32-bit offset, 740// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 741def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 742 "#LDtoc", 743 [(set i64:$rD, 744 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 745def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 746 "#LDtocJTI", 747 [(set i64:$rD, 748 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 749def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 750 "#LDtocCPT", 751 [(set i64:$rD, 752 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 753 754let hasSideEffects = 1, isCodeGenOnly = 1 in { 755let RST = 2, DS = 2 in 756def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg), 757 "ld 2, 8($reg)", LdStLD, 758 [(PPCload_toc i64:$reg)]>, isPPC64; 759 760let RST = 2, DS = 10, RA = 1 in 761def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), 762 "ld 2, 40(1)", LdStLD, 763 [(PPCtoc_restore)]>, isPPC64; 764} 765def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 766 "ldx $rD, $src", LdStLD, 767 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 768def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 769 "ldbrx $rD, $src", LdStLoad, 770 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 771 772let mayLoad = 1, neverHasSideEffects = 1 in { 773def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 774 "ldu $rD, $addr", LdStLDU, 775 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 776 NoEncode<"$ea_result">; 777 778def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 779 (ins memrr:$addr), 780 "ldux $rD, $addr", LdStLDU, 781 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 782 NoEncode<"$ea_result">, isPPC64; 783} 784} 785 786def : Pat<(PPCload ixaddr:$src), 787 (LD ixaddr:$src)>; 788def : Pat<(PPCload xaddr:$src), 789 (LDX xaddr:$src)>; 790 791// Support for medium and large code model. 792def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 793 "#ADDIStocHA", 794 [(set i64:$rD, 795 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>, 796 isPPC64; 797def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 798 "#LDtocL", 799 [(set i64:$rD, 800 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64; 801def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 802 "#ADDItocL", 803 [(set i64:$rD, 804 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64; 805 806// Support for thread-local storage. 807def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 808 "#ADDISgotTprelHA", 809 [(set i64:$rD, 810 (PPCaddisGotTprelHA i64:$reg, 811 tglobaltlsaddr:$disp))]>, 812 isPPC64; 813def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 814 "#LDgotTprelL", 815 [(set i64:$rD, 816 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 817 isPPC64; 818def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 819 (ADD8TLS $in, tglobaltlsaddr:$g)>; 820def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 821 "#ADDIStlsgdHA", 822 [(set i64:$rD, 823 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 824 isPPC64; 825def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 826 "#ADDItlsgdL", 827 [(set i64:$rD, 828 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 829 isPPC64; 830def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 831 "#GETtlsADDR", 832 [(set i64:$rD, 833 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 834 isPPC64; 835def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 836 "#ADDIStlsldHA", 837 [(set i64:$rD, 838 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 839 isPPC64; 840def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 841 "#ADDItlsldL", 842 [(set i64:$rD, 843 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 844 isPPC64; 845def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 846 "#GETtlsldADDR", 847 [(set i64:$rD, 848 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 849 isPPC64; 850def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 851 "#ADDISdtprelHA", 852 [(set i64:$rD, 853 (PPCaddisDtprelHA i64:$reg, 854 tglobaltlsaddr:$disp))]>, 855 isPPC64; 856def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 857 "#ADDIdtprelL", 858 [(set i64:$rD, 859 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 860 isPPC64; 861 862let PPC970_Unit = 2 in { 863let Interpretation64Bit = 1 in { 864// Truncating stores. 865def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 866 "stb $rS, $src", LdStStore, 867 [(truncstorei8 i64:$rS, iaddr:$src)]>; 868def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 869 "sth $rS, $src", LdStStore, 870 [(truncstorei16 i64:$rS, iaddr:$src)]>; 871def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 872 "stw $rS, $src", LdStStore, 873 [(truncstorei32 i64:$rS, iaddr:$src)]>; 874def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 875 "stbx $rS, $dst", LdStStore, 876 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 877 PPC970_DGroup_Cracked; 878def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 879 "sthx $rS, $dst", LdStStore, 880 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 881 PPC970_DGroup_Cracked; 882def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 883 "stwx $rS, $dst", LdStStore, 884 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 885 PPC970_DGroup_Cracked; 886} // Interpretation64Bit 887 888// Normal 8-byte stores. 889def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 890 "std $rS, $dst", LdStSTD, 891 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 892def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 893 "stdx $rS, $dst", LdStSTD, 894 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 895 PPC970_DGroup_Cracked; 896def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 897 "stdbrx $rS, $dst", LdStStore, 898 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 899 PPC970_DGroup_Cracked; 900} 901 902// Stores with Update (pre-inc). 903let PPC970_Unit = 2, mayStore = 1 in { 904let Interpretation64Bit = 1 in { 905def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 906 "stbu $rS, $dst", LdStStoreUpd, []>, 907 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 908def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 909 "sthu $rS, $dst", LdStStoreUpd, []>, 910 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 911def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 912 "stwu $rS, $dst", LdStStoreUpd, []>, 913 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 914def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 915 "stdu $rS, $dst", LdStSTDU, []>, 916 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 917 isPPC64; 918 919def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 920 "stbux $rS, $dst", LdStStoreUpd, []>, 921 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 922 PPC970_DGroup_Cracked; 923def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 924 "sthux $rS, $dst", LdStStoreUpd, []>, 925 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 926 PPC970_DGroup_Cracked; 927def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 928 "stwux $rS, $dst", LdStStoreUpd, []>, 929 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 930 PPC970_DGroup_Cracked; 931} // Interpretation64Bit 932 933def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 934 "stdux $rS, $dst", LdStSTDU, []>, 935 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 936 PPC970_DGroup_Cracked, isPPC64; 937} 938 939// Patterns to match the pre-inc stores. We can't put the patterns on 940// the instruction definitions directly as ISel wants the address base 941// and offset to be separate operands, not a single complex operand. 942def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 943 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 944def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 945 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 946def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 947 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 948def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 949 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 950 951def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 952 (STBUX8 $rS, $ptrreg, $ptroff)>; 953def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 954 (STHUX8 $rS, $ptrreg, $ptroff)>; 955def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 956 (STWUX8 $rS, $ptrreg, $ptroff)>; 957def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 958 (STDUX $rS, $ptrreg, $ptroff)>; 959 960 961//===----------------------------------------------------------------------===// 962// Floating point instructions. 963// 964 965 966let PPC970_Unit = 3, neverHasSideEffects = 1, 967 Uses = [RM] in { // FPU Operations. 968defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 969 "fcfid", "$frD, $frB", FPGeneral, 970 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 971defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 972 "fctid", "$frD, $frB", FPGeneral, 973 []>, isPPC64; 974defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 975 "fctidz", "$frD, $frB", FPGeneral, 976 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 977 978defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 979 "fcfidu", "$frD, $frB", FPGeneral, 980 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 981defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 982 "fcfids", "$frD, $frB", FPGeneral, 983 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 984defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 985 "fcfidus", "$frD, $frB", FPGeneral, 986 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 987defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 988 "fctiduz", "$frD, $frB", FPGeneral, 989 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 990defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 991 "fctiwuz", "$frD, $frB", FPGeneral, 992 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 993} 994 995 996//===----------------------------------------------------------------------===// 997// Instruction Patterns 998// 999 1000// Extensions and truncates to/from 32-bit regs. 1001def : Pat<(i64 (zext i32:$in)), 1002 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1003 0, 32)>; 1004def : Pat<(i64 (anyext i32:$in)), 1005 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1006def : Pat<(i32 (trunc i64:$in)), 1007 (EXTRACT_SUBREG $in, sub_32)>; 1008 1009// Extending loads with i64 targets. 1010def : Pat<(zextloadi1 iaddr:$src), 1011 (LBZ8 iaddr:$src)>; 1012def : Pat<(zextloadi1 xaddr:$src), 1013 (LBZX8 xaddr:$src)>; 1014def : Pat<(extloadi1 iaddr:$src), 1015 (LBZ8 iaddr:$src)>; 1016def : Pat<(extloadi1 xaddr:$src), 1017 (LBZX8 xaddr:$src)>; 1018def : Pat<(extloadi8 iaddr:$src), 1019 (LBZ8 iaddr:$src)>; 1020def : Pat<(extloadi8 xaddr:$src), 1021 (LBZX8 xaddr:$src)>; 1022def : Pat<(extloadi16 iaddr:$src), 1023 (LHZ8 iaddr:$src)>; 1024def : Pat<(extloadi16 xaddr:$src), 1025 (LHZX8 xaddr:$src)>; 1026def : Pat<(extloadi32 iaddr:$src), 1027 (LWZ8 iaddr:$src)>; 1028def : Pat<(extloadi32 xaddr:$src), 1029 (LWZX8 xaddr:$src)>; 1030 1031// Standard shifts. These are represented separately from the real shifts above 1032// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1033// amounts. 1034def : Pat<(sra i64:$rS, i32:$rB), 1035 (SRAD $rS, $rB)>; 1036def : Pat<(srl i64:$rS, i32:$rB), 1037 (SRD $rS, $rB)>; 1038def : Pat<(shl i64:$rS, i32:$rB), 1039 (SLD $rS, $rB)>; 1040 1041// SHL/SRL 1042def : Pat<(shl i64:$in, (i32 imm:$imm)), 1043 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1044def : Pat<(srl i64:$in, (i32 imm:$imm)), 1045 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1046 1047// ROTL 1048def : Pat<(rotl i64:$in, i32:$sh), 1049 (RLDCL $in, $sh, 0)>; 1050def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1051 (RLDICL $in, imm:$imm, 0)>; 1052 1053// Hi and Lo for Darwin Global Addresses. 1054def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1055def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1056def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1057def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1058def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1059def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1060def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1061def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1062def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1063 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1064def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1065 (ADDI8 $in, tglobaltlsaddr:$g)>; 1066def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1067 (ADDIS8 $in, tglobaladdr:$g)>; 1068def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1069 (ADDIS8 $in, tconstpool:$g)>; 1070def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1071 (ADDIS8 $in, tjumptable:$g)>; 1072def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1073 (ADDIS8 $in, tblockaddress:$g)>; 1074 1075// Patterns to match r+r indexed loads and stores for 1076// addresses without at least 4-byte alignment. 1077def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1078 (LWAX xoaddr:$src)>; 1079def : Pat<(i64 (unaligned4load xoaddr:$src)), 1080 (LDX xoaddr:$src)>; 1081def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1082 (STDX $rS, xoaddr:$dst)>; 1083 1084