PPCInstr64Bit.td revision bdab93a2ef5d9574bb4e322e020849f9bc9c90d7
1//===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20} 21def u16imm64 : Operand<i64> { 22 let PrintMethod = "printU16ImmOperand"; 23} 24def symbolHi64 : Operand<i64> { 25 let PrintMethod = "printSymbolHi"; 26} 27def symbolLo64 : Operand<i64> { 28 let PrintMethod = "printSymbolLo"; 29} 30 31//===----------------------------------------------------------------------===// 32// 64-bit transformation functions. 33// 34 35def SHL64 : SDNodeXForm<imm, [{ 36 // Transformation function: 63 - imm 37 return getI32Imm(63 - N->getValue()); 38}]>; 39 40def SRL64 : SDNodeXForm<imm, [{ 41 // Transformation function: 64 - imm 42 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0); 43}]>; 44 45def HI32_48 : SDNodeXForm<imm, [{ 46 // Transformation function: shift the immediate value down into the low bits. 47 return getI32Imm((unsigned short)(N->getValue() >> 32)); 48}]>; 49 50def HI48_64 : SDNodeXForm<imm, [{ 51 // Transformation function: shift the immediate value down into the low bits. 52 return getI32Imm((unsigned short)(N->getValue() >> 48)); 53}]>; 54 55 56//===----------------------------------------------------------------------===// 57// Calls. 58// 59 60let Defs = [LR8] in 61 def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>, 62 PPC970_Unit_BRU; 63 64// Macho ABI Calls. 65let isCall = 1, PPC970_Unit = 7, 66 // All calls clobber the PPC64 non-callee saved registers. 67 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12, 68 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 69 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 70 LR8,CTR8, 71 CR0,CR1,CR5,CR6,CR7] in { 72 // Convenient aliases for call instructions 73 def BL8_Macho : IForm<18, 0, 1, 74 (outs), (ins calltarget:$func, variable_ops), 75 "bl $func", BrB, []>; // See Pat patterns below. 76 def BLA8_Macho : IForm<18, 1, 1, 77 (outs), (ins aaddr:$func, variable_ops), 78 "bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>; 79 def BCTRL8_Macho : XLForm_2_ext<19, 528, 20, 0, 1, 80 (outs), (ins variable_ops), 81 "bctrl", BrB, 82 [(PPCbctrl_Macho)]>, Requires<[In64BitMode]>; 83} 84 85// ELF 64 ABI Calls = Macho ABI Calls 86// Used to define BL8_ELF and BLA8_ELF 87let isCall = 1, PPC970_Unit = 7, 88 // All calls clobber the PPC64 non-callee saved registers. 89 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12, 90 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 91 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 92 LR8,CTR8, 93 CR0,CR1,CR5,CR6,CR7] in { 94 // Convenient aliases for call instructions 95 def BL8_ELF : IForm<18, 0, 1, 96 (outs), (ins calltarget:$func, variable_ops), 97 "bl $func", BrB, []>; // See Pat patterns below. 98 def BLA8_ELF : IForm<18, 1, 1, 99 (outs), (ins aaddr:$func, variable_ops), 100 "bla $func", BrB, [(PPCcall_ELF (i64 imm:$func))]>; 101 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 102 (outs), (ins variable_ops), 103 "bctrl", BrB, 104 [(PPCbctrl_ELF)]>, Requires<[In64BitMode]>; 105} 106 107 108// Calls 109def : Pat<(PPCcall_Macho (i64 tglobaladdr:$dst)), 110 (BL8_Macho tglobaladdr:$dst)>; 111def : Pat<(PPCcall_Macho (i64 texternalsym:$dst)), 112 (BL8_Macho texternalsym:$dst)>; 113 114def : Pat<(PPCcall_ELF (i64 tglobaladdr:$dst)), 115 (BL8_ELF tglobaladdr:$dst)>; 116def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)), 117 (BL8_ELF texternalsym:$dst)>; 118 119// Atomic operations 120let usesCustomDAGSchedInserter = 1 in { 121 let Uses = [CR0] in { 122 def ATOMIC_LOAD_ADD_I64 : Pseudo< 123 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 124 "${:comment} ATOMIC_LOAD_ADD_I64 PSEUDO!", 125 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 126 def ATOMIC_LOAD_SUB_I64 : Pseudo< 127 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 128 "${:comment} ATOMIC_LOAD_SUB_I64 PSEUDO!", 129 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 130 def ATOMIC_LOAD_OR_I64 : Pseudo< 131 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 132 "${:comment} ATOMIC_LOAD_OR_I64 PSEUDO!", 133 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 134 def ATOMIC_LOAD_XOR_I64 : Pseudo< 135 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 136 "${:comment} ATOMIC_LOAD_XOR_I64 PSEUDO!", 137 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 138 def ATOMIC_LOAD_AND_I64 : Pseudo< 139 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 140 "${:comment} ATOMIC_LOAD_AND_I64 PSEUDO!", 141 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 142 def ATOMIC_LOAD_NAND_I64 : Pseudo< 143 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 144 "${:comment} ATOMIC_LOAD_NAND_I64 PSEUDO!", 145 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 146 147 def ATOMIC_CMP_SWAP_I64 : Pseudo< 148 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), 149 "${:comment} ATOMIC_CMP_SWAP_I64 PSEUDO!", 150 [(set G8RC:$dst, 151 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 152 153 def ATOMIC_SWAP_I64 : Pseudo< 154 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), 155 "${:comment} ATOMIC_SWAP_I64 PSEUDO!", 156 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 157 } 158} 159 160// Instructions to support atomic operations 161def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 162 "ldarx $rD, $ptr", LdStLDARX, 163 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 164 165let Defs = [CR0] in 166def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 167 "stdcx. $rS, $dst", LdStSTDCX, 168 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 169 isDOT; 170 171let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in 172def TCRETURNdi8 :Pseudo< (outs), 173 (ins calltarget:$dst, i32imm:$offset, variable_ops), 174 "#TC_RETURNd8 $dst $offset", 175 []>; 176 177let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in 178def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), 179 "#TC_RETURNa8 $func $offset", 180 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 181 182let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in 183def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops), 184 "#TC_RETURNr8 $dst $offset", 185 []>; 186 187 188let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 189 isIndirectBranch = 1, isCall = 1, isReturn = 1 in 190def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 191 Requires<[In64BitMode]>; 192 193 194 195let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 196 isBarrier = 1, isCall = 1, isReturn = 1 in 197def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 198 "b $dst", BrB, 199 []>; 200 201 202let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 203 isBarrier = 1, isCall = 1, isReturn = 1 in 204def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 205 "ba $dst", BrB, 206 []>; 207 208def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 209 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 210 211def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 212 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 213 214def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 215 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 216 217 218//===----------------------------------------------------------------------===// 219// 64-bit SPR manipulation instrs. 220 221def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 222 "mfctr $rT", SprMFSPR>, 223 PPC970_DGroup_First, PPC970_Unit_FXU; 224let Pattern = [(PPCmtctr G8RC:$rS)] in { 225def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 226 "mtctr $rS", SprMTSPR>, 227 PPC970_DGroup_First, PPC970_Unit_FXU; 228} 229 230let Defs = [X1], Uses = [X1] in 231def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi), 232 "${:comment} DYNALLOC8 $result, $negsize, $fpsi", 233 [(set G8RC:$result, 234 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 235 236def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 237 "mtlr $rS", SprMTSPR>, 238 PPC970_DGroup_First, PPC970_Unit_FXU; 239def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 240 "mflr $rT", SprMFSPR>, 241 PPC970_DGroup_First, PPC970_Unit_FXU; 242 243 244//===----------------------------------------------------------------------===// 245// Fixed point instructions. 246// 247 248let PPC970_Unit = 1 in { // FXU Operations. 249 250// Copies, extends, truncates. 251def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB), 252 "or $rA, $rS, $rB", IntGeneral, 253 []>; 254def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB), 255 "or $rA, $rS, $rB", IntGeneral, 256 []>; 257 258def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 259 "li $rD, $imm", IntGeneral, 260 [(set G8RC:$rD, immSExt16:$imm)]>; 261def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 262 "lis $rD, $imm", IntGeneral, 263 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 264 265// Logical ops. 266def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 267 "nand $rA, $rS, $rB", IntGeneral, 268 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 269def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 270 "and $rA, $rS, $rB", IntGeneral, 271 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 272def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 273 "andc $rA, $rS, $rB", IntGeneral, 274 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 275def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 276 "or $rA, $rS, $rB", IntGeneral, 277 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 278def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 279 "nor $rA, $rS, $rB", IntGeneral, 280 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 281def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 282 "orc $rA, $rS, $rB", IntGeneral, 283 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 284def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 285 "eqv $rA, $rS, $rB", IntGeneral, 286 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 287def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 288 "xor $rA, $rS, $rB", IntGeneral, 289 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 290 291// Logical ops with immediate. 292def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 293 "andi. $dst, $src1, $src2", IntGeneral, 294 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 295 isDOT; 296def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 297 "andis. $dst, $src1, $src2", IntGeneral, 298 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 299 isDOT; 300def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 301 "ori $dst, $src1, $src2", IntGeneral, 302 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 303def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 304 "oris $dst, $src1, $src2", IntGeneral, 305 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 306def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 307 "xori $dst, $src1, $src2", IntGeneral, 308 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 309def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 310 "xoris $dst, $src1, $src2", IntGeneral, 311 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 312 313def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 314 "add $rT, $rA, $rB", IntGeneral, 315 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 316 317def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 318 "addc $rT, $rA, $rB", IntGeneral, 319 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 320 PPC970_DGroup_Cracked; 321def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 322 "adde $rT, $rA, $rB", IntGeneral, 323 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 324 325def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 326 "addi $rD, $rA, $imm", IntGeneral, 327 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 328def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), 329 "addis $rD, $rA, $imm", IntGeneral, 330 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 331 332def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 333 "subfic $rD, $rA, $imm", IntGeneral, 334 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 335def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 336 "subf $rT, $rA, $rB", IntGeneral, 337 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 338def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 339 "subfc $rT, $rA, $rB", IntGeneral, 340 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 341 PPC970_DGroup_Cracked; 342 343def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 344 "subfe $rT, $rA, $rB", IntGeneral, 345 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 346def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 347 "addme $rT, $rA", IntGeneral, 348 [(set G8RC:$rT, (adde G8RC:$rA, immAllOnes))]>; 349def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 350 "addze $rT, $rA", IntGeneral, 351 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 352def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 353 "neg $rT, $rA", IntGeneral, 354 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 355def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 356 "subfme $rT, $rA", IntGeneral, 357 [(set G8RC:$rT, (sube immAllOnes, G8RC:$rA))]>; 358def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 359 "subfze $rT, $rA", IntGeneral, 360 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 361 362 363 364def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 365 "mulhd $rT, $rA, $rB", IntMulHW, 366 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 367def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 368 "mulhdu $rT, $rA, $rB", IntMulHWU, 369 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 370 371def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 372 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 373def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 374 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 375def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 376 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 377def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 378 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 379 380def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 381 "sld $rA, $rS, $rB", IntRotateD, 382 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 383def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 384 "srd $rA, $rS, $rB", IntRotateD, 385 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 386def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 387 "srad $rA, $rS, $rB", IntRotateD, 388 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 389 390def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 391 "extsb $rA, $rS", IntGeneral, 392 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 393def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 394 "extsh $rA, $rS", IntGeneral, 395 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 396 397def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 398 "extsw $rA, $rS", IntGeneral, 399 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 400/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 401def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 402 "extsw $rA, $rS", IntGeneral, 403 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 404def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 405 "extsw $rA, $rS", IntGeneral, 406 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 407 408def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 409 "sradi $rA, $rS, $SH", IntRotateD, 410 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 411def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 412 "cntlzd $rA, $rS", IntGeneral, 413 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 414 415def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 416 "divd $rT, $rA, $rB", IntDivD, 417 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 418 PPC970_DGroup_First, PPC970_DGroup_Cracked; 419def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 420 "divdu $rT, $rA, $rB", IntDivD, 421 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 422 PPC970_DGroup_First, PPC970_DGroup_Cracked; 423def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 424 "mulld $rT, $rA, $rB", IntMulHD, 425 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 426 427 428let isCommutable = 1 in { 429def RLDIMI : MDForm_1<30, 3, 430 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 431 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 432 []>, isPPC64, RegConstraint<"$rSi = $rA">, 433 NoEncode<"$rSi">; 434} 435 436// Rotate instructions. 437def RLDCL : MDForm_1<30, 0, 438 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB), 439 "rldcl $rA, $rS, $rB, $MB", IntRotateD, 440 []>, isPPC64; 441def RLDICL : MDForm_1<30, 0, 442 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB), 443 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 444 []>, isPPC64; 445def RLDICR : MDForm_1<30, 1, 446 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME), 447 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 448 []>, isPPC64; 449} // End FXU Operations. 450 451 452//===----------------------------------------------------------------------===// 453// Load/Store instructions. 454// 455 456 457// Sign extending loads. 458let isSimpleLoad = 1, PPC970_Unit = 2 in { 459def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 460 "lha $rD, $src", LdStLHA, 461 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 462 PPC970_DGroup_Cracked; 463def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 464 "lwa $rD, $src", LdStLWA, 465 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, 466 PPC970_DGroup_Cracked; 467def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 468 "lhax $rD, $src", LdStLHA, 469 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 470 PPC970_DGroup_Cracked; 471def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 472 "lwax $rD, $src", LdStLHA, 473 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 474 PPC970_DGroup_Cracked; 475 476// Update forms. 477def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, 478 ptr_rc:$rA), 479 "lhau $rD, $disp($rA)", LdStGeneral, 480 []>, RegConstraint<"$rA = $ea_result">, 481 NoEncode<"$ea_result">; 482// NO LWAU! 483 484} 485 486// Zero extending loads. 487let isSimpleLoad = 1, PPC970_Unit = 2 in { 488def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 489 "lbz $rD, $src", LdStGeneral, 490 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 491def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 492 "lhz $rD, $src", LdStGeneral, 493 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 494def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 495 "lwz $rD, $src", LdStGeneral, 496 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 497 498def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 499 "lbzx $rD, $src", LdStGeneral, 500 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 501def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 502 "lhzx $rD, $src", LdStGeneral, 503 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 504def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 505 "lwzx $rD, $src", LdStGeneral, 506 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 507 508 509// Update forms. 510def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 511 "lbzu $rD, $addr", LdStGeneral, 512 []>, RegConstraint<"$addr.reg = $ea_result">, 513 NoEncode<"$ea_result">; 514def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 515 "lhzu $rD, $addr", LdStGeneral, 516 []>, RegConstraint<"$addr.reg = $ea_result">, 517 NoEncode<"$ea_result">; 518def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 519 "lwzu $rD, $addr", LdStGeneral, 520 []>, RegConstraint<"$addr.reg = $ea_result">, 521 NoEncode<"$ea_result">; 522} 523 524 525// Full 8-byte loads. 526let isSimpleLoad = 1, PPC970_Unit = 2 in { 527def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 528 "ld $rD, $src", LdStLD, 529 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; 530def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 531 "ldx $rD, $src", LdStLD, 532 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 533 534def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), 535 "ldu $rD, $addr", LdStLD, 536 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 537 NoEncode<"$ea_result">; 538 539} 540 541let PPC970_Unit = 2 in { 542// Truncating stores. 543def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 544 "stb $rS, $src", LdStGeneral, 545 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 546def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 547 "sth $rS, $src", LdStGeneral, 548 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 549def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 550 "stw $rS, $src", LdStGeneral, 551 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 552def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 553 "stbx $rS, $dst", LdStGeneral, 554 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 555 PPC970_DGroup_Cracked; 556def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 557 "sthx $rS, $dst", LdStGeneral, 558 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 559 PPC970_DGroup_Cracked; 560def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 561 "stwx $rS, $dst", LdStGeneral, 562 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 563 PPC970_DGroup_Cracked; 564// Normal 8-byte stores. 565def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 566 "std $rS, $dst", LdStSTD, 567 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 568def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 569 "stdx $rS, $dst", LdStSTD, 570 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 571 PPC970_DGroup_Cracked; 572} 573 574let PPC970_Unit = 2 in { 575 576def STBU8 : DForm_1<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 577 symbolLo:$ptroff, ptr_rc:$ptrreg), 578 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 579 [(set ptr_rc:$ea_res, 580 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, 581 iaddroff:$ptroff))]>, 582 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 583def STHU8 : DForm_1<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 584 symbolLo:$ptroff, ptr_rc:$ptrreg), 585 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 586 [(set ptr_rc:$ea_res, 587 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, 588 iaddroff:$ptroff))]>, 589 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 590def STWU8 : DForm_1<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 591 symbolLo:$ptroff, ptr_rc:$ptrreg), 592 "stwu $rS, $ptroff($ptrreg)", LdStGeneral, 593 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, 594 iaddroff:$ptroff))]>, 595 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 596 597 598def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 599 s16immX4:$ptroff, ptr_rc:$ptrreg), 600 "stdu $rS, $ptroff($ptrreg)", LdStSTD, 601 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, 602 iaddroff:$ptroff))]>, 603 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">, 604 isPPC64; 605 606let mayStore = 1 in 607def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst), 608 "stdux $rS, $dst", LdStSTD, 609 []>, isPPC64; 610 611// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 612def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 613 "std $rT, $dst", LdStSTD, 614 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 615def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 616 "stdx $rT, $dst", LdStSTD, 617 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 618 PPC970_DGroup_Cracked; 619} 620 621 622 623//===----------------------------------------------------------------------===// 624// Floating point instructions. 625// 626 627 628let PPC970_Unit = 3 in { // FPU Operations. 629def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 630 "fcfid $frD, $frB", FPGeneral, 631 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 632def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 633 "fctidz $frD, $frB", FPGeneral, 634 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 635} 636 637 638//===----------------------------------------------------------------------===// 639// Instruction Patterns 640// 641 642// Extensions and truncates to/from 32-bit regs. 643def : Pat<(i64 (zext GPRC:$in)), 644 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; 645def : Pat<(i64 (anyext GPRC:$in)), 646 (OR4To8 GPRC:$in, GPRC:$in)>; 647def : Pat<(i32 (trunc G8RC:$in)), 648 (OR8To4 G8RC:$in, G8RC:$in)>; 649 650// Extending loads with i64 targets. 651def : Pat<(zextloadi1 iaddr:$src), 652 (LBZ8 iaddr:$src)>; 653def : Pat<(zextloadi1 xaddr:$src), 654 (LBZX8 xaddr:$src)>; 655def : Pat<(extloadi1 iaddr:$src), 656 (LBZ8 iaddr:$src)>; 657def : Pat<(extloadi1 xaddr:$src), 658 (LBZX8 xaddr:$src)>; 659def : Pat<(extloadi8 iaddr:$src), 660 (LBZ8 iaddr:$src)>; 661def : Pat<(extloadi8 xaddr:$src), 662 (LBZX8 xaddr:$src)>; 663def : Pat<(extloadi16 iaddr:$src), 664 (LHZ8 iaddr:$src)>; 665def : Pat<(extloadi16 xaddr:$src), 666 (LHZX8 xaddr:$src)>; 667def : Pat<(extloadi32 iaddr:$src), 668 (LWZ8 iaddr:$src)>; 669def : Pat<(extloadi32 xaddr:$src), 670 (LWZX8 xaddr:$src)>; 671 672// Standard shifts. These are represented separately from the real shifts above 673// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 674// amounts. 675def : Pat<(sra G8RC:$rS, GPRC:$rB), 676 (SRAD G8RC:$rS, GPRC:$rB)>; 677def : Pat<(srl G8RC:$rS, GPRC:$rB), 678 (SRD G8RC:$rS, GPRC:$rB)>; 679def : Pat<(shl G8RC:$rS, GPRC:$rB), 680 (SLD G8RC:$rS, GPRC:$rB)>; 681 682// SHL/SRL 683def : Pat<(shl G8RC:$in, (i32 imm:$imm)), 684 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 685def : Pat<(srl G8RC:$in, (i32 imm:$imm)), 686 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 687 688// ROTL 689def : Pat<(rotl G8RC:$in, GPRC:$sh), 690 (RLDCL G8RC:$in, GPRC:$sh, 0)>; 691def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), 692 (RLDICL G8RC:$in, imm:$imm, 0)>; 693 694// Hi and Lo for Darwin Global Addresses. 695def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 696def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 697def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 698def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 699def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 700def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 701def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 702 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 703def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 704 (ADDIS8 G8RC:$in, tconstpool:$g)>; 705def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 706 (ADDIS8 G8RC:$in, tjumptable:$g)>; 707