PPCInstrAltivec.td revision 6b9d52eefd3e7d57618c0b7e84f0297298a5a65f
1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Altivec extension to the PowerPC instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Altivec transformation functions and pattern fragments. 16// 17 18// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 19// of that type. 20def vnot_ppc : PatFrag<(ops node:$in), 21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 22 23def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 24 (vector_shuffle node:$lhs, node:$rhs), [{ 25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 26}]>; 27def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 28 (vector_shuffle node:$lhs, node:$rhs), [{ 29 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 30}]>; 31def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 32 (vector_shuffle node:$lhs, node:$rhs), [{ 33 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 34}]>; 35def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 36 (vector_shuffle node:$lhs, node:$rhs), [{ 37 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 38}]>; 39 40 41def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 42 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 43 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 44}]>; 45def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 47 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 48}]>; 49def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 50 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 51 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 52}]>; 53def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 54 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 55 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 56}]>; 57def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 58 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 59 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 60}]>; 61def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 62 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 63 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 64}]>; 65 66 67def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 69 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 70}]>; 71def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 72 (vector_shuffle node:$lhs, node:$rhs), [{ 73 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 74}]>; 75def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 76 (vector_shuffle node:$lhs, node:$rhs), [{ 77 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 78}]>; 79def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 80 (vector_shuffle node:$lhs, node:$rhs), [{ 81 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 82}]>; 83def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 84 (vector_shuffle node:$lhs, node:$rhs), [{ 85 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 86}]>; 87def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 88 (vector_shuffle node:$lhs, node:$rhs), [{ 89 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 90}]>; 91 92 93def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 94 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false)); 95}]>; 96def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 97 (vector_shuffle node:$lhs, node:$rhs), [{ 98 return PPC::isVSLDOIShuffleMask(N, false) != -1; 99}], VSLDOI_get_imm>; 100 101 102/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 103/// vector_shuffle(X,undef,mask) by the dag combiner. 104def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 105 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true)); 106}]>; 107def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 108 (vector_shuffle node:$lhs, node:$rhs), [{ 109 return PPC::isVSLDOIShuffleMask(N, true) != -1; 110}], VSLDOI_unary_get_imm>; 111 112 113// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 114def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 115 return getI32Imm(PPC::getVSPLTImmediate(N, 1)); 116}]>; 117def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 118 (vector_shuffle node:$lhs, node:$rhs), [{ 119 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 120}], VSPLTB_get_imm>; 121def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 122 return getI32Imm(PPC::getVSPLTImmediate(N, 2)); 123}]>; 124def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 125 (vector_shuffle node:$lhs, node:$rhs), [{ 126 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 127}], VSPLTH_get_imm>; 128def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 129 return getI32Imm(PPC::getVSPLTImmediate(N, 4)); 130}]>; 131def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 132 (vector_shuffle node:$lhs, node:$rhs), [{ 133 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 134}], VSPLTW_get_imm>; 135 136 137// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 138def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 139 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 140}]>; 141def vecspltisb : PatLeaf<(build_vector), [{ 142 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0; 143}], VSPLTISB_get_imm>; 144 145// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 146def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 147 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 148}]>; 149def vecspltish : PatLeaf<(build_vector), [{ 150 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0; 151}], VSPLTISH_get_imm>; 152 153// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 154def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 155 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 156}]>; 157def vecspltisw : PatLeaf<(build_vector), [{ 158 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0; 159}], VSPLTISW_get_imm>; 160 161//===----------------------------------------------------------------------===// 162// Helpers for defining instructions that directly correspond to intrinsics. 163 164// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 165class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 166 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC), 167 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 168 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 169 170// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 171// inputs doesn't match the type of the output. 172class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 173 ValueType InTy> 174 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC), 175 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 176 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 177 178// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 179// input types and an output type. 180class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 181 ValueType In1Ty, ValueType In2Ty> 182 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC), 183 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 184 [(set OutTy:$vD, 185 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 186 187// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 188class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 189 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 190 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 191 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 192 193// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 194// inputs doesn't match the type of the output. 195class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 196 ValueType InTy> 197 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 198 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 199 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 200 201// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 202// input types and an output type. 203class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 204 ValueType In1Ty, ValueType In2Ty> 205 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 206 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 207 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 208 209// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 210class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 211 : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB), 212 !strconcat(opc, " $vD, $vB"), VecFP, 213 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 214 215// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 216// inputs doesn't match the type of the output. 217class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 218 ValueType InTy> 219 : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB), 220 !strconcat(opc, " $vD, $vB"), VecFP, 221 [(set OutTy:$vD, (IntID InTy:$vB))]>; 222 223//===----------------------------------------------------------------------===// 224// Instruction Definitions. 225 226def HasAltivec : Predicate<"PPCSubTarget.hasAltivec()">; 227let Predicates = [HasAltivec] in { 228 229let isCodeGenOnly = 1 in { 230def DSS : DSS_Form<822, (outs), 231 (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), 232 "dss $STRM", LdStLoad /*FIXME*/, []>; 233def DSSALL : DSS_Form<822, (outs), 234 (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), 235 "dssall", LdStLoad /*FIXME*/, []>; 236def DST : DSS_Form<342, (outs), 237 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 238 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 239def DSTT : DSS_Form<342, (outs), 240 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 241 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 242def DSTST : DSS_Form<374, (outs), 243 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 244 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 245def DSTSTT : DSS_Form<374, (outs), 246 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 247 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 248 249def DST64 : DSS_Form<342, (outs), 250 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 251 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 252def DSTT64 : DSS_Form<342, (outs), 253 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 254 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 255def DSTST64 : DSS_Form<374, (outs), 256 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 257 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 258def DSTSTT64 : DSS_Form<374, (outs), 259 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 260 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 261} 262 263def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins), 264 "mfvscr $vD", LdStStore, 265 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 266def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB), 267 "mtvscr $vB", LdStLoad, 268 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 269 270let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads. 271def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src), 272 "lvebx $vD, $src", LdStLoad, 273 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 274def LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src), 275 "lvehx $vD, $src", LdStLoad, 276 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 277def LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src), 278 "lvewx $vD, $src", LdStLoad, 279 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 280def LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src), 281 "lvx $vD, $src", LdStLoad, 282 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 283def LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src), 284 "lvxl $vD, $src", LdStLoad, 285 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 286} 287 288def LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src), 289 "lvsl $vD, $src", LdStLoad, 290 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 291 PPC970_Unit_LSU; 292def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src), 293 "lvsr $vD, $src", LdStLoad, 294 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 295 PPC970_Unit_LSU; 296 297let PPC970_Unit = 2 in { // Stores. 298def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst), 299 "stvebx $rS, $dst", LdStStore, 300 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; 301def STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst), 302 "stvehx $rS, $dst", LdStStore, 303 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; 304def STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst), 305 "stvewx $rS, $dst", LdStStore, 306 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 307def STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst), 308 "stvx $rS, $dst", LdStStore, 309 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 310def STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst), 311 "stvxl $rS, $dst", LdStStore, 312 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 313} 314 315let PPC970_Unit = 5 in { // VALU Operations. 316// VA-Form instructions. 3-input AltiVec ops. 317def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), 318 "vmaddfp $vD, $vA, $vC, $vB", VecFP, 319 [(set v4f32:$vD, 320 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 321def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), 322 "vnmsubfp $vD, $vA, $vC, $vB", VecFP, 323 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 324 (fneg v4f32:$vB))))]>; 325 326def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 327def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 328 v8i16>; 329def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 330 331def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 332 v4i32, v4i32, v16i8>; 333def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 334 335// Shuffles. 336def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH), 337 "vsldoi $vD, $vA, $vB, $SH", VecFP, 338 [(set v16i8:$vD, 339 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>; 340 341// VX-Form instructions. AltiVec arithmetic ops. 342def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 343 "vaddfp $vD, $vA, $vB", VecFP, 344 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 345 346def VADDUBM : VXForm_1<0, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 347 "vaddubm $vD, $vA, $vB", VecGeneral, 348 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 349def VADDUHM : VXForm_1<64, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 350 "vadduhm $vD, $vA, $vB", VecGeneral, 351 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 352def VADDUWM : VXForm_1<128, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 353 "vadduwm $vD, $vA, $vB", VecGeneral, 354 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 355 356def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 357def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 358def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 359def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 360def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 361def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 362def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 363 364 365def VAND : VXForm_1<1028, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 366 "vand $vD, $vA, $vB", VecFP, 367 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; 368def VANDC : VXForm_1<1092, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 369 "vandc $vD, $vA, $vB", VecFP, 370 [(set v4i32:$vD, (and v4i32:$vA, 371 (vnot_ppc v4i32:$vB)))]>; 372 373def VCFSX : VXForm_1<842, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 374 "vcfsx $vD, $vB, $UIMM", VecFP, 375 [(set v4f32:$vD, 376 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>; 377def VCFUX : VXForm_1<778, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 378 "vcfux $vD, $vB, $UIMM", VecFP, 379 [(set v4f32:$vD, 380 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>; 381def VCTSXS : VXForm_1<970, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 382 "vctsxs $vD, $vB, $UIMM", VecFP, 383 [(set v4i32:$vD, 384 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>; 385def VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 386 "vctuxs $vD, $vB, $UIMM", VecFP, 387 [(set v4i32:$vD, 388 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>; 389 390// Defines with the UIM field set to 0 for floating-point 391// to integer (fp_to_sint/fp_to_uint) conversions and integer 392// to floating-point (sint_to_fp/uint_to_fp) conversions. 393let VA = 0 in { 394def VCFSX_0 : VXForm_1<842, (outs VRRC:$vD), (ins VRRC:$vB), 395 "vcfsx $vD, $vB, 0", VecFP, 396 [(set v4f32:$vD, 397 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 398def VCTUXS_0 : VXForm_1<906, (outs VRRC:$vD), (ins VRRC:$vB), 399 "vctuxs $vD, $vB, 0", VecFP, 400 [(set v4i32:$vD, 401 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 402def VCFUX_0 : VXForm_1<778, (outs VRRC:$vD), (ins VRRC:$vB), 403 "vcfux $vD, $vB, 0", VecFP, 404 [(set v4f32:$vD, 405 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 406def VCTSXS_0 : VXForm_1<970, (outs VRRC:$vD), (ins VRRC:$vB), 407 "vctsxs $vD, $vB, 0", VecFP, 408 [(set v4i32:$vD, 409 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 410} 411def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 412def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 413 414def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 415def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 416def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 417def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 418def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 419def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 420 421def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 422def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 423def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 424def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 425def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 426def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 427def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 428def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 429def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 430def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 431def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 432def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 433def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 434def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 435 436def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 437 "vmrghb $vD, $vA, $vB", VecFP, 438 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 439def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 440 "vmrghh $vD, $vA, $vB", VecFP, 441 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; 442def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 443 "vmrghw $vD, $vA, $vB", VecFP, 444 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; 445def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 446 "vmrglb $vD, $vA, $vB", VecFP, 447 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 448def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 449 "vmrglh $vD, $vA, $vB", VecFP, 450 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; 451def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 452 "vmrglw $vD, $vA, $vB", VecFP, 453 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; 454 455def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 456 v4i32, v16i8, v4i32>; 457def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 458 v4i32, v8i16, v4i32>; 459def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 460 v4i32, v8i16, v4i32>; 461def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 462 v4i32, v16i8, v4i32>; 463def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 464 v4i32, v8i16, v4i32>; 465def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 466 v4i32, v8i16, v4i32>; 467 468def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 469 v8i16, v16i8>; 470def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 471 v4i32, v8i16>; 472def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 473 v8i16, v16i8>; 474def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 475 v4i32, v8i16>; 476def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 477 v8i16, v16i8>; 478def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 479 v4i32, v8i16>; 480def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 481 v8i16, v16i8>; 482def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 483 v4i32, v8i16>; 484 485def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 486def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 487def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 488def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 489def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 490def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 491 492def VSUBCUW : VX1_Int_Ty<74, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 493 494def VSUBFP : VXForm_1<74, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 495 "vsubfp $vD, $vA, $vB", VecGeneral, 496 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 497def VSUBUBM : VXForm_1<1024, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 498 "vsububm $vD, $vA, $vB", VecGeneral, 499 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 500def VSUBUHM : VXForm_1<1088, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 501 "vsubuhm $vD, $vA, $vB", VecGeneral, 502 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 503def VSUBUWM : VXForm_1<1152, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 504 "vsubuwm $vD, $vA, $vB", VecGeneral, 505 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 506 507def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 508def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 509def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 510def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 511def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 512def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 513 514def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 515def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 516 517def VSUM4SBS: VX1_Int_Ty3<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs, 518 v4i32, v16i8, v4i32>; 519def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 520 v4i32, v8i16, v4i32>; 521def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 522 v4i32, v16i8, v4i32>; 523 524def VNOR : VXForm_1<1284, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 525 "vnor $vD, $vA, $vB", VecFP, 526 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, 527 v4i32:$vB)))]>; 528def VOR : VXForm_1<1156, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 529 "vor $vD, $vA, $vB", VecFP, 530 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; 531def VXOR : VXForm_1<1220, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 532 "vxor $vD, $vA, $vB", VecFP, 533 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; 534 535def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 536def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 537def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 538 539def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 540def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 541 542def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 543def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 544def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 545 546def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 547 "vspltb $vD, $vB, $UIMM", VecPerm, 548 [(set v16i8:$vD, 549 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; 550def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 551 "vsplth $vD, $vB, $UIMM", VecPerm, 552 [(set v16i8:$vD, 553 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; 554def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 555 "vspltw $vD, $vB, $UIMM", VecPerm, 556 [(set v16i8:$vD, 557 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; 558 559def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 560def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 561 562def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 563def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 564def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 565def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 566def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 567def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 568 569 570def VSPLTISB : VXForm_3<780, (outs VRRC:$vD), (ins s5imm:$SIMM), 571 "vspltisb $vD, $SIMM", VecPerm, 572 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 573def VSPLTISH : VXForm_3<844, (outs VRRC:$vD), (ins s5imm:$SIMM), 574 "vspltish $vD, $SIMM", VecPerm, 575 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 576def VSPLTISW : VXForm_3<908, (outs VRRC:$vD), (ins s5imm:$SIMM), 577 "vspltisw $vD, $SIMM", VecPerm, 578 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 579 580// Vector Pack. 581def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 582 v8i16, v4i32>; 583def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 584 v16i8, v8i16>; 585def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 586 v16i8, v8i16>; 587def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 588 v16i8, v4i32>; 589def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 590 v8i16, v4i32>; 591def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 592 "vpkuhum $vD, $vA, $vB", VecFP, 593 [(set v16i8:$vD, 594 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; 595def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 596 v16i8, v8i16>; 597def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 598 "vpkuwum $vD, $vA, $vB", VecFP, 599 [(set v16i8:$vD, 600 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; 601def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 602 v8i16, v4i32>; 603 604// Vector Unpack. 605def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 606 v4i32, v8i16>; 607def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 608 v8i16, v16i8>; 609def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 610 v4i32, v8i16>; 611def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 612 v4i32, v8i16>; 613def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 614 v8i16, v16i8>; 615def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 616 v4i32, v8i16>; 617 618 619// Altivec Comparisons. 620 621class VCMP<bits<10> xo, string asmstr, ValueType Ty> 622 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, 623 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 624class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 625 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, 626 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> { 627 let Defs = [CR6]; 628 let RC = 1; 629} 630 631// f32 element comparisons.0 632def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 633def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 634def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 635def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 636def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 637def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 638def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 639def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 640 641// i8 element comparisons. 642def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 643def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 644def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 645def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 646def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 647def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 648 649// i16 element comparisons. 650def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 651def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 652def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 653def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 654def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 655def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 656 657// i32 element comparisons. 658def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 659def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 660def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 661def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 662def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 663def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 664 665let isCodeGenOnly = 1 in 666def V_SET0 : VXForm_setzero<1220, (outs VRRC:$vD), (ins), 667 "vxor $vD, $vD, $vD", VecFP, 668 [(set v4i32:$vD, (v4i32 immAllZerosV))]>; 669let IMM=-1 in { 670def V_SETALLONES : VXForm_3<908, (outs VRRC:$vD), (ins), 671 "vspltisw $vD, -1", VecFP, 672 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 673} 674} // VALU Operations. 675 676//===----------------------------------------------------------------------===// 677// Additional Altivec Patterns 678// 679 680// DS* intrinsics 681def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>; 682def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; 683 684// * 32-bit 685def : Pat<(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM), 686 (DST 0, imm:$STRM, $rA, $rB)>; 687def : Pat<(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM), 688 (DSTT 1, imm:$STRM, $rA, $rB)>; 689def : Pat<(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM), 690 (DSTST 0, imm:$STRM, $rA, $rB)>; 691def : Pat<(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM), 692 (DSTSTT 1, imm:$STRM, $rA, $rB)>; 693 694// * 64-bit 695def : Pat<(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM), 696 (DST64 0, imm:$STRM, $rA, $rB)>; 697def : Pat<(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM), 698 (DSTT64 1, imm:$STRM, $rA, $rB)>; 699def : Pat<(int_ppc_altivec_dstst i64:$rA, i32:$rB, imm:$STRM), 700 (DSTST64 0, imm:$STRM, $rA, $rB)>; 701def : Pat<(int_ppc_altivec_dststt i64:$rA, i32:$rB, imm:$STRM), 702 (DSTSTT64 1, imm:$STRM, $rA, $rB)>; 703 704// Loads. 705def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 706 707// Stores. 708def : Pat<(store v4i32:$rS, xoaddr:$dst), 709 (STVX $rS, xoaddr:$dst)>; 710 711// Bit conversions. 712def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 713def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 714def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 715 716def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 717def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 718def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 719 720def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 721def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 722def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 723 724def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 725def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 726def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 727 728// Shuffles. 729 730// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 731def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 732 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>; 733def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 734 (VPKUWUM $vA, $vA)>; 735def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 736 (VPKUHUM $vA, $vA)>; 737 738// Match vmrg*(x,x) 739def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 740 (VMRGLB $vA, $vA)>; 741def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 742 (VMRGLH $vA, $vA)>; 743def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 744 (VMRGLW $vA, $vA)>; 745def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 746 (VMRGHB $vA, $vA)>; 747def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 748 (VMRGHH $vA, $vA)>; 749def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 750 (VMRGHW $vA, $vA)>; 751 752// Logical Operations 753def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; 754 755def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)), 756 (VNOR $A, $B)>; 757def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)), 758 (VANDC $A, $B)>; 759 760def : Pat<(fmul v4f32:$vA, v4f32:$vB), 761 (VMADDFP $vA, $vB, 762 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>; 763 764// Fused multiply add and multiply sub for packed float. These are represented 765// separately from the real instructions above, for operations that must have 766// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 767def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 768 (VMADDFP $A, $B, $C)>; 769def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 770 (VNMSUBFP $A, $B, $C)>; 771 772def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 773 (VMADDFP $A, $B, $C)>; 774def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 775 (VNMSUBFP $A, $B, $C)>; 776 777def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), 778 (VPERM $vA, $vB, $vC)>; 779 780def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 781def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 782 783// Vector shifts 784def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 785 (v16i8 (VSLB $vA, $vB))>; 786def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 787 (v8i16 (VSLH $vA, $vB))>; 788def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 789 (v4i32 (VSLW $vA, $vB))>; 790 791def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 792 (v16i8 (VSRB $vA, $vB))>; 793def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 794 (v8i16 (VSRH $vA, $vB))>; 795def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 796 (v4i32 (VSRW $vA, $vB))>; 797 798def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 799 (v16i8 (VSRAB $vA, $vB))>; 800def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 801 (v8i16 (VSRAH $vA, $vB))>; 802def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 803 (v4i32 (VSRAW $vA, $vB))>; 804 805// Float to integer and integer to float conversions 806def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 807 (VCTSXS_0 $vA)>; 808def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 809 (VCTUXS_0 $vA)>; 810def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 811 (VCFSX_0 $vA)>; 812def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 813 (VCFUX_0 $vA)>; 814 815// Floating-point rounding 816def : Pat<(v4f32 (ffloor v4f32:$vA)), 817 (VRFIM $vA)>; 818def : Pat<(v4f32 (fceil v4f32:$vA)), 819 (VRFIP $vA)>; 820def : Pat<(v4f32 (ftrunc v4f32:$vA)), 821 (VRFIZ $vA)>; 822def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 823 (VRFIN $vA)>; 824 825} // end HasAltivec 826 827