PPCInstrAltivec.td revision 827307b95fa909e35a3ddef612f9f50ffcf0963a
1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Altivec extension to the PowerPC instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Altivec transformation functions and pattern fragments. 16// 17 18// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 19// of that type. 20def vnot_ppc : PatFrag<(ops node:$in), 21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 22 23def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 24 (vector_shuffle node:$lhs, node:$rhs), [{ 25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 26}]>; 27def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 28 (vector_shuffle node:$lhs, node:$rhs), [{ 29 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 30}]>; 31def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 32 (vector_shuffle node:$lhs, node:$rhs), [{ 33 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 34}]>; 35def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 36 (vector_shuffle node:$lhs, node:$rhs), [{ 37 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 38}]>; 39 40 41def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 42 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 43 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 44}]>; 45def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 47 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 48}]>; 49def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 50 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 51 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 52}]>; 53def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 54 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 55 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 56}]>; 57def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 58 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 59 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 60}]>; 61def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 62 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 63 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 64}]>; 65 66 67def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 69 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 70}]>; 71def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 72 (vector_shuffle node:$lhs, node:$rhs), [{ 73 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 74}]>; 75def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 76 (vector_shuffle node:$lhs, node:$rhs), [{ 77 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 78}]>; 79def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 80 (vector_shuffle node:$lhs, node:$rhs), [{ 81 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 82}]>; 83def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 84 (vector_shuffle node:$lhs, node:$rhs), [{ 85 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 86}]>; 87def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 88 (vector_shuffle node:$lhs, node:$rhs), [{ 89 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 90}]>; 91 92 93def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 94 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false)); 95}]>; 96def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 97 (vector_shuffle node:$lhs, node:$rhs), [{ 98 return PPC::isVSLDOIShuffleMask(N, false) != -1; 99}], VSLDOI_get_imm>; 100 101 102/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 103/// vector_shuffle(X,undef,mask) by the dag combiner. 104def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 105 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true)); 106}]>; 107def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 108 (vector_shuffle node:$lhs, node:$rhs), [{ 109 return PPC::isVSLDOIShuffleMask(N, true) != -1; 110}], VSLDOI_unary_get_imm>; 111 112 113// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 114def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 115 return getI32Imm(PPC::getVSPLTImmediate(N, 1)); 116}]>; 117def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 118 (vector_shuffle node:$lhs, node:$rhs), [{ 119 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 120}], VSPLTB_get_imm>; 121def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 122 return getI32Imm(PPC::getVSPLTImmediate(N, 2)); 123}]>; 124def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 125 (vector_shuffle node:$lhs, node:$rhs), [{ 126 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 127}], VSPLTH_get_imm>; 128def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 129 return getI32Imm(PPC::getVSPLTImmediate(N, 4)); 130}]>; 131def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 132 (vector_shuffle node:$lhs, node:$rhs), [{ 133 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 134}], VSPLTW_get_imm>; 135 136 137// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 138def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 139 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 140}]>; 141def vecspltisb : PatLeaf<(build_vector), [{ 142 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0; 143}], VSPLTISB_get_imm>; 144 145// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 146def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 147 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 148}]>; 149def vecspltish : PatLeaf<(build_vector), [{ 150 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0; 151}], VSPLTISH_get_imm>; 152 153// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 154def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 155 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 156}]>; 157def vecspltisw : PatLeaf<(build_vector), [{ 158 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0; 159}], VSPLTISW_get_imm>; 160 161//===----------------------------------------------------------------------===// 162// Helpers for defining instructions that directly correspond to intrinsics. 163 164// VA1a_Int - A VAForm_1a intrinsic definition of generic type. 165class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID> 166 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC), 167 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 168 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>; 169 170// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 171class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 172 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC), 173 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 174 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 175 176// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 177// inputs doesn't match the type of the output. 178class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 179 ValueType InTy> 180 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC), 181 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 182 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 183 184// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 185// input types and an output type. 186class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 187 ValueType In1Ty, ValueType In2Ty> 188 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC), 189 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 190 [(set OutTy:$vD, 191 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 192 193// VX1_Int - A VXForm_1 intrinsic definition of generic type. 194class VX1_Int<bits<11> xo, string opc, Intrinsic IntID> 195 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 196 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 197 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>; 198 199// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 200class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 201 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 202 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 203 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 204 205// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 206// inputs doesn't match the type of the output. 207class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 208 ValueType InTy> 209 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 210 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 211 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 212 213// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 214// input types and an output type. 215class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 216 ValueType In1Ty, ValueType In2Ty> 217 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 218 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 219 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 220 221// VX2_Int - A VXForm_1 intrinsic definition of generic type. 222class VX2_Int<bits<11> xo, string opc, Intrinsic IntID> 223 : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB), 224 !strconcat(opc, " $vD, $vB"), VecFP, 225 [(set VRRC:$vD, (IntID VRRC:$vB))]>; 226 227// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 228class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 229 : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB), 230 !strconcat(opc, " $vD, $vB"), VecFP, 231 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 232 233// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 234// inputs doesn't match the type of the output. 235class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 236 ValueType InTy> 237 : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB), 238 !strconcat(opc, " $vD, $vB"), VecFP, 239 [(set OutTy:$vD, (IntID InTy:$vB))]>; 240 241//===----------------------------------------------------------------------===// 242// Instruction Definitions. 243 244def HasAltivec : Predicate<"PPCSubTarget.hasAltivec()">; 245let Predicates = [HasAltivec] in { 246 247let isCodeGenOnly = 1 in { 248def DSS : DSS_Form<822, (outs), 249 (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), 250 "dss $STRM", LdStLoad /*FIXME*/, []>; 251def DSSALL : DSS_Form<822, (outs), 252 (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), 253 "dssall", LdStLoad /*FIXME*/, []>; 254def DST : DSS_Form<342, (outs), 255 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 256 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 257def DSTT : DSS_Form<342, (outs), 258 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 259 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 260def DSTST : DSS_Form<374, (outs), 261 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 262 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 263def DSTSTT : DSS_Form<374, (outs), 264 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 265 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 266 267def DST64 : DSS_Form<342, (outs), 268 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 269 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 270def DSTT64 : DSS_Form<342, (outs), 271 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 272 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 273def DSTST64 : DSS_Form<374, (outs), 274 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 275 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 276def DSTSTT64 : DSS_Form<374, (outs), 277 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 278 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 279} 280 281def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins), 282 "mfvscr $vD", LdStStore, 283 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 284def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB), 285 "mtvscr $vB", LdStLoad, 286 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 287 288let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads. 289def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src), 290 "lvebx $vD, $src", LdStLoad, 291 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 292def LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src), 293 "lvehx $vD, $src", LdStLoad, 294 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 295def LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src), 296 "lvewx $vD, $src", LdStLoad, 297 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 298def LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src), 299 "lvx $vD, $src", LdStLoad, 300 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 301def LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src), 302 "lvxl $vD, $src", LdStLoad, 303 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 304} 305 306def LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src), 307 "lvsl $vD, $src", LdStLoad, 308 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 309 PPC970_Unit_LSU; 310def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src), 311 "lvsr $vD, $src", LdStLoad, 312 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 313 PPC970_Unit_LSU; 314 315let PPC970_Unit = 2 in { // Stores. 316def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst), 317 "stvebx $rS, $dst", LdStStore, 318 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; 319def STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst), 320 "stvehx $rS, $dst", LdStStore, 321 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; 322def STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst), 323 "stvewx $rS, $dst", LdStStore, 324 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 325def STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst), 326 "stvx $rS, $dst", LdStStore, 327 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 328def STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst), 329 "stvxl $rS, $dst", LdStStore, 330 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 331} 332 333let PPC970_Unit = 5 in { // VALU Operations. 334// VA-Form instructions. 3-input AltiVec ops. 335def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), 336 "vmaddfp $vD, $vA, $vC, $vB", VecFP, 337 [(set v4f32:$vD, 338 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 339def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), 340 "vnmsubfp $vD, $vA, $vC, $vB", VecFP, 341 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 342 (fneg v4f32:$vB))))]>; 343 344def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 345def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 346 v8i16>; 347def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 348 349def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 350 v4i32, v4i32, v16i8>; 351def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 352 353// Shuffles. 354def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH), 355 "vsldoi $vD, $vA, $vB, $SH", VecFP, 356 [(set VRRC:$vD, 357 (vsldoi_shuffle:$SH (v16i8 VRRC:$vA), VRRC:$vB))]>; 358 359// VX-Form instructions. AltiVec arithmetic ops. 360def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 361 "vaddfp $vD, $vA, $vB", VecFP, 362 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 363 364def VADDUBM : VXForm_1<0, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 365 "vaddubm $vD, $vA, $vB", VecGeneral, 366 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 367def VADDUHM : VXForm_1<64, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 368 "vadduhm $vD, $vA, $vB", VecGeneral, 369 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 370def VADDUWM : VXForm_1<128, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 371 "vadduwm $vD, $vA, $vB", VecGeneral, 372 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 373 374def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 375def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 376def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 377def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 378def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 379def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 380def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 381 382 383def VAND : VXForm_1<1028, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 384 "vand $vD, $vA, $vB", VecFP, 385 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>; 386def VANDC : VXForm_1<1092, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 387 "vandc $vD, $vA, $vB", VecFP, 388 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), 389 (vnot_ppc VRRC:$vB)))]>; 390 391def VCFSX : VXForm_1<842, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 392 "vcfsx $vD, $vB, $UIMM", VecFP, 393 [(set v4f32:$vD, 394 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>; 395def VCFUX : VXForm_1<778, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 396 "vcfux $vD, $vB, $UIMM", VecFP, 397 [(set v4f32:$vD, 398 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>; 399def VCTSXS : VXForm_1<970, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 400 "vctsxs $vD, $vB, $UIMM", VecFP, 401 [(set v4i32:$vD, 402 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>; 403def VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 404 "vctuxs $vD, $vB, $UIMM", VecFP, 405 [(set v4i32:$vD, 406 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>; 407 408// Defines with the UIM field set to 0 for floating-point 409// to integer (fp_to_sint/fp_to_uint) conversions and integer 410// to floating-point (sint_to_fp/uint_to_fp) conversions. 411let VA = 0 in { 412def VCFSX_0 : VXForm_1<842, (outs VRRC:$vD), (ins VRRC:$vB), 413 "vcfsx $vD, $vB, 0", VecFP, 414 [(set v4f32:$vD, 415 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 416def VCTUXS_0 : VXForm_1<906, (outs VRRC:$vD), (ins VRRC:$vB), 417 "vctuxs $vD, $vB, 0", VecFP, 418 [(set v4i32:$vD, 419 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 420def VCFUX_0 : VXForm_1<778, (outs VRRC:$vD), (ins VRRC:$vB), 421 "vcfux $vD, $vB, 0", VecFP, 422 [(set v4f32:$vD, 423 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 424def VCTSXS_0 : VXForm_1<970, (outs VRRC:$vD), (ins VRRC:$vB), 425 "vctsxs $vD, $vB, 0", VecFP, 426 [(set v4i32:$vD, 427 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 428} 429def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 430def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 431 432def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 433def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 434def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 435def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 436def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 437def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 438 439def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 440def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 441def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 442def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 443def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 444def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 445def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 446def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 447def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 448def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 449def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 450def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 451def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 452def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 453 454def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 455 "vmrghb $vD, $vA, $vB", VecFP, 456 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 457def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 458 "vmrghh $vD, $vA, $vB", VecFP, 459 [(set VRRC:$vD, (vmrghh_shuffle VRRC:$vA, VRRC:$vB))]>; 460def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 461 "vmrghw $vD, $vA, $vB", VecFP, 462 [(set VRRC:$vD, (vmrghw_shuffle VRRC:$vA, VRRC:$vB))]>; 463def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 464 "vmrglb $vD, $vA, $vB", VecFP, 465 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 466def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 467 "vmrglh $vD, $vA, $vB", VecFP, 468 [(set VRRC:$vD, (vmrglh_shuffle VRRC:$vA, VRRC:$vB))]>; 469def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 470 "vmrglw $vD, $vA, $vB", VecFP, 471 [(set VRRC:$vD, (vmrglw_shuffle VRRC:$vA, VRRC:$vB))]>; 472 473def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 474 v4i32, v16i8, v4i32>; 475def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 476 v4i32, v8i16, v4i32>; 477def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 478 v4i32, v8i16, v4i32>; 479def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 480 v4i32, v16i8, v4i32>; 481def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 482 v4i32, v8i16, v4i32>; 483def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 484 v4i32, v8i16, v4i32>; 485 486def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 487 v8i16, v16i8>; 488def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 489 v4i32, v8i16>; 490def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 491 v8i16, v16i8>; 492def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 493 v4i32, v8i16>; 494def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 495 v8i16, v16i8>; 496def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 497 v4i32, v8i16>; 498def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 499 v8i16, v16i8>; 500def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 501 v4i32, v8i16>; 502 503def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 504def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 505def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 506def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 507def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 508def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 509 510def VSUBCUW : VX1_Int_Ty<74, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 511 512def VSUBFP : VXForm_1<74, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 513 "vsubfp $vD, $vA, $vB", VecGeneral, 514 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 515def VSUBUBM : VXForm_1<1024, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 516 "vsububm $vD, $vA, $vB", VecGeneral, 517 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 518def VSUBUHM : VXForm_1<1088, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 519 "vsubuhm $vD, $vA, $vB", VecGeneral, 520 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 521def VSUBUWM : VXForm_1<1152, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 522 "vsubuwm $vD, $vA, $vB", VecGeneral, 523 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 524 525def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 526def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 527def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 528def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 529def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 530def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 531 532def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 533def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 534 535def VSUM4SBS: VX1_Int_Ty3<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs, 536 v4i32, v16i8, v4i32>; 537def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 538 v4i32, v8i16, v4i32>; 539def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 540 v4i32, v16i8, v4i32>; 541 542def VNOR : VXForm_1<1284, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 543 "vnor $vD, $vA, $vB", VecFP, 544 [(set VRRC:$vD, (vnot_ppc (or (v4i32 VRRC:$vA), 545 VRRC:$vB)))]>; 546def VOR : VXForm_1<1156, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 547 "vor $vD, $vA, $vB", VecFP, 548 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>; 549def VXOR : VXForm_1<1220, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 550 "vxor $vD, $vA, $vB", VecFP, 551 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>; 552 553def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 554def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 555def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 556 557def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 558def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 559 560def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 561def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 562def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 563 564def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 565 "vspltb $vD, $vB, $UIMM", VecPerm, 566 [(set VRRC:$vD, 567 (vspltb_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 568def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 569 "vsplth $vD, $vB, $UIMM", VecPerm, 570 [(set VRRC:$vD, 571 (vsplth_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 572def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 573 "vspltw $vD, $vB, $UIMM", VecPerm, 574 [(set VRRC:$vD, 575 (vspltw_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 576 577def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 578def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 579 580def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 581def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 582def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 583def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 584def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 585def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 586 587 588def VSPLTISB : VXForm_3<780, (outs VRRC:$vD), (ins s5imm:$SIMM), 589 "vspltisb $vD, $SIMM", VecPerm, 590 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 591def VSPLTISH : VXForm_3<844, (outs VRRC:$vD), (ins s5imm:$SIMM), 592 "vspltish $vD, $SIMM", VecPerm, 593 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 594def VSPLTISW : VXForm_3<908, (outs VRRC:$vD), (ins s5imm:$SIMM), 595 "vspltisw $vD, $SIMM", VecPerm, 596 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 597 598// Vector Pack. 599def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 600 v8i16, v4i32>; 601def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 602 v16i8, v8i16>; 603def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 604 v16i8, v8i16>; 605def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 606 v16i8, v4i32>; 607def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 608 v8i16, v4i32>; 609def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 610 "vpkuhum $vD, $vA, $vB", VecFP, 611 [(set VRRC:$vD, 612 (vpkuhum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>; 613def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 614 v16i8, v8i16>; 615def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 616 "vpkuwum $vD, $vA, $vB", VecFP, 617 [(set VRRC:$vD, 618 (vpkuwum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>; 619def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 620 v8i16, v4i32>; 621 622// Vector Unpack. 623def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 624 v4i32, v8i16>; 625def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 626 v8i16, v16i8>; 627def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 628 v4i32, v8i16>; 629def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 630 v4i32, v8i16>; 631def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 632 v8i16, v16i8>; 633def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 634 v4i32, v8i16>; 635 636 637// Altivec Comparisons. 638 639class VCMP<bits<10> xo, string asmstr, ValueType Ty> 640 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, 641 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 642class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 643 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, 644 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> { 645 let Defs = [CR6]; 646 let RC = 1; 647} 648 649// f32 element comparisons.0 650def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 651def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 652def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 653def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 654def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 655def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 656def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 657def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 658 659// i8 element comparisons. 660def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 661def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 662def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 663def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 664def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 665def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 666 667// i16 element comparisons. 668def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 669def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 670def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 671def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 672def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 673def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 674 675// i32 element comparisons. 676def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 677def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 678def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 679def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 680def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 681def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 682 683let isCodeGenOnly = 1 in 684def V_SET0 : VXForm_setzero<1220, (outs VRRC:$vD), (ins), 685 "vxor $vD, $vD, $vD", VecFP, 686 [(set VRRC:$vD, (v4i32 immAllZerosV))]>; 687let IMM=-1 in { 688def V_SETALLONES : VXForm_3<908, (outs VRRC:$vD), (ins), 689 "vspltisw $vD, -1", VecFP, 690 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 691} 692} // VALU Operations. 693 694//===----------------------------------------------------------------------===// 695// Additional Altivec Patterns 696// 697 698// DS* intrinsics 699def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>; 700def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; 701 702// * 32-bit 703def : Pat<(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM), 704 (DST 0, imm:$STRM, $rA, $rB)>; 705def : Pat<(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM), 706 (DSTT 1, imm:$STRM, $rA, $rB)>; 707def : Pat<(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM), 708 (DSTST 0, imm:$STRM, $rA, $rB)>; 709def : Pat<(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM), 710 (DSTSTT 1, imm:$STRM, $rA, $rB)>; 711 712// * 64-bit 713def : Pat<(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM), 714 (DST64 0, imm:$STRM, $rA, $rB)>; 715def : Pat<(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM), 716 (DSTT64 1, imm:$STRM, $rA, $rB)>; 717def : Pat<(int_ppc_altivec_dstst i64:$rA, i32:$rB, imm:$STRM), 718 (DSTST64 0, imm:$STRM, $rA, $rB)>; 719def : Pat<(int_ppc_altivec_dststt i64:$rA, i32:$rB, imm:$STRM), 720 (DSTSTT64 1, imm:$STRM, $rA, $rB)>; 721 722// Loads. 723def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 724 725// Stores. 726def : Pat<(store v4i32:$rS, xoaddr:$dst), 727 (STVX $rS, xoaddr:$dst)>; 728 729// Bit conversions. 730def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 731def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 732def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 733 734def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 735def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 736def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 737 738def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 739def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 740def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 741 742def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 743def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 744def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 745 746// Shuffles. 747 748// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 749def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 750 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm VRRC:$in))>; 751def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 752 (VPKUWUM $vA, $vA)>; 753def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 754 (VPKUHUM $vA, $vA)>; 755 756// Match vmrg*(x,x) 757def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 758 (VMRGLB $vA, $vA)>; 759def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 760 (VMRGLH $vA, $vA)>; 761def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 762 (VMRGLW $vA, $vA)>; 763def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 764 (VMRGHB $vA, $vA)>; 765def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 766 (VMRGHH $vA, $vA)>; 767def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 768 (VMRGHW $vA, $vA)>; 769 770// Logical Operations 771def : Pat<(v4i32 (vnot_ppc VRRC:$vA)), (VNOR $vA, $vA)>; 772 773def : Pat<(v4i32 (vnot_ppc (or VRRC:$A, VRRC:$B))), 774 (VNOR $A, $B)>; 775def : Pat<(v4i32 (and VRRC:$A, (vnot_ppc VRRC:$B))), 776 (VANDC $A, $B)>; 777 778def : Pat<(fmul v4f32:$vA, v4f32:$vB), 779 (VMADDFP $vA, $vB, 780 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>; 781 782// Fused multiply add and multiply sub for packed float. These are represented 783// separately from the real instructions above, for operations that must have 784// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 785def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 786 (VMADDFP $A, $B, $C)>; 787def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 788 (VNMSUBFP $A, $B, $C)>; 789 790def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 791 (VMADDFP $A, $B, $C)>; 792def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 793 (VNMSUBFP $A, $B, $C)>; 794 795def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC), 796 (VPERM $vA, $vB, $vC)>; 797 798def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 799def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 800 801// Vector shifts 802def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 803 (v16i8 (VSLB $vA, $vB))>; 804def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 805 (v8i16 (VSLH $vA, $vB))>; 806def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 807 (v4i32 (VSLW $vA, $vB))>; 808 809def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 810 (v16i8 (VSRB $vA, $vB))>; 811def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 812 (v8i16 (VSRH $vA, $vB))>; 813def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 814 (v4i32 (VSRW $vA, $vB))>; 815 816def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 817 (v16i8 (VSRAB $vA, $vB))>; 818def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 819 (v8i16 (VSRAH $vA, $vB))>; 820def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 821 (v4i32 (VSRAW $vA, $vB))>; 822 823// Float to integer and integer to float conversions 824def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 825 (VCTSXS_0 $vA)>; 826def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 827 (VCTUXS_0 $vA)>; 828def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 829 (VCFSX_0 $vA)>; 830def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 831 (VCFUX_0 $vA)>; 832 833// Floating-point rounding 834def : Pat<(v4f32 (ffloor v4f32:$vA)), 835 (VRFIM $vA)>; 836def : Pat<(v4f32 (fceil v4f32:$vA)), 837 (VRFIP $vA)>; 838def : Pat<(v4f32 (ftrunc v4f32:$vA)), 839 (VRFIZ $vA)>; 840def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 841 (VRFIN $vA)>; 842 843} // end HasAltivec 844 845