PPCInstrAltivec.td revision c3837d49178c2d3f8e80347f93f4859d46175cc0 
1//===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Altivec extension to the PowerPC instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Altivec transformation functions and pattern fragments.
16//
17
18// VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
19def VSPLT_get_imm : SDNodeXForm<build_vector, [{
20  return getI32Imm(PPC::getVSPLTImmediate(N));
21}]>;
22
23def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
24  return PPC::isSplatShuffleMask(N);
25}], VSPLT_get_imm>;
26
27
28// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
29def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
30  char Val;
31  PPC::isVecSplatImm(N, 1, &Val);
32  return getI32Imm(Val);
33}]>;
34def vecspltisb : PatLeaf<(build_vector), [{
35  return PPC::isVecSplatImm(N, 1);
36}], VSPLTISB_get_imm>;
37
38// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
39def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
40  char Val;
41  PPC::isVecSplatImm(N, 2, &Val);
42  return getI32Imm(Val);
43}]>;
44def vecspltish : PatLeaf<(build_vector), [{
45  return PPC::isVecSplatImm(N, 2);
46}], VSPLTISH_get_imm>;
47
48// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
49def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
50  char Val;
51  PPC::isVecSplatImm(N, 4, &Val);
52  return getI32Imm(Val);
53}]>;
54def vecspltisw : PatLeaf<(build_vector), [{
55  return PPC::isVecSplatImm(N, 4);
56}], VSPLTISW_get_imm>;
57
58class isVDOT {   // vector dot instruction.
59  list<Register> Defs = [CR6];
60  bit RC = 1;
61}
62
63//===----------------------------------------------------------------------===//
64// Helpers for defining instructions that directly correspond to intrinsics.
65
66// VA1a_Int - A VAForm_1a intrinsic definition.
67class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
68  : VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
69              !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
70                       [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
71
72// VX1_Int - A VXForm_1 intrinsic definition.
73class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
74  : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
75             !strconcat(opc, " $vD, $vA, $vB"), VecFP,
76             [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
77
78// VX2_Int - A VXForm_2 intrinsic definition.
79class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
80  : VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB),
81             !strconcat(opc, " $vD, $vB"), VecFP,
82             [(set VRRC:$vD, (IntID VRRC:$vB))]>;
83
84//===----------------------------------------------------------------------===//
85// Instruction Definitions.
86
87def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
88                               [(set VRRC:$rD, (v4f32 (undef)))]>;
89
90let isLoad = 1, PPC970_Unit = 2 in {  // Loads.
91def LVEBX: XForm_1<31,   7, (ops VRRC:$vD, memrr:$src),
92                   "lvebx $vD, $src", LdStGeneral,
93                   [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
94def LVEHX: XForm_1<31,  39, (ops VRRC:$vD, memrr:$src),
95                   "lvehx $vD, $src", LdStGeneral,
96                   [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
97def LVEWX: XForm_1<31,  71, (ops VRRC:$vD, memrr:$src),
98                   "lvewx $vD, $src", LdStGeneral,
99                   [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
100def LVX  : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
101                   "lvx $vD, $src", LdStGeneral,
102                   [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
103def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src),
104                   "lvxl $vD, $src", LdStGeneral,
105                   [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
106}
107
108def LVSL : XForm_1<31,   6, (ops VRRC:$vD, memrr:$src),
109                   "lvsl $vD, $src", LdStGeneral,
110                   [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
111                   PPC970_Unit_LSU;
112def LVSR : XForm_1<31,  38, (ops VRRC:$vD, memrr:$src),
113                   "lvsl $vD, $src", LdStGeneral,
114                   [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
115                   PPC970_Unit_LSU;
116
117let isStore = 1, noResults = 1, PPC970_Unit = 2 in {   // Stores.
118def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
119                   "stvebx $rS, $dst", LdStGeneral,
120                   [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
121def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
122                   "stvehx $rS, $dst", LdStGeneral,
123                   [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
124def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
125                   "stvewx $rS, $dst", LdStGeneral,
126                   [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
127def STVX  : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
128                   "stvx $rS, $dst", LdStGeneral,
129                   [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
130def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst),
131                   "stvxl $rS, $dst", LdStGeneral,
132                   [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
133}
134
135let PPC970_Unit = 5 in {  // VALU Operations.
136// VA-Form instructions.  3-input AltiVec ops.
137def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
138                       "vmaddfp $vD, $vA, $vC, $vB", VecFP,
139                       [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
140                                             VRRC:$vB))]>,
141                       Requires<[FPContractions]>;
142def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
143                       "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
144                       [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
145                                                   VRRC:$vB)))]>,
146                       Requires<[FPContractions]>;
147def VMHADDSHS  : VA1a_Int<32, "vmhaddshs",  int_ppc_altivec_vmhaddshs>;
148def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
149def VPERM      : VA1a_Int<43, "vperm",      int_ppc_altivec_vperm>;
150def VSEL       : VA1a_Int<42, "vsel",       int_ppc_altivec_vsel>;
151
152def VSLDOI  : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
153                       "vsldoi $vD, $vA, $vB, $SH", VecFP,
154                       [(set VRRC:$vD,
155                             (int_ppc_altivec_vsldoi VRRC:$vA, VRRC:$vB,
156                                                     imm:$SH))]>;
157
158// VX-Form instructions.  AltiVec arithmetic ops.
159def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
160                      "vaddfp $vD, $vA, $vB", VecFP,
161                      [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
162                      
163def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
164                      "vaddubm $vD, $vA, $vB", VecGeneral,
165                      [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
166def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
167                      "vadduhm $vD, $vA, $vB", VecGeneral,
168                      [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
169def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
170                      "vadduwm $vD, $vA, $vB", VecGeneral,
171                      [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
172                      
173def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>;
174def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>;
175def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>;
176def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>;
177def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>;
178def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>;
179def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>;
180                             
181                             
182def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
183                    "vand $vD, $vA, $vB", VecFP,
184                    [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
185def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
186                     "vandc $vD, $vA, $vB", VecFP,
187                     [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
188
189def VCFSX  : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
190                      "vcfsx $vD, $vB, $UIMM", VecFP,
191                      [(set VRRC:$vD,
192                             (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
193def VCFUX  : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
194                      "vcfux $vD, $vB, $UIMM", VecFP,
195                      [(set VRRC:$vD,
196                             (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
197def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
198                      "vctsxs $vD, $vB, $UIMM", VecFP,
199                      []>;
200def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
201                      "vctuxs $vD, $vB, $UIMM", VecFP,
202                      []>;
203def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>;
204def VLOGEFP  : VX2_Int<458, "vlogefp",  int_ppc_altivec_vlogefp>;
205
206def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
207                      "vmaxfp $vD, $vA, $vB", VecFP,
208                      []>;
209def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
210                      "vminfp $vD, $vA, $vB", VecFP,
211                      []>;
212
213def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>;
214def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>;
215def VMRGLH : VX1_Int<332, "vmrglh", int_ppc_altivec_vmrglh>;
216def VMRGLW : VX1_Int<396, "vmrglw", int_ppc_altivec_vmrglw>;
217
218def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
219def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
220def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>;
221def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
222def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
223def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
224
225def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>;
226def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>;
227def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>;
228def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>;
229def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>;
230def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>;
231def VMULOUB : VX1_Int<  8, "vmuloub", int_ppc_altivec_vmuloub>;
232def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>;
233                       
234def VREFP     : VX2_Int<266, "vrefp",     int_ppc_altivec_vrefp>;
235def VRFIM     : VX2_Int<714, "vrfim",     int_ppc_altivec_vrfim>;
236def VRFIN     : VX2_Int<522, "vrfin",     int_ppc_altivec_vrfin>;
237def VRFIP     : VX2_Int<650, "vrfip",     int_ppc_altivec_vrfip>;
238def VRFIZ     : VX2_Int<586, "vrfiz",     int_ppc_altivec_vrfiz>;
239def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
240
241def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>;
242
243def VSUBFP  : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
244                      "vsubfp $vD, $vA, $vB", VecGeneral,
245                      [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
246def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
247                      "vsububm $vD, $vA, $vB", VecGeneral,
248                      [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
249def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
250                      "vsubuhm $vD, $vA, $vB", VecGeneral,
251                      [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
252def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
253                      "vsubuwm $vD, $vA, $vB", VecGeneral,
254                      [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
255                      
256def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>;
257def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>;
258def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>;
259def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>;
260def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>;
261def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>;
262def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>;
263def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>;
264def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>;
265def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>;
266def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>;
267
268def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
269                    "vnor $vD, $vA, $vB", VecFP,
270                    [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
271def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
272                      "vor $vD, $vA, $vB", VecFP,
273                      [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
274def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
275                      "vxor $vD, $vA, $vB", VecFP,
276                      [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
277
278def VRLB   : VX1_Int<   4, "vrlb", int_ppc_altivec_vrlb>;
279def VRLH   : VX1_Int<  68, "vrlh", int_ppc_altivec_vrlh>;
280def VRLW   : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
281def VSLO   : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
282def VSLB   : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
283def VSLH   : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
284def VSLW   : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
285
286def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
287                      "vspltb $vD, $vB, $UIMM", VecPerm,
288                      []>;
289def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
290                      "vsplth $vD, $vB, $UIMM", VecPerm,
291                      []>;
292def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
293                      "vspltw $vD, $vB, $UIMM", VecPerm,
294                      [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
295                                      VSPLT_shuffle_mask:$UIMM))]>;
296
297def VSR    : VX1_Int< 708, "vsr"  , int_ppc_altivec_vsr>;
298def VSRO   : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
299def VSRAB  : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>;
300def VSRAH  : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>;
301def VSRAW  : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>;
302def VSRB   : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>;
303def VSRH   : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>;
304def VSRW   : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>;
305
306
307def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
308                       "vspltisb $vD, $SIMM", VecPerm,
309                       [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
310def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
311                       "vspltish $vD, $SIMM", VecPerm,
312                       [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
313def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
314                       "vspltisw $vD, $SIMM", VecPerm,
315                       [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
316
317// Vector Pack.
318def VPKPX   : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>;
319def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>;
320def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>;
321def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
322def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
323def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
324                       "vpkuhum $vD, $vA, $vB", VecFP,
325                       [/*TODO*/]>;
326def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
327def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
328                       "vpkuwum $vD, $vA, $vB", VecFP,
329                       [/*TODO*/]>;
330def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
331
332// Vector Unpack.
333def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>;
334def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>;
335def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>;
336def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>;
337def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>;
338def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>;
339
340
341// Altivec Comparisons.
342
343class VCMP<bits<10> xo, string asmstr, ValueType Ty>
344  : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
345              [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
346class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
347  : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
348              [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]>,isVDOT;
349
350// f32 element comparisons.0
351def VCMPBFP   : VCMP <966, "vcmpbfp $vD, $vA, $vB"  , v4f32>;
352def VCMPBFPo  : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
353def VCMPEQFP  : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
354def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
355def VCMPGEFP  : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
356def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
357def VCMPGTFP  : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
358def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
359
360// i8 element comparisons.
361def VCMPEQUB  : VCMP <  6, "vcmpequb $vD, $vA, $vB" , v16i8>;
362def VCMPEQUBo : VCMPo<  6, "vcmpequb. $vD, $vA, $vB", v16i8>;
363def VCMPGTSB  : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
364def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
365def VCMPGTUB  : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
366def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
367
368// i16 element comparisons.
369def VCMPEQUH  : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
370def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
371def VCMPGTSH  : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
372def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
373def VCMPGTUH  : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
374def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
375
376// i32 element comparisons.
377def VCMPEQUW  : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
378def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
379def VCMPGTSW  : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
380def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
381def VCMPGTUW  : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
382def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
383                      
384def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
385                      "vxor $vD, $vD, $vD", VecFP,
386                      [(set VRRC:$vD, (v4f32 immAllZerosV))]>;
387}
388
389//===----------------------------------------------------------------------===//
390// Additional Altivec Patterns
391//
392
393// Undef/Zero.
394def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
395def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
396def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
397def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>;
398def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>;
399def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>;
400
401// Loads.
402def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
403def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
404def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
405def : Pat<(v4f32 (load xoaddr:$src)), (v4f32 (LVX xoaddr:$src))>;
406
407// Stores.
408def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
409          (STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
410def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
411          (STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
412def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
413          (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
414def : Pat<(store (v4f32 VRRC:$rS), xoaddr:$dst),
415          (STVX (v4f32 VRRC:$rS), xoaddr:$dst)>;
416
417// Bit conversions.
418def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
419def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
420def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
421
422def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
423def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
424def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
425
426def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
427def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
428def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
429
430def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
431def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
432def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
433
434// Immediate vector formation with vsplti*.
435def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>;
436def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>;
437def : Pat<(v16i8 vecspltisw:$invec), (v16i8 (VSPLTISW vecspltisw:$invec))>;
438
439def : Pat<(v8i16 vecspltisb:$invec), (v8i16 (VSPLTISB vecspltisb:$invec))>;
440def : Pat<(v8i16 vecspltish:$invec), (v8i16 (VSPLTISH vecspltish:$invec))>;
441def : Pat<(v8i16 vecspltisw:$invec), (v8i16 (VSPLTISW vecspltisw:$invec))>;
442
443def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>;
444def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>;
445def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
446
447// Logical Operations
448def : Pat<(v16i8 (vnot VRRC:$vA)), (v16i8 (VNOR VRRC:$vA, VRRC:$vA))>;
449def : Pat<(v8i16 (vnot VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>;
450def : Pat<(v4i32 (vnot VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>;
451
452def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>;
453def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>;
454def : Pat<(v16i8 (or  VRRC:$A, VRRC:$B)), (v16i8 (VOR  VRRC:$A, VRRC:$B))>;
455def : Pat<(v8i16 (or  VRRC:$A, VRRC:$B)), (v8i16 (VOR  VRRC:$A, VRRC:$B))>;
456def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>;
457def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>;
458def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>;
459def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>;
460def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))),
461          (v16i8 (VANDC VRRC:$A, VRRC:$B))>;
462def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
463          (v8i16 (VANDC VRRC:$A, VRRC:$B))>;
464
465def : Pat<(fmul VRRC:$vA, VRRC:$vB),
466          (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>; 
467
468// Fused multiply add and multiply sub for packed float.  These are represented
469// separately from the real instructions above, for operations that must have
470// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
471def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
472          (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
473def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
474          (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
475
476def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
477          (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
478def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
479          (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
480def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
481          (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
482
483def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
484          (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
485def : Pat<(PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
486          (v4f32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
487def : Pat<(PPCvperm (v8i16 VRRC:$vA), VRRC:$vB, VRRC:$vC),
488          (v8i16 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
489def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
490          (v16i8 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
491