PPCInstrAltivec.td revision e87192a854ff0f2f1904dd9ea282eb36059bb5af 
1//===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Altivec extension to the PowerPC instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Altivec transformation functions and pattern fragments.
16//
17
18/// VPKUHUM_shuffle_mask/VPKUWUM_shuffle_mask - Return true if this is a valid
19/// shuffle mask for the VPKUHUM or VPKUWUM instructions.
20def VPKUHUM_shuffle_mask : PatLeaf<(build_vector), [{
21  return PPC::isVPKUHUMShuffleMask(N, false);
22}]>;
23def VPKUWUM_shuffle_mask : PatLeaf<(build_vector), [{
24  return PPC::isVPKUWUMShuffleMask(N, false);
25}]>;
26
27def VPKUHUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
28  return PPC::isVPKUHUMShuffleMask(N, true);
29}]>;
30def VPKUWUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
31  return PPC::isVPKUWUMShuffleMask(N, true);
32}]>;
33
34
35def VMRGLB_shuffle_mask : PatLeaf<(build_vector), [{
36  return PPC::isVMRGLShuffleMask(N, 1, false);
37}]>;
38def VMRGLH_shuffle_mask : PatLeaf<(build_vector), [{
39  return PPC::isVMRGLShuffleMask(N, 2, false);
40}]>;
41def VMRGLW_shuffle_mask : PatLeaf<(build_vector), [{
42  return PPC::isVMRGLShuffleMask(N, 4, false);
43}]>;
44def VMRGHB_shuffle_mask : PatLeaf<(build_vector), [{
45  return PPC::isVMRGHShuffleMask(N, 1, false);
46}]>;
47def VMRGHH_shuffle_mask : PatLeaf<(build_vector), [{
48  return PPC::isVMRGHShuffleMask(N, 2, false);
49}]>;
50def VMRGHW_shuffle_mask : PatLeaf<(build_vector), [{
51  return PPC::isVMRGHShuffleMask(N, 4, false);
52}]>;
53
54def VMRGLB_unary_shuffle_mask : PatLeaf<(build_vector), [{
55  return PPC::isVMRGLShuffleMask(N, 1, true);
56}]>;
57def VMRGLH_unary_shuffle_mask : PatLeaf<(build_vector), [{
58  return PPC::isVMRGLShuffleMask(N, 2, true);
59}]>;
60def VMRGLW_unary_shuffle_mask : PatLeaf<(build_vector), [{
61  return PPC::isVMRGLShuffleMask(N, 4, true);
62}]>;
63def VMRGHB_unary_shuffle_mask : PatLeaf<(build_vector), [{
64  return PPC::isVMRGHShuffleMask(N, 1, true);
65}]>;
66def VMRGHH_unary_shuffle_mask : PatLeaf<(build_vector), [{
67  return PPC::isVMRGHShuffleMask(N, 2, true);
68}]>;
69def VMRGHW_unary_shuffle_mask : PatLeaf<(build_vector), [{
70  return PPC::isVMRGHShuffleMask(N, 4, true);
71}]>;
72
73
74def VSLDOI_get_imm : SDNodeXForm<build_vector, [{
75  return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
76}]>;
77def VSLDOI_shuffle_mask :  PatLeaf<(build_vector), [{
78  return PPC::isVSLDOIShuffleMask(N, false) != -1;
79}], VSLDOI_get_imm>;
80
81/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
82/// vector_shuffle(X,undef,mask) by the dag combiner.
83def VSLDOI_unary_get_imm : SDNodeXForm<build_vector, [{
84  return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
85}]>;
86def VSLDOI_unary_shuffle_mask :  PatLeaf<(build_vector), [{
87  return PPC::isVSLDOIShuffleMask(N, true) != -1;
88}], VSLDOI_unary_get_imm>;
89
90
91// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
92def VSPLTB_get_imm : SDNodeXForm<build_vector, [{
93  return getI32Imm(PPC::getVSPLTImmediate(N, 1));
94}]>;
95def VSPLTB_shuffle_mask : PatLeaf<(build_vector), [{
96  return PPC::isSplatShuffleMask(N, 1);
97}], VSPLTB_get_imm>;
98def VSPLTH_get_imm : SDNodeXForm<build_vector, [{
99  return getI32Imm(PPC::getVSPLTImmediate(N, 2));
100}]>;
101def VSPLTH_shuffle_mask : PatLeaf<(build_vector), [{
102  return PPC::isSplatShuffleMask(N, 2);
103}], VSPLTH_get_imm>;
104def VSPLTW_get_imm : SDNodeXForm<build_vector, [{
105  return getI32Imm(PPC::getVSPLTImmediate(N, 4));
106}]>;
107def VSPLTW_shuffle_mask : PatLeaf<(build_vector), [{
108  return PPC::isSplatShuffleMask(N, 4);
109}], VSPLTW_get_imm>;
110
111
112// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
113def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
114  return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
115}]>;
116def vecspltisb : PatLeaf<(build_vector), [{
117  return PPC::get_VSPLTI_elt(N, 1, *CurDAG).Val != 0;
118}], VSPLTISB_get_imm>;
119
120// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
121def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
122  return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
123}]>;
124def vecspltish : PatLeaf<(build_vector), [{
125  return PPC::get_VSPLTI_elt(N, 2, *CurDAG).Val != 0;
126}], VSPLTISH_get_imm>;
127
128// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
129def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
130  return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
131}]>;
132def vecspltisw : PatLeaf<(build_vector), [{
133  return PPC::get_VSPLTI_elt(N, 4, *CurDAG).Val != 0;
134}], VSPLTISW_get_imm>;
135
136//===----------------------------------------------------------------------===//
137// Helpers for defining instructions that directly correspond to intrinsics.
138
139// VA1a_Int - A VAForm_1a intrinsic definition.
140class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
141  : VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
142              !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
143                       [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
144
145// VX1_Int - A VXForm_1 intrinsic definition.
146class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
147  : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
148             !strconcat(opc, " $vD, $vA, $vB"), VecFP,
149             [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
150
151// VX2_Int - A VXForm_2 intrinsic definition.
152class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
153  : VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB),
154             !strconcat(opc, " $vD, $vB"), VecFP,
155             [(set VRRC:$vD, (IntID VRRC:$vB))]>;
156
157//===----------------------------------------------------------------------===//
158// Instruction Definitions.
159
160def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
161                               [(set VRRC:$rD, (v4f32 (undef)))]>;
162
163let noResults = 1 in {
164def DSS   : DSS_Form<822, (ops u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
165                     "dss $STRM, $A", LdStGeneral /*FIXME*/, []>;
166def DST   : DSS_Form<342, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
167                     "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
168def DSTST : DSS_Form<374, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
169                   "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
170}
171
172def MFVSCR : VXForm_4<1540, (ops VRRC:$vD),
173                      "mfvcr $vD", LdStGeneral,
174                      [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>; 
175def MTVSCR : VXForm_5<1604, (ops VRRC:$vB),
176                      "mtvcr $vB", LdStGeneral,
177                      [(int_ppc_altivec_mtvscr VRRC:$vB)]>; 
178
179let isLoad = 1, PPC970_Unit = 2 in {  // Loads.
180def LVEBX: XForm_1<31,   7, (ops VRRC:$vD, memrr:$src),
181                   "lvebx $vD, $src", LdStGeneral,
182                   [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
183def LVEHX: XForm_1<31,  39, (ops VRRC:$vD, memrr:$src),
184                   "lvehx $vD, $src", LdStGeneral,
185                   [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
186def LVEWX: XForm_1<31,  71, (ops VRRC:$vD, memrr:$src),
187                   "lvewx $vD, $src", LdStGeneral,
188                   [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
189def LVX  : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
190                   "lvx $vD, $src", LdStGeneral,
191                   [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
192def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src),
193                   "lvxl $vD, $src", LdStGeneral,
194                   [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
195}
196
197def LVSL : XForm_1<31,   6, (ops VRRC:$vD, memrr:$src),
198                   "lvsl $vD, $src", LdStGeneral,
199                   [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
200                   PPC970_Unit_LSU;
201def LVSR : XForm_1<31,  38, (ops VRRC:$vD, memrr:$src),
202                   "lvsr $vD, $src", LdStGeneral,
203                   [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
204                   PPC970_Unit_LSU;
205
206let isStore = 1, noResults = 1, PPC970_Unit = 2 in {   // Stores.
207def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
208                   "stvebx $rS, $dst", LdStGeneral,
209                   [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
210def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
211                   "stvehx $rS, $dst", LdStGeneral,
212                   [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
213def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
214                   "stvewx $rS, $dst", LdStGeneral,
215                   [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
216def STVX  : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
217                   "stvx $rS, $dst", LdStGeneral,
218                   [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
219def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst),
220                   "stvxl $rS, $dst", LdStGeneral,
221                   [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
222}
223
224let PPC970_Unit = 5 in {  // VALU Operations.
225// VA-Form instructions.  3-input AltiVec ops.
226def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
227                       "vmaddfp $vD, $vA, $vC, $vB", VecFP,
228                       [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
229                                             VRRC:$vB))]>,
230                       Requires<[FPContractions]>;
231def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
232                       "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
233                       [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
234                                                   VRRC:$vB)))]>,
235                       Requires<[FPContractions]>;
236
237def VMHADDSHS  : VA1a_Int<32, "vmhaddshs",  int_ppc_altivec_vmhaddshs>;
238def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
239def VMLADDUHM  : VA1a_Int<34, "vmladduhm",  int_ppc_altivec_vmladduhm>;
240def VPERM      : VA1a_Int<43, "vperm",      int_ppc_altivec_vperm>;
241def VSEL       : VA1a_Int<42, "vsel",       int_ppc_altivec_vsel>;
242
243// Shuffles.
244def VSLDOI  : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
245                       "vsldoi $vD, $vA, $vB, $SH", VecFP,
246                       [(set VRRC:$vD, 
247                             (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB,
248                                             VSLDOI_shuffle_mask:$SH))]>;
249
250// VX-Form instructions.  AltiVec arithmetic ops.
251def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
252                      "vaddfp $vD, $vA, $vB", VecFP,
253                      [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
254                      
255def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
256                      "vaddubm $vD, $vA, $vB", VecGeneral,
257                      [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
258def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
259                      "vadduhm $vD, $vA, $vB", VecGeneral,
260                      [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
261def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
262                      "vadduwm $vD, $vA, $vB", VecGeneral,
263                      [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
264                      
265def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>;
266def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>;
267def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>;
268def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>;
269def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>;
270def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>;
271def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>;
272                             
273                             
274def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
275                    "vand $vD, $vA, $vB", VecFP,
276                    [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
277def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
278                     "vandc $vD, $vA, $vB", VecFP,
279                     [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
280
281def VCFSX  : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
282                      "vcfsx $vD, $vB, $UIMM", VecFP,
283                      [(set VRRC:$vD,
284                             (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
285def VCFUX  : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
286                      "vcfux $vD, $vB, $UIMM", VecFP,
287                      [(set VRRC:$vD,
288                             (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
289def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
290                      "vctsxs $vD, $vB, $UIMM", VecFP,
291                      [(set VRRC:$vD,
292                             (int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>;
293def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
294                      "vctuxs $vD, $vB, $UIMM", VecFP,
295                      [(set VRRC:$vD,
296                             (int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>;
297def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>;
298def VLOGEFP  : VX2_Int<458, "vlogefp",  int_ppc_altivec_vlogefp>;
299
300def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>;
301def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>;
302def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>;
303def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>;
304def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>;
305def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>;
306
307def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>;
308def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>;
309def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>;
310def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>;
311def VMAXUB : VX1_Int<   2, "vmaxub", int_ppc_altivec_vmaxub>;
312def VMAXUH : VX1_Int<  66, "vmaxuh", int_ppc_altivec_vmaxuh>;
313def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>;
314def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>;
315def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>;
316def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>;
317def VMINSW : VX1_Int< 896, "vminsw", int_ppc_altivec_vminsw>;
318def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>;
319def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>;
320def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>;
321
322def VMRGHB : VXForm_1< 12, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
323                      "vmrghb $vD, $vA, $vB", VecFP,
324                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
325                                             VRRC:$vB, VMRGHB_shuffle_mask))]>;
326def VMRGHH : VXForm_1< 76, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
327                      "vmrghh $vD, $vA, $vB", VecFP,
328                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
329                                             VRRC:$vB, VMRGHH_shuffle_mask))]>;
330def VMRGHW : VXForm_1<140, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
331                      "vmrghw $vD, $vA, $vB", VecFP,
332                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
333                                             VRRC:$vB, VMRGHW_shuffle_mask))]>;
334def VMRGLB : VXForm_1<268, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
335                      "vmrglb $vD, $vA, $vB", VecFP,
336                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
337                                             VRRC:$vB, VMRGLB_shuffle_mask))]>;
338def VMRGLH : VXForm_1<332, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
339                      "vmrglh $vD, $vA, $vB", VecFP,
340                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
341                                             VRRC:$vB, VMRGLH_shuffle_mask))]>;
342def VMRGLW : VXForm_1<396, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
343                      "vmrglw $vD, $vA, $vB", VecFP,
344                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
345                                             VRRC:$vB, VMRGLW_shuffle_mask))]>;
346
347def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
348def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
349def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>;
350def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
351def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
352def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
353
354def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>;
355def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>;
356def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>;
357def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>;
358def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>;
359def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>;
360def VMULOUB : VX1_Int<  8, "vmuloub", int_ppc_altivec_vmuloub>;
361def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>;
362                       
363def VREFP     : VX2_Int<266, "vrefp",     int_ppc_altivec_vrefp>;
364def VRFIM     : VX2_Int<714, "vrfim",     int_ppc_altivec_vrfim>;
365def VRFIN     : VX2_Int<522, "vrfin",     int_ppc_altivec_vrfin>;
366def VRFIP     : VX2_Int<650, "vrfip",     int_ppc_altivec_vrfip>;
367def VRFIZ     : VX2_Int<586, "vrfiz",     int_ppc_altivec_vrfiz>;
368def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
369
370def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>;
371
372def VSUBFP  : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
373                      "vsubfp $vD, $vA, $vB", VecGeneral,
374                      [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
375def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
376                      "vsububm $vD, $vA, $vB", VecGeneral,
377                      [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
378def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
379                      "vsubuhm $vD, $vA, $vB", VecGeneral,
380                      [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
381def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
382                      "vsubuwm $vD, $vA, $vB", VecGeneral,
383                      [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
384                      
385def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>;
386def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>;
387def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>;
388def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>;
389def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>;
390def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>;
391def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>;
392def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>;
393def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>;
394def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>;
395def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>;
396
397def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
398                    "vnor $vD, $vA, $vB", VecFP,
399                    [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
400def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
401                      "vor $vD, $vA, $vB", VecFP,
402                      [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
403def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
404                      "vxor $vD, $vA, $vB", VecFP,
405                      [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
406
407def VRLB   : VX1_Int<   4, "vrlb", int_ppc_altivec_vrlb>;
408def VRLH   : VX1_Int<  68, "vrlh", int_ppc_altivec_vrlh>;
409def VRLW   : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
410
411def VSL    : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >;
412def VSLO   : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
413def VSLB   : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
414def VSLH   : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
415def VSLW   : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
416
417def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
418                      "vspltb $vD, $vB, $UIMM", VecPerm,
419                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
420                                      VSPLTB_shuffle_mask:$UIMM))]>;
421def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
422                      "vsplth $vD, $vB, $UIMM", VecPerm,
423                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
424                                      VSPLTH_shuffle_mask:$UIMM))]>;
425def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
426                      "vspltw $vD, $vB, $UIMM", VecPerm,
427                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
428                                      VSPLTW_shuffle_mask:$UIMM))]>;
429
430def VSR    : VX1_Int< 708, "vsr"  , int_ppc_altivec_vsr>;
431def VSRO   : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
432def VSRAB  : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>;
433def VSRAH  : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>;
434def VSRAW  : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>;
435def VSRB   : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>;
436def VSRH   : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>;
437def VSRW   : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>;
438
439
440def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
441                       "vspltisb $vD, $SIMM", VecPerm,
442                       [(set VRRC:$vD, (v16i8 vecspltisb:$SIMM))]>;
443def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
444                       "vspltish $vD, $SIMM", VecPerm,
445                       [(set VRRC:$vD, (v8i16 vecspltish:$SIMM))]>;
446def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
447                       "vspltisw $vD, $SIMM", VecPerm,
448                       [(set VRRC:$vD, (v4i32 vecspltisw:$SIMM))]>;
449
450// Vector Pack.
451def VPKPX   : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>;
452def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>;
453def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>;
454def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
455def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
456def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
457                       "vpkuhum $vD, $vA, $vB", VecFP,
458                       [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
459                                             VRRC:$vB, VPKUHUM_shuffle_mask))]>;
460def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
461def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
462                       "vpkuwum $vD, $vA, $vB", VecFP,
463                       [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
464                                             VRRC:$vB, VPKUWUM_shuffle_mask))]>;
465def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
466
467// Vector Unpack.
468def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>;
469def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>;
470def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>;
471def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>;
472def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>;
473def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>;
474
475
476// Altivec Comparisons.
477
478class VCMP<bits<10> xo, string asmstr, ValueType Ty>
479  : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
480              [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
481class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
482  : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
483              [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> {
484  let Defs = [CR6];
485  let RC = 1;
486}
487
488// f32 element comparisons.0
489def VCMPBFP   : VCMP <966, "vcmpbfp $vD, $vA, $vB"  , v4f32>;
490def VCMPBFPo  : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
491def VCMPEQFP  : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
492def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
493def VCMPGEFP  : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
494def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
495def VCMPGTFP  : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
496def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
497
498// i8 element comparisons.
499def VCMPEQUB  : VCMP <  6, "vcmpequb $vD, $vA, $vB" , v16i8>;
500def VCMPEQUBo : VCMPo<  6, "vcmpequb. $vD, $vA, $vB", v16i8>;
501def VCMPGTSB  : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
502def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
503def VCMPGTUB  : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
504def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
505
506// i16 element comparisons.
507def VCMPEQUH  : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
508def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
509def VCMPGTSH  : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
510def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
511def VCMPGTUH  : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
512def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
513
514// i32 element comparisons.
515def VCMPEQUW  : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
516def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
517def VCMPGTSW  : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
518def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
519def VCMPGTUW  : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
520def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
521                      
522def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
523                      "vxor $vD, $vD, $vD", VecFP,
524                      [(set VRRC:$vD, (v4i32 immAllZerosV))]>;
525}
526
527//===----------------------------------------------------------------------===//
528// Additional Altivec Patterns
529//
530
531// DS* intrinsics.
532def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
533def : Pat<(int_ppc_altivec_dssall), (DSS 1, 0, 0, 0)>;
534def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM),
535          (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
536def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM),
537          (DST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
538def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM),
539          (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
540def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM),
541          (DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
542
543// Undef.
544def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
545def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
546def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
547
548// Loads.
549def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
550def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
551def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
552def : Pat<(v4f32 (load xoaddr:$src)), (v4f32 (LVX xoaddr:$src))>;
553
554// Stores.
555def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
556          (STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
557def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
558          (STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
559def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
560          (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
561def : Pat<(store (v4f32 VRRC:$rS), xoaddr:$dst),
562          (STVX (v4f32 VRRC:$rS), xoaddr:$dst)>;
563
564// Bit conversions.
565def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
566def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
567def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
568
569def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
570def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
571def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
572
573def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
574def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
575def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
576
577def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
578def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
579def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
580
581// Shuffles.
582
583// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
584def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VSLDOI_unary_shuffle_mask:$in),
585        (VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_unary_shuffle_mask:$in)>;
586def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUWUM_unary_shuffle_mask:$in),
587        (VPKUWUM VRRC:$vA, VRRC:$vA)>;
588def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUHUM_unary_shuffle_mask:$in),
589        (VPKUHUM VRRC:$vA, VRRC:$vA)>;
590
591// Match vmrg*(x,x)
592def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLB_unary_shuffle_mask:$in),
593        (VMRGLB VRRC:$vA, VRRC:$vA)>;
594def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLH_unary_shuffle_mask:$in),
595        (VMRGLH VRRC:$vA, VRRC:$vA)>;
596def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLW_unary_shuffle_mask:$in),
597        (VMRGLW VRRC:$vA, VRRC:$vA)>;
598def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHB_unary_shuffle_mask:$in),
599        (VMRGHB VRRC:$vA, VRRC:$vA)>;
600def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHH_unary_shuffle_mask:$in),
601        (VMRGHH VRRC:$vA, VRRC:$vA)>;
602def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHW_unary_shuffle_mask:$in),
603        (VMRGHW VRRC:$vA, VRRC:$vA)>;
604
605// Logical Operations
606def : Pat<(v16i8 (vnot VRRC:$vA)), (v16i8 (VNOR VRRC:$vA, VRRC:$vA))>;
607def : Pat<(v8i16 (vnot VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>;
608def : Pat<(v4i32 (vnot VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>;
609
610def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>;
611def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>;
612def : Pat<(v16i8 (or  VRRC:$A, VRRC:$B)), (v16i8 (VOR  VRRC:$A, VRRC:$B))>;
613def : Pat<(v8i16 (or  VRRC:$A, VRRC:$B)), (v8i16 (VOR  VRRC:$A, VRRC:$B))>;
614def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>;
615def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>;
616def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>;
617def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>;
618def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))),
619          (v16i8 (VANDC VRRC:$A, VRRC:$B))>;
620def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
621          (v8i16 (VANDC VRRC:$A, VRRC:$B))>;
622
623def : Pat<(fmul VRRC:$vA, VRRC:$vB),
624          (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>; 
625
626// Fused multiply add and multiply sub for packed float.  These are represented
627// separately from the real instructions above, for operations that must have
628// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
629def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
630          (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
631def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
632          (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
633
634def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
635          (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
636def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
637          (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
638
639def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
640          (v16i8 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
641