PPCInstrFormats.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 18 let Size = 4; 19 20 bit PPC64 = 0; // Default value, override with isPPC64 21 22 let Namespace = "PPC"; 23 let Inst{0-5} = opcode; 24 let OutOperandList = OOL; 25 let InOperandList = IOL; 26 let AsmString = asmstr; 27 let Itinerary = itin; 28 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 33 34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 35 /// these must be reflected there! See comments there for what these are. 36 let TSFlags{0} = PPC970_First; 37 let TSFlags{1} = PPC970_Single; 38 let TSFlags{2} = PPC970_Cracked; 39 let TSFlags{5-3} = PPC970_Unit; 40 41 // Fields used for relation models. 42 string BaseName = ""; 43 44 // For cases where multiple instruction definitions really represent the 45 // same underlying instruction but with one definition for 64-bit arguments 46 // and one for 32-bit arguments, this bit breaks the degeneracy between 47 // the two forms and allows TableGen to generate mapping tables. 48 bit Interpretation64Bit = 0; 49} 50 51class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 52class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 53class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 54class PPC970_MicroCode; 55 56class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 57class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 58class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 59class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 60class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 61class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 62class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 63class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 64 65// Two joined instructions; used to emit two adjacent instructions as one. 66// The itinerary from the first instruction is used for scheduling and 67// classification. 68class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 69 InstrItinClass itin> 70 : Instruction { 71 field bits<64> Inst; 72 field bits<64> SoftFail = 0; 73 let Size = 8; 74 75 bit PPC64 = 0; // Default value, override with isPPC64 76 77 let Namespace = "PPC"; 78 let Inst{0-5} = opcode1; 79 let Inst{32-37} = opcode2; 80 let OutOperandList = OOL; 81 let InOperandList = IOL; 82 let AsmString = asmstr; 83 let Itinerary = itin; 84 85 bits<1> PPC970_First = 0; 86 bits<1> PPC970_Single = 0; 87 bits<1> PPC970_Cracked = 0; 88 bits<3> PPC970_Unit = 0; 89 90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 91 /// these must be reflected there! See comments there for what these are. 92 let TSFlags{0} = PPC970_First; 93 let TSFlags{1} = PPC970_Single; 94 let TSFlags{2} = PPC970_Cracked; 95 let TSFlags{5-3} = PPC970_Unit; 96 97 // Fields used for relation models. 98 string BaseName = ""; 99 bit Interpretation64Bit = 0; 100} 101 102// 1.7.1 I-Form 103class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 104 InstrItinClass itin, list<dag> pattern> 105 : I<opcode, OOL, IOL, asmstr, itin> { 106 let Pattern = pattern; 107 bits<24> LI; 108 109 let Inst{6-29} = LI; 110 let Inst{30} = aa; 111 let Inst{31} = lk; 112} 113 114// 1.7.2 B-Form 115class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 118 bits<3> CR; 119 bits<14> BD; 120 121 bits<5> BI; 122 let BI{0-1} = BIBO{5-6}; 123 let BI{2-4} = CR{0-2}; 124 125 let Inst{6-10} = BIBO{4-0}; 126 let Inst{11-15} = BI; 127 let Inst{16-29} = BD; 128 let Inst{30} = aa; 129 let Inst{31} = lk; 130} 131 132class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 133 string asmstr> 134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 135 let BIBO{4-0} = bo; 136 let BIBO{6-5} = 0; 137 let CR = 0; 138} 139 140class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 141 dag OOL, dag IOL, string asmstr> 142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 143 bits<14> BD; 144 145 let Inst{6-10} = bo; 146 let Inst{11-15} = bi; 147 let Inst{16-29} = BD; 148 let Inst{30} = aa; 149 let Inst{31} = lk; 150} 151 152class BForm_3<bits<6> opcode, bit aa, bit lk, 153 dag OOL, dag IOL, string asmstr> 154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 155 bits<5> BO; 156 bits<5> BI; 157 bits<14> BD; 158 159 let Inst{6-10} = BO; 160 let Inst{11-15} = BI; 161 let Inst{16-29} = BD; 162 let Inst{30} = aa; 163 let Inst{31} = lk; 164} 165 166class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<5> BI; 170 bits<14> BD; 171 172 let Inst{6-10} = bo; 173 let Inst{11-15} = BI; 174 let Inst{16-29} = BD; 175 let Inst{30} = aa; 176 let Inst{31} = lk; 177} 178 179// 1.7.3 SC-Form 180class SCForm<bits<6> opcode, bits<1> xo, 181 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 182 list<dag> pattern> 183 : I<opcode, OOL, IOL, asmstr, itin> { 184 bits<7> LEV; 185 186 let Pattern = pattern; 187 188 let Inst{20-26} = LEV; 189 let Inst{30} = xo; 190} 191 192// 1.7.4 D-Form 193class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 194 InstrItinClass itin, list<dag> pattern> 195 : I<opcode, OOL, IOL, asmstr, itin> { 196 bits<5> A; 197 bits<5> B; 198 bits<16> C; 199 200 let Pattern = pattern; 201 202 let Inst{6-10} = A; 203 let Inst{11-15} = B; 204 let Inst{16-31} = C; 205} 206 207class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 208 InstrItinClass itin, list<dag> pattern> 209 : I<opcode, OOL, IOL, asmstr, itin> { 210 bits<5> A; 211 bits<21> Addr; 212 213 let Pattern = pattern; 214 215 let Inst{6-10} = A; 216 let Inst{11-15} = Addr{20-16}; // Base Reg 217 let Inst{16-31} = Addr{15-0}; // Displacement 218} 219 220class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 221 InstrItinClass itin, list<dag> pattern> 222 : I<opcode, OOL, IOL, asmstr, itin> { 223 bits<5> A; 224 bits<16> C; 225 bits<5> B; 226 227 let Pattern = pattern; 228 229 let Inst{6-10} = A; 230 let Inst{11-15} = B; 231 let Inst{16-31} = C; 232} 233 234 235class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 236 InstrItinClass itin, list<dag> pattern> 237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 238 239 // Even though ADDICo does not really have an RC bit, provide 240 // the declaration of one here so that isDOT has something to set. 241 bit RC = 0; 242} 243 244class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 245 InstrItinClass itin, list<dag> pattern> 246 : I<opcode, OOL, IOL, asmstr, itin> { 247 bits<5> A; 248 bits<16> B; 249 250 let Pattern = pattern; 251 252 let Inst{6-10} = A; 253 let Inst{11-15} = 0; 254 let Inst{16-31} = B; 255} 256 257class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 258 InstrItinClass itin, list<dag> pattern> 259 : I<opcode, OOL, IOL, asmstr, itin> { 260 bits<5> B; 261 bits<5> A; 262 bits<16> C; 263 264 let Pattern = pattern; 265 266 let Inst{6-10} = A; 267 let Inst{11-15} = B; 268 let Inst{16-31} = C; 269} 270 271class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 272 InstrItinClass itin, list<dag> pattern> 273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 274 let A = 0; 275 let Addr = 0; 276} 277 278class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 279 string asmstr, InstrItinClass itin, 280 list<dag> pattern> 281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 282 let A = R; 283 let B = R; 284 let C = 0; 285} 286 287class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 288 dag OOL, dag IOL, string asmstr, 289 InstrItinClass itin, list<dag> pattern> 290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 291 bits<5> A; 292 bits<21> Addr; 293 294 let Pattern = pattern; 295 bits<24> LI; 296 297 let Inst{6-29} = LI; 298 let Inst{30} = aa; 299 let Inst{31} = lk; 300 301 let Inst{38-42} = A; 302 let Inst{43-47} = Addr{20-16}; // Base Reg 303 let Inst{48-63} = Addr{15-0}; // Displacement 304} 305 306// This is used to emit BL8+NOP. 307class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 308 dag OOL, dag IOL, string asmstr, 309 InstrItinClass itin, list<dag> pattern> 310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 311 OOL, IOL, asmstr, itin, pattern> { 312 let A = 0; 313 let Addr = 0; 314} 315 316class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 317 InstrItinClass itin> 318 : I<opcode, OOL, IOL, asmstr, itin> { 319 bits<3> BF; 320 bits<1> L; 321 bits<5> RA; 322 bits<16> I; 323 324 let Inst{6-8} = BF; 325 let Inst{9} = 0; 326 let Inst{10} = L; 327 let Inst{11-15} = RA; 328 let Inst{16-31} = I; 329} 330 331class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 332 InstrItinClass itin> 333 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 334 let L = PPC64; 335} 336 337class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 338 InstrItinClass itin> 339 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 340 341class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 342 InstrItinClass itin> 343 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 344 let L = PPC64; 345} 346 347 348// 1.7.5 DS-Form 349class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 350 InstrItinClass itin, list<dag> pattern> 351 : I<opcode, OOL, IOL, asmstr, itin> { 352 bits<5> RST; 353 bits<19> DS_RA; 354 355 let Pattern = pattern; 356 357 let Inst{6-10} = RST; 358 let Inst{11-15} = DS_RA{18-14}; // Register # 359 let Inst{16-29} = DS_RA{13-0}; // Displacement. 360 let Inst{30-31} = xo; 361} 362 363class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 364 InstrItinClass itin, list<dag> pattern> 365 : I<opcode, OOL, IOL, asmstr, itin> { 366 bits<5> RST; 367 bits<14> DS; 368 bits<5> RA; 369 370 let Pattern = pattern; 371 372 let Inst{6-10} = RST; 373 let Inst{11-15} = RA; 374 let Inst{16-29} = DS; 375 let Inst{30-31} = xo; 376} 377 378// 1.7.6 X-Form 379class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 380 InstrItinClass itin, list<dag> pattern> 381 : I<opcode, OOL, IOL, asmstr, itin> { 382 bits<5> RST; 383 bits<5> A; 384 bits<5> B; 385 386 let Pattern = pattern; 387 388 bit RC = 0; // set by isDOT 389 390 let Inst{6-10} = RST; 391 let Inst{11-15} = A; 392 let Inst{16-20} = B; 393 let Inst{21-30} = xo; 394 let Inst{31} = RC; 395} 396 397// This is the same as XForm_base_r3xo, but the first two operands are swapped 398// when code is emitted. 399class XForm_base_r3xo_swapped 400 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 401 InstrItinClass itin> 402 : I<opcode, OOL, IOL, asmstr, itin> { 403 bits<5> A; 404 bits<5> RST; 405 bits<5> B; 406 407 bit RC = 0; // set by isDOT 408 409 let Inst{6-10} = RST; 410 let Inst{11-15} = A; 411 let Inst{16-20} = B; 412 let Inst{21-30} = xo; 413 let Inst{31} = RC; 414} 415 416 417class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 418 InstrItinClass itin, list<dag> pattern> 419 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 420 421class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 422 InstrItinClass itin, list<dag> pattern> 423 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 424 let RST = 0; 425} 426 427class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 428 InstrItinClass itin, list<dag> pattern> 429 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 430 let A = 0; 431 let B = 0; 432} 433 434class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 435 InstrItinClass itin, list<dag> pattern> 436 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 437 let Pattern = pattern; 438} 439 440class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 441 InstrItinClass itin, list<dag> pattern> 442 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 443 444class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 445 InstrItinClass itin, list<dag> pattern> 446 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 447 let Pattern = pattern; 448} 449 450class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 451 InstrItinClass itin, list<dag> pattern> 452 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 453 let B = 0; 454 let Pattern = pattern; 455} 456 457class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 458 InstrItinClass itin> 459 : I<opcode, OOL, IOL, asmstr, itin> { 460 bits<3> BF; 461 bits<1> L; 462 bits<5> RA; 463 bits<5> RB; 464 465 let Inst{6-8} = BF; 466 let Inst{9} = 0; 467 let Inst{10} = L; 468 let Inst{11-15} = RA; 469 let Inst{16-20} = RB; 470 let Inst{21-30} = xo; 471 let Inst{31} = 0; 472} 473 474class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 475 InstrItinClass itin> 476 : I<opcode, OOL, IOL, asmstr, itin> { 477 bits<5> RS; 478 bits<1> L; 479 480 let Inst{6-10} = RS; 481 let Inst{15} = L; 482 let Inst{21-30} = xo; 483} 484 485class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 486 InstrItinClass itin> 487 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 488 let L = PPC64; 489} 490 491class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 492 InstrItinClass itin> 493 : I<opcode, OOL, IOL, asmstr, itin> { 494 bits<3> BF; 495 bits<5> FRA; 496 bits<5> FRB; 497 498 let Inst{6-8} = BF; 499 let Inst{9-10} = 0; 500 let Inst{11-15} = FRA; 501 let Inst{16-20} = FRB; 502 let Inst{21-30} = xo; 503 let Inst{31} = 0; 504} 505 506class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 507 InstrItinClass itin, list<dag> pattern> 508 : I<opcode, OOL, IOL, asmstr, itin> { 509 let Pattern = pattern; 510 let Inst{6-10} = 31; 511 let Inst{11-15} = 0; 512 let Inst{16-20} = 0; 513 let Inst{21-30} = xo; 514 let Inst{31} = 0; 515} 516 517class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 518 string asmstr, InstrItinClass itin, list<dag> pattern> 519 : I<opcode, OOL, IOL, asmstr, itin> { 520 bits<2> L; 521 522 let Pattern = pattern; 523 let Inst{6-8} = 0; 524 let Inst{9-10} = L; 525 let Inst{11-15} = 0; 526 let Inst{16-20} = 0; 527 let Inst{21-30} = xo; 528 let Inst{31} = 0; 529} 530 531class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 532 string asmstr, InstrItinClass itin, list<dag> pattern> 533 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 534 let L = 0; 535} 536 537class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 538 InstrItinClass itin, list<dag> pattern> 539 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 540} 541 542class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 543 InstrItinClass itin, list<dag> pattern> 544 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 545 let A = 0; 546} 547 548class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 549 InstrItinClass itin, list<dag> pattern> 550 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 551} 552 553// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 554// numbers presumably relates to some document, but I haven't found it. 555class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 556 InstrItinClass itin, list<dag> pattern> 557 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 558 let Pattern = pattern; 559 560 bit RC = 0; // set by isDOT 561 562 let Inst{6-10} = RST; 563 let Inst{11-20} = 0; 564 let Inst{21-30} = xo; 565 let Inst{31} = RC; 566} 567class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 568 InstrItinClass itin, list<dag> pattern> 569 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 570 let Pattern = pattern; 571 bits<5> FM; 572 573 bit RC = 0; // set by isDOT 574 575 let Inst{6-10} = FM; 576 let Inst{11-20} = 0; 577 let Inst{21-30} = xo; 578 let Inst{31} = RC; 579} 580 581class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 582 InstrItinClass itin, list<dag> pattern> 583 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 584 let RST = 0; 585 let A = 0; 586 let B = 0; 587} 588 589class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 590 InstrItinClass itin, list<dag> pattern> 591 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 592 let RST = 0; 593 let A = 0; 594} 595 596// XX*-Form (VSX) 597class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 598 InstrItinClass itin, list<dag> pattern> 599 : I<opcode, OOL, IOL, asmstr, itin> { 600 bits<6> XT; 601 bits<5> A; 602 bits<5> B; 603 604 let Pattern = pattern; 605 606 let Inst{6-10} = XT{4-0}; 607 let Inst{11-15} = A; 608 let Inst{16-20} = B; 609 let Inst{21-30} = xo; 610 let Inst{31} = XT{5}; 611} 612 613class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 614 InstrItinClass itin, list<dag> pattern> 615 : I<opcode, OOL, IOL, asmstr, itin> { 616 bits<6> XT; 617 bits<6> XB; 618 619 let Pattern = pattern; 620 621 let Inst{6-10} = XT{4-0}; 622 let Inst{11-15} = 0; 623 let Inst{16-20} = XB{4-0}; 624 let Inst{21-29} = xo; 625 let Inst{30} = XB{5}; 626 let Inst{31} = XT{5}; 627} 628 629class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 630 InstrItinClass itin, list<dag> pattern> 631 : I<opcode, OOL, IOL, asmstr, itin> { 632 bits<3> CR; 633 bits<6> XB; 634 635 let Pattern = pattern; 636 637 let Inst{6-8} = CR; 638 let Inst{9-15} = 0; 639 let Inst{16-20} = XB{4-0}; 640 let Inst{21-29} = xo; 641 let Inst{30} = XB{5}; 642 let Inst{31} = 0; 643} 644 645class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 646 InstrItinClass itin, list<dag> pattern> 647 : I<opcode, OOL, IOL, asmstr, itin> { 648 bits<6> XT; 649 bits<6> XB; 650 bits<2> D; 651 652 let Pattern = pattern; 653 654 let Inst{6-10} = XT{4-0}; 655 let Inst{11-13} = 0; 656 let Inst{14-15} = D; 657 let Inst{16-20} = XB{4-0}; 658 let Inst{21-29} = xo; 659 let Inst{30} = XB{5}; 660 let Inst{31} = XT{5}; 661} 662 663class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 664 InstrItinClass itin, list<dag> pattern> 665 : I<opcode, OOL, IOL, asmstr, itin> { 666 bits<6> XT; 667 bits<6> XA; 668 bits<6> XB; 669 670 let Pattern = pattern; 671 672 let Inst{6-10} = XT{4-0}; 673 let Inst{11-15} = XA{4-0}; 674 let Inst{16-20} = XB{4-0}; 675 let Inst{21-28} = xo; 676 let Inst{29} = XA{5}; 677 let Inst{30} = XB{5}; 678 let Inst{31} = XT{5}; 679} 680 681class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 682 InstrItinClass itin, list<dag> pattern> 683 : I<opcode, OOL, IOL, asmstr, itin> { 684 bits<3> CR; 685 bits<6> XA; 686 bits<6> XB; 687 688 let Pattern = pattern; 689 690 let Inst{6-8} = CR; 691 let Inst{9-10} = 0; 692 let Inst{11-15} = XA{4-0}; 693 let Inst{16-20} = XB{4-0}; 694 let Inst{21-28} = xo; 695 let Inst{29} = XA{5}; 696 let Inst{30} = XB{5}; 697 let Inst{31} = 0; 698} 699 700class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 701 InstrItinClass itin, list<dag> pattern> 702 : I<opcode, OOL, IOL, asmstr, itin> { 703 bits<6> XT; 704 bits<6> XA; 705 bits<6> XB; 706 bits<2> D; 707 708 let Pattern = pattern; 709 710 let Inst{6-10} = XT{4-0}; 711 let Inst{11-15} = XA{4-0}; 712 let Inst{16-20} = XB{4-0}; 713 let Inst{21} = 0; 714 let Inst{22-23} = D; 715 let Inst{24-28} = xo; 716 let Inst{29} = XA{5}; 717 let Inst{30} = XB{5}; 718 let Inst{31} = XT{5}; 719} 720 721class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 722 InstrItinClass itin, list<dag> pattern> 723 : I<opcode, OOL, IOL, asmstr, itin> { 724 bits<6> XT; 725 bits<6> XA; 726 bits<6> XB; 727 728 let Pattern = pattern; 729 730 bit RC = 0; // set by isDOT 731 732 let Inst{6-10} = XT{4-0}; 733 let Inst{11-15} = XA{4-0}; 734 let Inst{16-20} = XB{4-0}; 735 let Inst{21} = RC; 736 let Inst{22-28} = xo; 737 let Inst{29} = XA{5}; 738 let Inst{30} = XB{5}; 739 let Inst{31} = XT{5}; 740} 741 742class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 743 InstrItinClass itin, list<dag> pattern> 744 : I<opcode, OOL, IOL, asmstr, itin> { 745 bits<6> XT; 746 bits<6> XA; 747 bits<6> XB; 748 bits<6> XC; 749 750 let Pattern = pattern; 751 752 let Inst{6-10} = XT{4-0}; 753 let Inst{11-15} = XA{4-0}; 754 let Inst{16-20} = XB{4-0}; 755 let Inst{21-25} = XC{4-0}; 756 let Inst{26-27} = xo; 757 let Inst{28} = XC{5}; 758 let Inst{29} = XA{5}; 759 let Inst{30} = XB{5}; 760 let Inst{31} = XT{5}; 761} 762 763// DCB_Form - Form X instruction, used for dcb* instructions. 764class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 765 InstrItinClass itin, list<dag> pattern> 766 : I<31, OOL, IOL, asmstr, itin> { 767 bits<5> A; 768 bits<5> B; 769 770 let Pattern = pattern; 771 772 let Inst{6-10} = immfield; 773 let Inst{11-15} = A; 774 let Inst{16-20} = B; 775 let Inst{21-30} = xo; 776 let Inst{31} = 0; 777} 778 779 780// DSS_Form - Form X instruction, used for altivec dss* instructions. 781class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr, 782 InstrItinClass itin, list<dag> pattern> 783 : I<31, OOL, IOL, asmstr, itin> { 784 bits<1> T; 785 bits<2> STRM; 786 bits<5> A; 787 bits<5> B; 788 789 let Pattern = pattern; 790 791 let Inst{6} = T; 792 let Inst{7-8} = 0; 793 let Inst{9-10} = STRM; 794 let Inst{11-15} = A; 795 let Inst{16-20} = B; 796 let Inst{21-30} = xo; 797 let Inst{31} = 0; 798} 799 800// 1.7.7 XL-Form 801class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 802 InstrItinClass itin, list<dag> pattern> 803 : I<opcode, OOL, IOL, asmstr, itin> { 804 bits<5> CRD; 805 bits<5> CRA; 806 bits<5> CRB; 807 808 let Pattern = pattern; 809 810 let Inst{6-10} = CRD; 811 let Inst{11-15} = CRA; 812 let Inst{16-20} = CRB; 813 let Inst{21-30} = xo; 814 let Inst{31} = 0; 815} 816 817class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 818 InstrItinClass itin, list<dag> pattern> 819 : I<opcode, OOL, IOL, asmstr, itin> { 820 bits<5> CRD; 821 822 let Pattern = pattern; 823 824 let Inst{6-10} = CRD; 825 let Inst{11-15} = CRD; 826 let Inst{16-20} = CRD; 827 let Inst{21-30} = xo; 828 let Inst{31} = 0; 829} 830 831class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 832 InstrItinClass itin, list<dag> pattern> 833 : I<opcode, OOL, IOL, asmstr, itin> { 834 bits<5> BO; 835 bits<5> BI; 836 bits<2> BH; 837 838 let Pattern = pattern; 839 840 let Inst{6-10} = BO; 841 let Inst{11-15} = BI; 842 let Inst{16-18} = 0; 843 let Inst{19-20} = BH; 844 let Inst{21-30} = xo; 845 let Inst{31} = lk; 846} 847 848class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 849 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 850 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 851 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 852 bits<3> CR; 853 854 let BO = BIBO{4-0}; 855 let BI{0-1} = BIBO{5-6}; 856 let BI{2-4} = CR{0-2}; 857 let BH = 0; 858} 859 860class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 861 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 862 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 863 let BO = bo; 864 let BH = 0; 865} 866 867class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 868 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 869 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 870 let BO = bo; 871 let BI = bi; 872 let BH = 0; 873} 874 875class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 876 InstrItinClass itin> 877 : I<opcode, OOL, IOL, asmstr, itin> { 878 bits<3> BF; 879 bits<3> BFA; 880 881 let Inst{6-8} = BF; 882 let Inst{9-10} = 0; 883 let Inst{11-13} = BFA; 884 let Inst{14-15} = 0; 885 let Inst{16-20} = 0; 886 let Inst{21-30} = xo; 887 let Inst{31} = 0; 888} 889 890// 1.7.8 XFX-Form 891class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 892 InstrItinClass itin> 893 : I<opcode, OOL, IOL, asmstr, itin> { 894 bits<5> RT; 895 bits<10> SPR; 896 897 let Inst{6-10} = RT; 898 let Inst{11} = SPR{4}; 899 let Inst{12} = SPR{3}; 900 let Inst{13} = SPR{2}; 901 let Inst{14} = SPR{1}; 902 let Inst{15} = SPR{0}; 903 let Inst{16} = SPR{9}; 904 let Inst{17} = SPR{8}; 905 let Inst{18} = SPR{7}; 906 let Inst{19} = SPR{6}; 907 let Inst{20} = SPR{5}; 908 let Inst{21-30} = xo; 909 let Inst{31} = 0; 910} 911 912class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 913 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 914 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 915 let SPR = spr; 916} 917 918class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 919 InstrItinClass itin> 920 : I<opcode, OOL, IOL, asmstr, itin> { 921 bits<5> RT; 922 923 let Inst{6-10} = RT; 924 let Inst{11-20} = 0; 925 let Inst{21-30} = xo; 926 let Inst{31} = 0; 927} 928 929class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 930 InstrItinClass itin> 931 : I<opcode, OOL, IOL, asmstr, itin> { 932 bits<8> FXM; 933 bits<5> rS; 934 935 let Inst{6-10} = rS; 936 let Inst{11} = 0; 937 let Inst{12-19} = FXM; 938 let Inst{20} = 0; 939 let Inst{21-30} = xo; 940 let Inst{31} = 0; 941} 942 943class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 944 InstrItinClass itin> 945 : I<opcode, OOL, IOL, asmstr, itin> { 946 bits<5> ST; 947 bits<8> FXM; 948 949 let Inst{6-10} = ST; 950 let Inst{11} = 1; 951 let Inst{12-19} = FXM; 952 let Inst{20} = 0; 953 let Inst{21-30} = xo; 954 let Inst{31} = 0; 955} 956 957class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 958 InstrItinClass itin> 959 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 960 961class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 962 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 963 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 964 let SPR = spr; 965} 966 967// XFL-Form - MTFSF 968// This is probably 1.7.9, but I don't have the reference that uses this 969// numbering scheme... 970class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 971 InstrItinClass itin, list<dag>pattern> 972 : I<opcode, OOL, IOL, asmstr, itin> { 973 bits<8> FM; 974 bits<5> rT; 975 976 bit RC = 0; // set by isDOT 977 let Pattern = pattern; 978 979 let Inst{6} = 0; 980 let Inst{7-14} = FM; 981 let Inst{15} = 0; 982 let Inst{16-20} = rT; 983 let Inst{21-30} = xo; 984 let Inst{31} = RC; 985} 986 987// 1.7.10 XS-Form - SRADI. 988class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 989 InstrItinClass itin, list<dag> pattern> 990 : I<opcode, OOL, IOL, asmstr, itin> { 991 bits<5> A; 992 bits<5> RS; 993 bits<6> SH; 994 995 bit RC = 0; // set by isDOT 996 let Pattern = pattern; 997 998 let Inst{6-10} = RS; 999 let Inst{11-15} = A; 1000 let Inst{16-20} = SH{4,3,2,1,0}; 1001 let Inst{21-29} = xo; 1002 let Inst{30} = SH{5}; 1003 let Inst{31} = RC; 1004} 1005 1006// 1.7.11 XO-Form 1007class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1008 InstrItinClass itin, list<dag> pattern> 1009 : I<opcode, OOL, IOL, asmstr, itin> { 1010 bits<5> RT; 1011 bits<5> RA; 1012 bits<5> RB; 1013 1014 let Pattern = pattern; 1015 1016 bit RC = 0; // set by isDOT 1017 1018 let Inst{6-10} = RT; 1019 let Inst{11-15} = RA; 1020 let Inst{16-20} = RB; 1021 let Inst{21} = oe; 1022 let Inst{22-30} = xo; 1023 let Inst{31} = RC; 1024} 1025 1026class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1027 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1028 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1029 let RB = 0; 1030} 1031 1032// 1.7.12 A-Form 1033class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1034 InstrItinClass itin, list<dag> pattern> 1035 : I<opcode, OOL, IOL, asmstr, itin> { 1036 bits<5> FRT; 1037 bits<5> FRA; 1038 bits<5> FRC; 1039 bits<5> FRB; 1040 1041 let Pattern = pattern; 1042 1043 bit RC = 0; // set by isDOT 1044 1045 let Inst{6-10} = FRT; 1046 let Inst{11-15} = FRA; 1047 let Inst{16-20} = FRB; 1048 let Inst{21-25} = FRC; 1049 let Inst{26-30} = xo; 1050 let Inst{31} = RC; 1051} 1052 1053class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1054 InstrItinClass itin, list<dag> pattern> 1055 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1056 let FRC = 0; 1057} 1058 1059class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1060 InstrItinClass itin, list<dag> pattern> 1061 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1062 let FRB = 0; 1063} 1064 1065class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1066 InstrItinClass itin, list<dag> pattern> 1067 : I<opcode, OOL, IOL, asmstr, itin> { 1068 bits<5> RT; 1069 bits<5> RA; 1070 bits<5> RB; 1071 bits<5> COND; 1072 1073 let Pattern = pattern; 1074 1075 let Inst{6-10} = RT; 1076 let Inst{11-15} = RA; 1077 let Inst{16-20} = RB; 1078 let Inst{21-25} = COND; 1079 let Inst{26-30} = xo; 1080 let Inst{31} = 0; 1081} 1082 1083// 1.7.13 M-Form 1084class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1085 InstrItinClass itin, list<dag> pattern> 1086 : I<opcode, OOL, IOL, asmstr, itin> { 1087 bits<5> RA; 1088 bits<5> RS; 1089 bits<5> RB; 1090 bits<5> MB; 1091 bits<5> ME; 1092 1093 let Pattern = pattern; 1094 1095 bit RC = 0; // set by isDOT 1096 1097 let Inst{6-10} = RS; 1098 let Inst{11-15} = RA; 1099 let Inst{16-20} = RB; 1100 let Inst{21-25} = MB; 1101 let Inst{26-30} = ME; 1102 let Inst{31} = RC; 1103} 1104 1105class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1106 InstrItinClass itin, list<dag> pattern> 1107 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1108} 1109 1110// 1.7.14 MD-Form 1111class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1112 InstrItinClass itin, list<dag> pattern> 1113 : I<opcode, OOL, IOL, asmstr, itin> { 1114 bits<5> RA; 1115 bits<5> RS; 1116 bits<6> SH; 1117 bits<6> MBE; 1118 1119 let Pattern = pattern; 1120 1121 bit RC = 0; // set by isDOT 1122 1123 let Inst{6-10} = RS; 1124 let Inst{11-15} = RA; 1125 let Inst{16-20} = SH{4,3,2,1,0}; 1126 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1127 let Inst{27-29} = xo; 1128 let Inst{30} = SH{5}; 1129 let Inst{31} = RC; 1130} 1131 1132class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1133 InstrItinClass itin, list<dag> pattern> 1134 : I<opcode, OOL, IOL, asmstr, itin> { 1135 bits<5> RA; 1136 bits<5> RS; 1137 bits<5> RB; 1138 bits<6> MBE; 1139 1140 let Pattern = pattern; 1141 1142 bit RC = 0; // set by isDOT 1143 1144 let Inst{6-10} = RS; 1145 let Inst{11-15} = RA; 1146 let Inst{16-20} = RB; 1147 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1148 let Inst{27-30} = xo; 1149 let Inst{31} = RC; 1150} 1151 1152 1153// E-1 VA-Form 1154 1155// VAForm_1 - DACB ordering. 1156class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1157 InstrItinClass itin, list<dag> pattern> 1158 : I<4, OOL, IOL, asmstr, itin> { 1159 bits<5> VD; 1160 bits<5> VA; 1161 bits<5> VC; 1162 bits<5> VB; 1163 1164 let Pattern = pattern; 1165 1166 let Inst{6-10} = VD; 1167 let Inst{11-15} = VA; 1168 let Inst{16-20} = VB; 1169 let Inst{21-25} = VC; 1170 let Inst{26-31} = xo; 1171} 1172 1173// VAForm_1a - DABC ordering. 1174class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1175 InstrItinClass itin, list<dag> pattern> 1176 : I<4, OOL, IOL, asmstr, itin> { 1177 bits<5> VD; 1178 bits<5> VA; 1179 bits<5> VB; 1180 bits<5> VC; 1181 1182 let Pattern = pattern; 1183 1184 let Inst{6-10} = VD; 1185 let Inst{11-15} = VA; 1186 let Inst{16-20} = VB; 1187 let Inst{21-25} = VC; 1188 let Inst{26-31} = xo; 1189} 1190 1191class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1192 InstrItinClass itin, list<dag> pattern> 1193 : I<4, OOL, IOL, asmstr, itin> { 1194 bits<5> VD; 1195 bits<5> VA; 1196 bits<5> VB; 1197 bits<4> SH; 1198 1199 let Pattern = pattern; 1200 1201 let Inst{6-10} = VD; 1202 let Inst{11-15} = VA; 1203 let Inst{16-20} = VB; 1204 let Inst{21} = 0; 1205 let Inst{22-25} = SH; 1206 let Inst{26-31} = xo; 1207} 1208 1209// E-2 VX-Form 1210class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1211 InstrItinClass itin, list<dag> pattern> 1212 : I<4, OOL, IOL, asmstr, itin> { 1213 bits<5> VD; 1214 bits<5> VA; 1215 bits<5> VB; 1216 1217 let Pattern = pattern; 1218 1219 let Inst{6-10} = VD; 1220 let Inst{11-15} = VA; 1221 let Inst{16-20} = VB; 1222 let Inst{21-31} = xo; 1223} 1224 1225class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1226 InstrItinClass itin, list<dag> pattern> 1227 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1228 let VA = VD; 1229 let VB = VD; 1230} 1231 1232 1233class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1234 InstrItinClass itin, list<dag> pattern> 1235 : I<4, OOL, IOL, asmstr, itin> { 1236 bits<5> VD; 1237 bits<5> VB; 1238 1239 let Pattern = pattern; 1240 1241 let Inst{6-10} = VD; 1242 let Inst{11-15} = 0; 1243 let Inst{16-20} = VB; 1244 let Inst{21-31} = xo; 1245} 1246 1247class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1248 InstrItinClass itin, list<dag> pattern> 1249 : I<4, OOL, IOL, asmstr, itin> { 1250 bits<5> VD; 1251 bits<5> IMM; 1252 1253 let Pattern = pattern; 1254 1255 let Inst{6-10} = VD; 1256 let Inst{11-15} = IMM; 1257 let Inst{16-20} = 0; 1258 let Inst{21-31} = xo; 1259} 1260 1261/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1262class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1263 InstrItinClass itin, list<dag> pattern> 1264 : I<4, OOL, IOL, asmstr, itin> { 1265 bits<5> VD; 1266 1267 let Pattern = pattern; 1268 1269 let Inst{6-10} = VD; 1270 let Inst{11-15} = 0; 1271 let Inst{16-20} = 0; 1272 let Inst{21-31} = xo; 1273} 1274 1275/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1276class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1277 InstrItinClass itin, list<dag> pattern> 1278 : I<4, OOL, IOL, asmstr, itin> { 1279 bits<5> VB; 1280 1281 let Pattern = pattern; 1282 1283 let Inst{6-10} = 0; 1284 let Inst{11-15} = 0; 1285 let Inst{16-20} = VB; 1286 let Inst{21-31} = xo; 1287} 1288 1289// E-4 VXR-Form 1290class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 1291 InstrItinClass itin, list<dag> pattern> 1292 : I<4, OOL, IOL, asmstr, itin> { 1293 bits<5> VD; 1294 bits<5> VA; 1295 bits<5> VB; 1296 bit RC = 0; 1297 1298 let Pattern = pattern; 1299 1300 let Inst{6-10} = VD; 1301 let Inst{11-15} = VA; 1302 let Inst{16-20} = VB; 1303 let Inst{21} = RC; 1304 let Inst{22-31} = xo; 1305} 1306 1307//===----------------------------------------------------------------------===// 1308class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 1309 : I<0, OOL, IOL, asmstr, NoItinerary> { 1310 let isCodeGenOnly = 1; 1311 let PPC64 = 0; 1312 let Pattern = pattern; 1313 let Inst{31-0} = 0; 1314} 1315