PPCInstrFormats.td revision 94e509caeab08edb27849ea9be5dc80e74d95f38
1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 18 bit PPC64 = 0; // Default value, override with isPPC64 19 20 let Name = ""; 21 let Namespace = "PPC"; 22 let Inst{0-5} = opcode; 23 let OperandList = OL; 24 let AsmString = asmstr; 25 let Itinerary = itin; 26 27 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 28 /// these must be reflected there! See comments there for what these are. 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 33} 34 35class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 36class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 37class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 38class PPC970_MicroCode; 39 40class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 41class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 42class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 43class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 44class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 45class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 46class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 47class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 48 49 50// 1.7.1 I-Form 51class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr, 52 InstrItinClass itin, list<dag> pattern> 53 : I<opcode, OL, asmstr, itin> { 54 let Pattern = pattern; 55 bits<24> LI; 56 57 let Inst{6-29} = LI; 58 let Inst{30} = aa; 59 let Inst{31} = lk; 60} 61 62// 1.7.2 B-Form 63class BForm<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode, dag OL, 64 string asmstr, InstrItinClass itin> 65 : I<opcode, OL, asmstr, itin> { 66 bits<3> CR; 67 bits<14> BD; 68 69 let Inst{6-10} = bo; 70 let Inst{11-13} = CR; 71 let Inst{14-15} = bicode; 72 let Inst{16-29} = BD; 73 let Inst{30} = aa; 74 let Inst{31} = lk; 75} 76 77// 1.7.4 D-Form 78class DForm_base<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, 79 list<dag> pattern> 80 : I<opcode, OL, asmstr, itin> { 81 bits<5> A; 82 bits<5> B; 83 bits<16> C; 84 85 let Pattern = pattern; 86 87 let Inst{6-10} = A; 88 let Inst{11-15} = B; 89 let Inst{16-31} = C; 90} 91 92class DForm_1<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, 93 list<dag> pattern> 94 : I<opcode, OL, asmstr, itin> { 95 bits<5> A; 96 bits<16> C; 97 bits<5> B; 98 99 let Pattern = pattern; 100 101 let Inst{6-10} = A; 102 let Inst{11-15} = B; 103 let Inst{16-31} = C; 104} 105 106class DForm_2<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, 107 list<dag> pattern> 108 : DForm_base<opcode, OL, asmstr, itin, pattern>; 109 110class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, 111 list<dag> pattern> 112 : I<opcode, OL, asmstr, itin> { 113 bits<5> A; 114 bits<16> B; 115 116 let Pattern = pattern; 117 118 let Inst{6-10} = A; 119 let Inst{11-15} = 0; 120 let Inst{16-31} = B; 121} 122 123// Currently we make the use/def reg distinction in ISel, not tablegen 124class DForm_3<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, 125 list<dag> pattern> 126 : DForm_1<opcode, OL, asmstr, itin, pattern>; 127 128class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, 129 list<dag> pattern> 130 : I<opcode, OL, asmstr, itin> { 131 bits<5> B; 132 bits<5> A; 133 bits<16> C; 134 135 let Pattern = pattern; 136 137 let Inst{6-10} = A; 138 let Inst{11-15} = B; 139 let Inst{16-31} = C; 140} 141 142class DForm_4_zero<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, 143 list<dag> pattern> 144 : DForm_1<opcode, OL, asmstr, itin, pattern> { 145 let A = 0; 146 let B = 0; 147 let C = 0; 148} 149 150class DForm_5<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> 151 : I<opcode, OL, asmstr, itin> { 152 bits<3> BF; 153 bits<1> L; 154 bits<5> RA; 155 bits<16> I; 156 157 let Inst{6-8} = BF; 158 let Inst{9} = 0; 159 let Inst{10} = L; 160 let Inst{11-15} = RA; 161 let Inst{16-31} = I; 162} 163 164class DForm_5_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> 165 : DForm_5<opcode, OL, asmstr, itin> { 166 let L = PPC64; 167} 168 169class DForm_6<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> 170 : DForm_5<opcode, OL, asmstr, itin>; 171 172class DForm_6_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> 173 : DForm_6<opcode, OL, asmstr, itin> { 174 let L = PPC64; 175} 176 177 178// 1.7.5 DS-Form 179class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr, 180 InstrItinClass itin, list<dag> pattern> 181 : I<opcode, OL, asmstr, itin> { 182 bits<5> RST; 183 bits<14> DS; 184 bits<5> RA; 185 186 let Pattern = pattern; 187 188 let Inst{6-10} = RST; 189 let Inst{11-15} = RA; 190 let Inst{16-29} = DS; 191 let Inst{30-31} = xo; 192} 193 194// 1.7.6 X-Form 195class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 196 InstrItinClass itin, list<dag> pattern> 197 : I<opcode, OL, asmstr, itin> { 198 bits<5> RST; 199 bits<5> A; 200 bits<5> B; 201 202 let Pattern = pattern; 203 204 bit RC = 0; // set by isDOT 205 206 let Inst{6-10} = RST; 207 let Inst{11-15} = A; 208 let Inst{16-20} = B; 209 let Inst{21-30} = xo; 210 let Inst{31} = RC; 211} 212 213// This is the same as XForm_base_r3xo, but the first two operands are swapped 214// when code is emitted. 215class XForm_base_r3xo_swapped 216 <bits<6> opcode, bits<10> xo, dag OL, string asmstr, 217 InstrItinClass itin> 218 : I<opcode, OL, asmstr, itin> { 219 bits<5> A; 220 bits<5> RST; 221 bits<5> B; 222 223 bit RC = 0; // set by isDOT 224 225 let Inst{6-10} = RST; 226 let Inst{11-15} = A; 227 let Inst{16-20} = B; 228 let Inst{21-30} = xo; 229 let Inst{31} = RC; 230} 231 232 233class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 234 InstrItinClass itin, list<dag> pattern> 235 : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>; 236 237class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 238 InstrItinClass itin, list<dag> pattern> 239 : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> { 240 let Pattern = pattern; 241} 242 243class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 244 InstrItinClass itin, list<dag> pattern> 245 : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>; 246 247class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 248 InstrItinClass itin, list<dag> pattern> 249 : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> { 250 let Pattern = pattern; 251} 252 253class XForm_11<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 254 InstrItinClass itin, list<dag> pattern> 255 : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> { 256 let B = 0; 257 let Pattern = pattern; 258} 259 260class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 261 InstrItinClass itin> 262 : I<opcode, OL, asmstr, itin> { 263 bits<3> BF; 264 bits<1> L; 265 bits<5> RA; 266 bits<5> RB; 267 268 let Inst{6-8} = BF; 269 let Inst{9} = 0; 270 let Inst{10} = L; 271 let Inst{11-15} = RA; 272 let Inst{16-20} = RB; 273 let Inst{21-30} = xo; 274 let Inst{31} = 0; 275} 276 277class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 278 InstrItinClass itin> 279 : XForm_16<opcode, xo, OL, asmstr, itin> { 280 let L = PPC64; 281} 282 283class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 284 InstrItinClass itin> 285 : I<opcode, OL, asmstr, itin> { 286 bits<3> BF; 287 bits<5> FRA; 288 bits<5> FRB; 289 290 let Inst{6-8} = BF; 291 let Inst{9-10} = 0; 292 let Inst{11-15} = FRA; 293 let Inst{16-20} = FRB; 294 let Inst{21-30} = xo; 295 let Inst{31} = 0; 296} 297 298class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 299 InstrItinClass itin, list<dag> pattern> 300 : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> { 301} 302 303class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 304 InstrItinClass itin, list<dag> pattern> 305 : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> { 306 let A = 0; 307} 308 309class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 310 InstrItinClass itin, list<dag> pattern> 311 : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> { 312} 313 314// DCB_Form - Form X instruction, used for dcb* instructions. 315class DCB_Form<bits<10> xo, bits<5> immfield, dag OL, string asmstr, 316 InstrItinClass itin, list<dag> pattern> 317 : I<31, OL, asmstr, itin> { 318 bits<5> A; 319 bits<5> B; 320 321 let Pattern = pattern; 322 323 let Inst{6-10} = immfield; 324 let Inst{11-15} = A; 325 let Inst{16-20} = B; 326 let Inst{21-30} = xo; 327 let Inst{31} = 0; 328} 329 330 331// DSS_Form - Form X instruction, used for altivec dss* instructions. 332class DSS_Form<bits<10> xo, dag OL, string asmstr, 333 InstrItinClass itin, list<dag> pattern> 334 : I<31, OL, asmstr, itin> { 335 bits<1> T; 336 bits<2> STRM; 337 bits<5> A; 338 bits<5> B; 339 340 let Pattern = pattern; 341 342 let Inst{6} = T; 343 let Inst{7-8} = 0; 344 let Inst{9-10} = STRM; 345 let Inst{11-15} = A; 346 let Inst{16-20} = B; 347 let Inst{21-30} = xo; 348 let Inst{31} = 0; 349} 350 351// 1.7.7 XL-Form 352class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 353 InstrItinClass itin> 354 : I<opcode, OL, asmstr, itin> { 355 bits<3> CRD; 356 bits<2> CRDb; 357 bits<3> CRA; 358 bits<2> CRAb; 359 bits<3> CRB; 360 bits<2> CRBb; 361 362 let Inst{6-8} = CRD; 363 let Inst{9-10} = CRDb; 364 let Inst{11-13} = CRA; 365 let Inst{14-15} = CRAb; 366 let Inst{16-18} = CRB; 367 let Inst{19-20} = CRBb; 368 let Inst{21-30} = xo; 369 let Inst{31} = 0; 370} 371 372class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr, 373 InstrItinClass itin, list<dag> pattern> 374 : I<opcode, OL, asmstr, itin> { 375 bits<5> BO; 376 bits<5> BI; 377 bits<2> BH; 378 379 let Pattern = pattern; 380 381 let Inst{6-10} = BO; 382 let Inst{11-15} = BI; 383 let Inst{16-18} = 0; 384 let Inst{19-20} = BH; 385 let Inst{21-30} = xo; 386 let Inst{31} = lk; 387} 388 389class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 390 dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> 391 : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> { 392 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 393 bits<3> CR; 394 395 let BO = BIBO{2-6}; 396 let BI{0-1} = BIBO{0-1}; 397 let BI{2-4} = CR; 398 let BH = 0; 399} 400 401 402class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 403 dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> 404 : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> { 405 let BO = bo; 406 let BI = bi; 407 let BH = 0; 408} 409 410class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 411 InstrItinClass itin> 412 : I<opcode, OL, asmstr, itin> { 413 bits<3> BF; 414 bits<3> BFA; 415 416 let Inst{6-8} = BF; 417 let Inst{9-10} = 0; 418 let Inst{11-13} = BFA; 419 let Inst{14-15} = 0; 420 let Inst{16-20} = 0; 421 let Inst{21-30} = xo; 422 let Inst{31} = 0; 423} 424 425// 1.7.8 XFX-Form 426class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 427 InstrItinClass itin> 428 : I<opcode, OL, asmstr, itin> { 429 bits<5> RT; 430 bits<10> SPR; 431 432 let Inst{6-10} = RT; 433 let Inst{11} = SPR{4}; 434 let Inst{12} = SPR{3}; 435 let Inst{13} = SPR{2}; 436 let Inst{14} = SPR{1}; 437 let Inst{15} = SPR{0}; 438 let Inst{16} = SPR{9}; 439 let Inst{17} = SPR{8}; 440 let Inst{18} = SPR{7}; 441 let Inst{19} = SPR{6}; 442 let Inst{20} = SPR{5}; 443 let Inst{21-30} = xo; 444 let Inst{31} = 0; 445} 446 447class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 448 dag OL, string asmstr, InstrItinClass itin> 449 : XFXForm_1<opcode, xo, OL, asmstr, itin> { 450 let SPR = spr; 451} 452 453class XFXForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 454 InstrItinClass itin> 455 : I<opcode, OL, asmstr, itin> { 456 bits<5> RT; 457 458 let Inst{6-10} = RT; 459 let Inst{11-20} = 0; 460 let Inst{21-30} = xo; 461 let Inst{31} = 0; 462} 463 464class XFXForm_5<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 465 InstrItinClass itin> 466 : I<opcode, OL, asmstr, itin> { 467 bits<8> FXM; 468 bits<5> ST; 469 470 let Inst{6-10} = ST; 471 let Inst{11} = 0; 472 let Inst{12-19} = FXM; 473 let Inst{20} = 0; 474 let Inst{21-30} = xo; 475 let Inst{31} = 0; 476} 477 478class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 479 InstrItinClass itin> 480 : I<opcode, OL, asmstr, itin> { 481 bits<5> ST; 482 bits<8> FXM; 483 484 let Inst{6-10} = ST; 485 let Inst{11} = 1; 486 let Inst{12-19} = FXM; 487 let Inst{20} = 0; 488 let Inst{21-30} = xo; 489 let Inst{31} = 0; 490} 491 492class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 493 InstrItinClass itin> 494 : XFXForm_1<opcode, xo, OL, asmstr, itin>; 495 496class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 497 dag OL, string asmstr, InstrItinClass itin> 498 : XFXForm_7<opcode, xo, OL, asmstr, itin> { 499 let SPR = spr; 500} 501 502// 1.7.10 XS-Form 503class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr, 504 InstrItinClass itin, list<dag> pattern> 505 : I<opcode, OL, asmstr, itin> { 506 bits<5> RS; 507 bits<5> A; 508 bits<6> SH; 509 510 bit RC = 0; // set by isDOT 511 let Pattern = pattern; 512 513 let Inst{6-10} = RS; 514 let Inst{11-15} = A; 515 let Inst{16-20} = SH{1-5}; 516 let Inst{21-29} = xo; 517 let Inst{30} = SH{0}; 518 let Inst{31} = RC; 519} 520 521// 1.7.11 XO-Form 522class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr, 523 InstrItinClass itin, list<dag> pattern> 524 : I<opcode, OL, asmstr, itin> { 525 bits<5> RT; 526 bits<5> RA; 527 bits<5> RB; 528 529 let Pattern = pattern; 530 531 bit RC = 0; // set by isDOT 532 533 let Inst{6-10} = RT; 534 let Inst{11-15} = RA; 535 let Inst{16-20} = RB; 536 let Inst{21} = oe; 537 let Inst{22-30} = xo; 538 let Inst{31} = RC; 539} 540 541class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 542 dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> 543 : XOForm_1<opcode, xo, oe, OL, asmstr, itin, pattern> { 544 let RB = 0; 545} 546 547// 1.7.12 A-Form 548class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr, 549 InstrItinClass itin, list<dag> pattern> 550 : I<opcode, OL, asmstr, itin> { 551 bits<5> FRT; 552 bits<5> FRA; 553 bits<5> FRC; 554 bits<5> FRB; 555 556 let Pattern = pattern; 557 558 bit RC = 0; // set by isDOT 559 560 let Inst{6-10} = FRT; 561 let Inst{11-15} = FRA; 562 let Inst{16-20} = FRB; 563 let Inst{21-25} = FRC; 564 let Inst{26-30} = xo; 565 let Inst{31} = RC; 566} 567 568class AForm_2<bits<6> opcode, bits<5> xo, dag OL, string asmstr, 569 InstrItinClass itin, list<dag> pattern> 570 : AForm_1<opcode, xo, OL, asmstr, itin, pattern> { 571 let FRC = 0; 572} 573 574class AForm_3<bits<6> opcode, bits<5> xo, dag OL, string asmstr, 575 InstrItinClass itin, list<dag> pattern> 576 : AForm_1<opcode, xo, OL, asmstr, itin, pattern> { 577 let FRB = 0; 578} 579 580// 1.7.13 M-Form 581class MForm_1<bits<6> opcode, dag OL, string asmstr, 582 InstrItinClass itin, list<dag> pattern> 583 : I<opcode, OL, asmstr, itin> { 584 bits<5> RA; 585 bits<5> RS; 586 bits<5> RB; 587 bits<5> MB; 588 bits<5> ME; 589 590 let Pattern = pattern; 591 592 bit RC = 0; // set by isDOT 593 594 let Inst{6-10} = RS; 595 let Inst{11-15} = RA; 596 let Inst{16-20} = RB; 597 let Inst{21-25} = MB; 598 let Inst{26-30} = ME; 599 let Inst{31} = RC; 600} 601 602class MForm_2<bits<6> opcode, dag OL, string asmstr, 603 InstrItinClass itin, list<dag> pattern> 604 : MForm_1<opcode, OL, asmstr, itin, pattern> { 605} 606 607// 1.7.14 MD-Form 608class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr, 609 InstrItinClass itin, list<dag> pattern> 610 : I<opcode, OL, asmstr, itin> { 611 bits<5> RA; 612 bits<5> RS; 613 bits<6> SH; 614 bits<6> MBE; 615 616 let Pattern = pattern; 617 618 bit RC = 0; // set by isDOT 619 620 let Inst{6-10} = RS; 621 let Inst{11-15} = RA; 622 let Inst{16-20} = { SH{4}, SH{3}, SH{2}, SH{1}, SH{0} }; 623 let Inst{21-26} = { MBE{4}, MBE{3}, MBE{2}, MBE{1}, MBE{0}, MBE{5} }; 624 let Inst{27-29} = xo; 625 let Inst{30} = SH{5}; 626 let Inst{31} = RC; 627} 628 629 630 631// E-1 VA-Form 632 633// VAForm_1 - DACB ordering. 634class VAForm_1<bits<6> xo, dag OL, string asmstr, 635 InstrItinClass itin, list<dag> pattern> 636 : I<4, OL, asmstr, itin> { 637 bits<5> VD; 638 bits<5> VA; 639 bits<5> VC; 640 bits<5> VB; 641 642 let Pattern = pattern; 643 644 let Inst{6-10} = VD; 645 let Inst{11-15} = VA; 646 let Inst{16-20} = VB; 647 let Inst{21-25} = VC; 648 let Inst{26-31} = xo; 649} 650 651// VAForm_1a - DABC ordering. 652class VAForm_1a<bits<6> xo, dag OL, string asmstr, 653 InstrItinClass itin, list<dag> pattern> 654 : I<4, OL, asmstr, itin> { 655 bits<5> VD; 656 bits<5> VA; 657 bits<5> VB; 658 bits<5> VC; 659 660 let Pattern = pattern; 661 662 let Inst{6-10} = VD; 663 let Inst{11-15} = VA; 664 let Inst{16-20} = VB; 665 let Inst{21-25} = VC; 666 let Inst{26-31} = xo; 667} 668 669class VAForm_2<bits<6> xo, dag OL, string asmstr, 670 InstrItinClass itin, list<dag> pattern> 671 : I<4, OL, asmstr, itin> { 672 bits<5> VD; 673 bits<5> VA; 674 bits<5> VB; 675 bits<4> SH; 676 677 let Pattern = pattern; 678 679 let Inst{6-10} = VD; 680 let Inst{11-15} = VA; 681 let Inst{16-20} = VB; 682 let Inst{21} = 0; 683 let Inst{22-25} = SH; 684 let Inst{26-31} = xo; 685} 686 687// E-2 VX-Form 688class VXForm_1<bits<11> xo, dag OL, string asmstr, 689 InstrItinClass itin, list<dag> pattern> 690 : I<4, OL, asmstr, itin> { 691 bits<5> VD; 692 bits<5> VA; 693 bits<5> VB; 694 695 let Pattern = pattern; 696 697 let Inst{6-10} = VD; 698 let Inst{11-15} = VA; 699 let Inst{16-20} = VB; 700 let Inst{21-31} = xo; 701} 702 703class VXForm_setzero<bits<11> xo, dag OL, string asmstr, 704 InstrItinClass itin, list<dag> pattern> 705 : VXForm_1<xo, OL, asmstr, itin, pattern> { 706 let VA = VD; 707 let VB = VD; 708} 709 710 711class VXForm_2<bits<11> xo, dag OL, string asmstr, 712 InstrItinClass itin, list<dag> pattern> 713 : I<4, OL, asmstr, itin> { 714 bits<5> VD; 715 bits<5> VB; 716 717 let Pattern = pattern; 718 719 let Inst{6-10} = VD; 720 let Inst{11-15} = 0; 721 let Inst{16-20} = VB; 722 let Inst{21-31} = xo; 723} 724 725class VXForm_3<bits<11> xo, dag OL, string asmstr, 726 InstrItinClass itin, list<dag> pattern> 727 : I<4, OL, asmstr, itin> { 728 bits<5> VD; 729 bits<5> IMM; 730 731 let Pattern = pattern; 732 733 let Inst{6-10} = VD; 734 let Inst{11-15} = IMM; 735 let Inst{16-20} = 0; 736 let Inst{21-31} = xo; 737} 738 739/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 740class VXForm_4<bits<11> xo, dag OL, string asmstr, 741 InstrItinClass itin, list<dag> pattern> 742 : I<4, OL, asmstr, itin> { 743 bits<5> VD; 744 745 let Pattern = pattern; 746 747 let Inst{6-10} = VD; 748 let Inst{11-15} = 0; 749 let Inst{16-20} = 0; 750 let Inst{21-31} = xo; 751} 752 753/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 754class VXForm_5<bits<11> xo, dag OL, string asmstr, 755 InstrItinClass itin, list<dag> pattern> 756 : I<4, OL, asmstr, itin> { 757 bits<5> VB; 758 759 let Pattern = pattern; 760 761 let Inst{6-10} = 0; 762 let Inst{11-15} = 0; 763 let Inst{16-20} = VB; 764 let Inst{21-31} = xo; 765} 766 767// E-4 VXR-Form 768class VXRForm_1<bits<10> xo, dag OL, string asmstr, 769 InstrItinClass itin, list<dag> pattern> 770 : I<4, OL, asmstr, itin> { 771 bits<5> VD; 772 bits<5> VA; 773 bits<5> VB; 774 bit RC = 0; 775 776 let Pattern = pattern; 777 778 let Inst{6-10} = VD; 779 let Inst{11-15} = VA; 780 let Inst{16-20} = VB; 781 let Inst{21} = RC; 782 let Inst{22-31} = xo; 783} 784 785//===----------------------------------------------------------------------===// 786class Pseudo<dag OL, string asmstr, list<dag> pattern> 787 : I<0, OL, asmstr, NoItinerary> { 788 let PPC64 = 0; 789 let Pattern = pattern; 790 let Inst{31-0} = 0; 791} 792