PPCInstrFormats.td revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb
1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 18 let Size = 4; 19 20 bit PPC64 = 0; // Default value, override with isPPC64 21 22 let Namespace = "PPC"; 23 let Inst{0-5} = opcode; 24 let OutOperandList = OOL; 25 let InOperandList = IOL; 26 let AsmString = asmstr; 27 let Itinerary = itin; 28 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 33 34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 35 /// these must be reflected there! See comments there for what these are. 36 let TSFlags{0} = PPC970_First; 37 let TSFlags{1} = PPC970_Single; 38 let TSFlags{2} = PPC970_Cracked; 39 let TSFlags{5-3} = PPC970_Unit; 40 41 // Fields used for relation models. 42 string BaseName = ""; 43 44 // For cases where multiple instruction definitions really represent the 45 // same underlying instruction but with one definition for 64-bit arguments 46 // and one for 32-bit arguments, this bit breaks the degeneracy between 47 // the two forms and allows TableGen to generate mapping tables. 48 bit Interpretation64Bit = 0; 49} 50 51class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 52class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 53class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 54class PPC970_MicroCode; 55 56class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 57class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 58class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 59class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 60class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 61class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 62class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 63class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 64 65// Two joined instructions; used to emit two adjacent instructions as one. 66// The itinerary from the first instruction is used for scheduling and 67// classification. 68class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 69 InstrItinClass itin> 70 : Instruction { 71 field bits<64> Inst; 72 field bits<64> SoftFail = 0; 73 let Size = 8; 74 75 bit PPC64 = 0; // Default value, override with isPPC64 76 77 let Namespace = "PPC"; 78 let Inst{0-5} = opcode1; 79 let Inst{32-37} = opcode2; 80 let OutOperandList = OOL; 81 let InOperandList = IOL; 82 let AsmString = asmstr; 83 let Itinerary = itin; 84 85 bits<1> PPC970_First = 0; 86 bits<1> PPC970_Single = 0; 87 bits<1> PPC970_Cracked = 0; 88 bits<3> PPC970_Unit = 0; 89 90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 91 /// these must be reflected there! See comments there for what these are. 92 let TSFlags{0} = PPC970_First; 93 let TSFlags{1} = PPC970_Single; 94 let TSFlags{2} = PPC970_Cracked; 95 let TSFlags{5-3} = PPC970_Unit; 96 97 // Fields used for relation models. 98 string BaseName = ""; 99 bit Interpretation64Bit = 0; 100} 101 102// 1.7.1 I-Form 103class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 104 InstrItinClass itin, list<dag> pattern> 105 : I<opcode, OOL, IOL, asmstr, itin> { 106 let Pattern = pattern; 107 bits<24> LI; 108 109 let Inst{6-29} = LI; 110 let Inst{30} = aa; 111 let Inst{31} = lk; 112} 113 114// 1.7.2 B-Form 115class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 118 bits<3> CR; 119 bits<14> BD; 120 121 bits<5> BI; 122 let BI{0-1} = BIBO{5-6}; 123 let BI{2-4} = CR{0-2}; 124 125 let Inst{6-10} = BIBO{4-0}; 126 let Inst{11-15} = BI; 127 let Inst{16-29} = BD; 128 let Inst{30} = aa; 129 let Inst{31} = lk; 130} 131 132class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 133 string asmstr> 134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 135 let BIBO{4-0} = bo; 136 let BIBO{6-5} = 0; 137 let CR = 0; 138} 139 140class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 141 dag OOL, dag IOL, string asmstr> 142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 143 bits<14> BD; 144 145 let Inst{6-10} = bo; 146 let Inst{11-15} = bi; 147 let Inst{16-29} = BD; 148 let Inst{30} = aa; 149 let Inst{31} = lk; 150} 151 152class BForm_3<bits<6> opcode, bit aa, bit lk, 153 dag OOL, dag IOL, string asmstr> 154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 155 bits<5> BO; 156 bits<5> BI; 157 bits<14> BD; 158 159 let Inst{6-10} = BO; 160 let Inst{11-15} = BI; 161 let Inst{16-29} = BD; 162 let Inst{30} = aa; 163 let Inst{31} = lk; 164} 165 166class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<5> BI; 170 bits<14> BD; 171 172 let Inst{6-10} = bo; 173 let Inst{11-15} = BI; 174 let Inst{16-29} = BD; 175 let Inst{30} = aa; 176 let Inst{31} = lk; 177} 178 179// 1.7.3 SC-Form 180class SCForm<bits<6> opcode, bits<1> xo, 181 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 182 list<dag> pattern> 183 : I<opcode, OOL, IOL, asmstr, itin> { 184 bits<7> LEV; 185 186 let Pattern = pattern; 187 188 let Inst{20-26} = LEV; 189 let Inst{30} = xo; 190} 191 192// 1.7.4 D-Form 193class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 194 InstrItinClass itin, list<dag> pattern> 195 : I<opcode, OOL, IOL, asmstr, itin> { 196 bits<5> A; 197 bits<5> B; 198 bits<16> C; 199 200 let Pattern = pattern; 201 202 let Inst{6-10} = A; 203 let Inst{11-15} = B; 204 let Inst{16-31} = C; 205} 206 207class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 208 InstrItinClass itin, list<dag> pattern> 209 : I<opcode, OOL, IOL, asmstr, itin> { 210 bits<5> A; 211 bits<21> Addr; 212 213 let Pattern = pattern; 214 215 let Inst{6-10} = A; 216 let Inst{11-15} = Addr{20-16}; // Base Reg 217 let Inst{16-31} = Addr{15-0}; // Displacement 218} 219 220class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 221 InstrItinClass itin, list<dag> pattern> 222 : I<opcode, OOL, IOL, asmstr, itin> { 223 bits<5> A; 224 bits<16> C; 225 bits<5> B; 226 227 let Pattern = pattern; 228 229 let Inst{6-10} = A; 230 let Inst{11-15} = B; 231 let Inst{16-31} = C; 232} 233 234 235class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 236 InstrItinClass itin, list<dag> pattern> 237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 238 239 // Even though ADDICo does not really have an RC bit, provide 240 // the declaration of one here so that isDOT has something to set. 241 bit RC = 0; 242} 243 244class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 245 InstrItinClass itin, list<dag> pattern> 246 : I<opcode, OOL, IOL, asmstr, itin> { 247 bits<5> A; 248 bits<16> B; 249 250 let Pattern = pattern; 251 252 let Inst{6-10} = A; 253 let Inst{11-15} = 0; 254 let Inst{16-31} = B; 255} 256 257class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 258 InstrItinClass itin, list<dag> pattern> 259 : I<opcode, OOL, IOL, asmstr, itin> { 260 bits<5> B; 261 bits<5> A; 262 bits<16> C; 263 264 let Pattern = pattern; 265 266 let Inst{6-10} = A; 267 let Inst{11-15} = B; 268 let Inst{16-31} = C; 269} 270 271class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 272 InstrItinClass itin, list<dag> pattern> 273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 274 let A = 0; 275 let Addr = 0; 276} 277 278class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 279 string asmstr, InstrItinClass itin, 280 list<dag> pattern> 281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 282 let A = R; 283 let B = R; 284 let C = 0; 285} 286 287class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 288 dag OOL, dag IOL, string asmstr, 289 InstrItinClass itin, list<dag> pattern> 290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 291 bits<5> A; 292 bits<21> Addr; 293 294 let Pattern = pattern; 295 bits<24> LI; 296 297 let Inst{6-29} = LI; 298 let Inst{30} = aa; 299 let Inst{31} = lk; 300 301 let Inst{38-42} = A; 302 let Inst{43-47} = Addr{20-16}; // Base Reg 303 let Inst{48-63} = Addr{15-0}; // Displacement 304} 305 306// This is used to emit BL8+NOP. 307class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 308 dag OOL, dag IOL, string asmstr, 309 InstrItinClass itin, list<dag> pattern> 310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 311 OOL, IOL, asmstr, itin, pattern> { 312 let A = 0; 313 let Addr = 0; 314} 315 316class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 317 InstrItinClass itin> 318 : I<opcode, OOL, IOL, asmstr, itin> { 319 bits<3> BF; 320 bits<1> L; 321 bits<5> RA; 322 bits<16> I; 323 324 let Inst{6-8} = BF; 325 let Inst{9} = 0; 326 let Inst{10} = L; 327 let Inst{11-15} = RA; 328 let Inst{16-31} = I; 329} 330 331class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 332 InstrItinClass itin> 333 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 334 let L = PPC64; 335} 336 337class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 338 InstrItinClass itin> 339 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 340 341class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 342 InstrItinClass itin> 343 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 344 let L = PPC64; 345} 346 347 348// 1.7.5 DS-Form 349class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 350 InstrItinClass itin, list<dag> pattern> 351 : I<opcode, OOL, IOL, asmstr, itin> { 352 bits<5> RST; 353 bits<19> DS_RA; 354 355 let Pattern = pattern; 356 357 let Inst{6-10} = RST; 358 let Inst{11-15} = DS_RA{18-14}; // Register # 359 let Inst{16-29} = DS_RA{13-0}; // Displacement. 360 let Inst{30-31} = xo; 361} 362 363 364// 1.7.6 X-Form 365class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 366 InstrItinClass itin, list<dag> pattern> 367 : I<opcode, OOL, IOL, asmstr, itin> { 368 bits<5> RST; 369 bits<5> A; 370 bits<5> B; 371 372 let Pattern = pattern; 373 374 bit RC = 0; // set by isDOT 375 376 let Inst{6-10} = RST; 377 let Inst{11-15} = A; 378 let Inst{16-20} = B; 379 let Inst{21-30} = xo; 380 let Inst{31} = RC; 381} 382 383// This is the same as XForm_base_r3xo, but the first two operands are swapped 384// when code is emitted. 385class XForm_base_r3xo_swapped 386 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 387 InstrItinClass itin> 388 : I<opcode, OOL, IOL, asmstr, itin> { 389 bits<5> A; 390 bits<5> RST; 391 bits<5> B; 392 393 bit RC = 0; // set by isDOT 394 395 let Inst{6-10} = RST; 396 let Inst{11-15} = A; 397 let Inst{16-20} = B; 398 let Inst{21-30} = xo; 399 let Inst{31} = RC; 400} 401 402 403class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 404 InstrItinClass itin, list<dag> pattern> 405 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 406 407class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 408 InstrItinClass itin, list<dag> pattern> 409 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 410 let RST = 0; 411} 412 413class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 414 InstrItinClass itin, list<dag> pattern> 415 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 416 let A = 0; 417 let B = 0; 418} 419 420class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 421 InstrItinClass itin, list<dag> pattern> 422 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 423 let Pattern = pattern; 424} 425 426class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 427 InstrItinClass itin, list<dag> pattern> 428 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 429 430class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 431 InstrItinClass itin, list<dag> pattern> 432 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 433 let Pattern = pattern; 434} 435 436class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 437 InstrItinClass itin, list<dag> pattern> 438 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 439 let B = 0; 440 let Pattern = pattern; 441} 442 443class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 444 InstrItinClass itin> 445 : I<opcode, OOL, IOL, asmstr, itin> { 446 bits<3> BF; 447 bits<1> L; 448 bits<5> RA; 449 bits<5> RB; 450 451 let Inst{6-8} = BF; 452 let Inst{9} = 0; 453 let Inst{10} = L; 454 let Inst{11-15} = RA; 455 let Inst{16-20} = RB; 456 let Inst{21-30} = xo; 457 let Inst{31} = 0; 458} 459 460class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 461 InstrItinClass itin> 462 : I<opcode, OOL, IOL, asmstr, itin> { 463 bits<5> RS; 464 bits<1> L; 465 466 let Inst{6-10} = RS; 467 let Inst{15} = L; 468 let Inst{21-30} = xo; 469} 470 471class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 472 InstrItinClass itin> 473 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 474 let L = PPC64; 475} 476 477class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 478 InstrItinClass itin> 479 : I<opcode, OOL, IOL, asmstr, itin> { 480 bits<3> BF; 481 bits<5> FRA; 482 bits<5> FRB; 483 484 let Inst{6-8} = BF; 485 let Inst{9-10} = 0; 486 let Inst{11-15} = FRA; 487 let Inst{16-20} = FRB; 488 let Inst{21-30} = xo; 489 let Inst{31} = 0; 490} 491 492class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 493 InstrItinClass itin, list<dag> pattern> 494 : I<opcode, OOL, IOL, asmstr, itin> { 495 let Pattern = pattern; 496 let Inst{6-10} = 31; 497 let Inst{11-15} = 0; 498 let Inst{16-20} = 0; 499 let Inst{21-30} = xo; 500 let Inst{31} = 0; 501} 502 503class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 504 string asmstr, InstrItinClass itin, list<dag> pattern> 505 : I<opcode, OOL, IOL, asmstr, itin> { 506 bits<2> L; 507 508 let Pattern = pattern; 509 let Inst{6-8} = 0; 510 let Inst{9-10} = L; 511 let Inst{11-15} = 0; 512 let Inst{16-20} = 0; 513 let Inst{21-30} = xo; 514 let Inst{31} = 0; 515} 516 517class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 518 string asmstr, InstrItinClass itin, list<dag> pattern> 519 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 520 let L = 0; 521} 522 523class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 524 InstrItinClass itin, list<dag> pattern> 525 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 526} 527 528class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 529 InstrItinClass itin, list<dag> pattern> 530 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 531 let A = 0; 532} 533 534class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 535 InstrItinClass itin, list<dag> pattern> 536 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 537} 538 539// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 540// numbers presumably relates to some document, but I haven't found it. 541class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 542 InstrItinClass itin, list<dag> pattern> 543 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 544 let Pattern = pattern; 545 546 bit RC = 0; // set by isDOT 547 548 let Inst{6-10} = RST; 549 let Inst{11-20} = 0; 550 let Inst{21-30} = xo; 551 let Inst{31} = RC; 552} 553class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 554 InstrItinClass itin, list<dag> pattern> 555 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 556 let Pattern = pattern; 557 bits<5> FM; 558 559 bit RC = 0; // set by isDOT 560 561 let Inst{6-10} = FM; 562 let Inst{11-20} = 0; 563 let Inst{21-30} = xo; 564 let Inst{31} = RC; 565} 566 567class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 568 InstrItinClass itin, list<dag> pattern> 569 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 570 let RST = 0; 571 let A = 0; 572 let B = 0; 573} 574 575class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 576 InstrItinClass itin, list<dag> pattern> 577 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 578 let RST = 0; 579 let A = 0; 580} 581 582// XX*-Form (VSX) 583class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 584 InstrItinClass itin, list<dag> pattern> 585 : I<opcode, OOL, IOL, asmstr, itin> { 586 bits<6> XT; 587 bits<5> A; 588 bits<5> B; 589 590 let Pattern = pattern; 591 592 let Inst{6-10} = XT{4-0}; 593 let Inst{11-15} = A; 594 let Inst{16-20} = B; 595 let Inst{21-30} = xo; 596 let Inst{31} = XT{5}; 597} 598 599class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 600 InstrItinClass itin, list<dag> pattern> 601 : I<opcode, OOL, IOL, asmstr, itin> { 602 bits<6> XT; 603 bits<6> XB; 604 605 let Pattern = pattern; 606 607 let Inst{6-10} = XT{4-0}; 608 let Inst{11-15} = 0; 609 let Inst{16-20} = XB{4-0}; 610 let Inst{21-29} = xo; 611 let Inst{30} = XB{5}; 612 let Inst{31} = XT{5}; 613} 614 615class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 616 InstrItinClass itin, list<dag> pattern> 617 : I<opcode, OOL, IOL, asmstr, itin> { 618 bits<3> CR; 619 bits<6> XB; 620 621 let Pattern = pattern; 622 623 let Inst{6-8} = CR; 624 let Inst{9-15} = 0; 625 let Inst{16-20} = XB{4-0}; 626 let Inst{21-29} = xo; 627 let Inst{30} = XB{5}; 628 let Inst{31} = 0; 629} 630 631class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 632 InstrItinClass itin, list<dag> pattern> 633 : I<opcode, OOL, IOL, asmstr, itin> { 634 bits<6> XT; 635 bits<6> XB; 636 bits<2> D; 637 638 let Pattern = pattern; 639 640 let Inst{6-10} = XT{4-0}; 641 let Inst{11-13} = 0; 642 let Inst{14-15} = D; 643 let Inst{16-20} = XB{4-0}; 644 let Inst{21-29} = xo; 645 let Inst{30} = XB{5}; 646 let Inst{31} = XT{5}; 647} 648 649class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 650 InstrItinClass itin, list<dag> pattern> 651 : I<opcode, OOL, IOL, asmstr, itin> { 652 bits<6> XT; 653 bits<6> XA; 654 bits<6> XB; 655 656 let Pattern = pattern; 657 658 let Inst{6-10} = XT{4-0}; 659 let Inst{11-15} = XA{4-0}; 660 let Inst{16-20} = XB{4-0}; 661 let Inst{21-28} = xo; 662 let Inst{29} = XA{5}; 663 let Inst{30} = XB{5}; 664 let Inst{31} = XT{5}; 665} 666 667class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 668 InstrItinClass itin, list<dag> pattern> 669 : I<opcode, OOL, IOL, asmstr, itin> { 670 bits<3> CR; 671 bits<6> XA; 672 bits<6> XB; 673 674 let Pattern = pattern; 675 676 let Inst{6-8} = CR; 677 let Inst{9-10} = 0; 678 let Inst{11-15} = XA{4-0}; 679 let Inst{16-20} = XB{4-0}; 680 let Inst{21-28} = xo; 681 let Inst{29} = XA{5}; 682 let Inst{30} = XB{5}; 683 let Inst{31} = 0; 684} 685 686class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 687 InstrItinClass itin, list<dag> pattern> 688 : I<opcode, OOL, IOL, asmstr, itin> { 689 bits<6> XT; 690 bits<6> XA; 691 bits<6> XB; 692 bits<2> D; 693 694 let Pattern = pattern; 695 696 let Inst{6-10} = XT{4-0}; 697 let Inst{11-15} = XA{4-0}; 698 let Inst{16-20} = XB{4-0}; 699 let Inst{21} = 0; 700 let Inst{22-23} = D; 701 let Inst{24-28} = xo; 702 let Inst{29} = XA{5}; 703 let Inst{30} = XB{5}; 704 let Inst{31} = XT{5}; 705} 706 707class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 708 InstrItinClass itin, list<dag> pattern> 709 : I<opcode, OOL, IOL, asmstr, itin> { 710 bits<6> XT; 711 bits<6> XA; 712 bits<6> XB; 713 714 let Pattern = pattern; 715 716 bit RC = 0; // set by isDOT 717 718 let Inst{6-10} = XT{4-0}; 719 let Inst{11-15} = XA{4-0}; 720 let Inst{16-20} = XB{4-0}; 721 let Inst{21} = RC; 722 let Inst{22-28} = xo; 723 let Inst{29} = XA{5}; 724 let Inst{30} = XB{5}; 725 let Inst{31} = XT{5}; 726} 727 728class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 729 InstrItinClass itin, list<dag> pattern> 730 : I<opcode, OOL, IOL, asmstr, itin> { 731 bits<6> XT; 732 bits<6> XA; 733 bits<6> XB; 734 bits<6> XC; 735 736 let Pattern = pattern; 737 738 let Inst{6-10} = XT{4-0}; 739 let Inst{11-15} = XA{4-0}; 740 let Inst{16-20} = XB{4-0}; 741 let Inst{21-25} = XC{4-0}; 742 let Inst{26-27} = xo; 743 let Inst{28} = XC{5}; 744 let Inst{29} = XA{5}; 745 let Inst{30} = XB{5}; 746 let Inst{31} = XT{5}; 747} 748 749// DCB_Form - Form X instruction, used for dcb* instructions. 750class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 751 InstrItinClass itin, list<dag> pattern> 752 : I<31, OOL, IOL, asmstr, itin> { 753 bits<5> A; 754 bits<5> B; 755 756 let Pattern = pattern; 757 758 let Inst{6-10} = immfield; 759 let Inst{11-15} = A; 760 let Inst{16-20} = B; 761 let Inst{21-30} = xo; 762 let Inst{31} = 0; 763} 764 765 766// DSS_Form - Form X instruction, used for altivec dss* instructions. 767class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr, 768 InstrItinClass itin, list<dag> pattern> 769 : I<31, OOL, IOL, asmstr, itin> { 770 bits<1> T; 771 bits<2> STRM; 772 bits<5> A; 773 bits<5> B; 774 775 let Pattern = pattern; 776 777 let Inst{6} = T; 778 let Inst{7-8} = 0; 779 let Inst{9-10} = STRM; 780 let Inst{11-15} = A; 781 let Inst{16-20} = B; 782 let Inst{21-30} = xo; 783 let Inst{31} = 0; 784} 785 786// 1.7.7 XL-Form 787class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 788 InstrItinClass itin, list<dag> pattern> 789 : I<opcode, OOL, IOL, asmstr, itin> { 790 bits<5> CRD; 791 bits<5> CRA; 792 bits<5> CRB; 793 794 let Pattern = pattern; 795 796 let Inst{6-10} = CRD; 797 let Inst{11-15} = CRA; 798 let Inst{16-20} = CRB; 799 let Inst{21-30} = xo; 800 let Inst{31} = 0; 801} 802 803class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 804 InstrItinClass itin, list<dag> pattern> 805 : I<opcode, OOL, IOL, asmstr, itin> { 806 bits<5> CRD; 807 808 let Pattern = pattern; 809 810 let Inst{6-10} = CRD; 811 let Inst{11-15} = CRD; 812 let Inst{16-20} = CRD; 813 let Inst{21-30} = xo; 814 let Inst{31} = 0; 815} 816 817class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 818 InstrItinClass itin, list<dag> pattern> 819 : I<opcode, OOL, IOL, asmstr, itin> { 820 bits<5> BO; 821 bits<5> BI; 822 bits<2> BH; 823 824 let Pattern = pattern; 825 826 let Inst{6-10} = BO; 827 let Inst{11-15} = BI; 828 let Inst{16-18} = 0; 829 let Inst{19-20} = BH; 830 let Inst{21-30} = xo; 831 let Inst{31} = lk; 832} 833 834class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 835 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 836 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 837 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 838 bits<3> CR; 839 840 let BO = BIBO{4-0}; 841 let BI{0-1} = BIBO{5-6}; 842 let BI{2-4} = CR{0-2}; 843 let BH = 0; 844} 845 846class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 847 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 848 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 849 let BO = bo; 850 let BH = 0; 851} 852 853class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 854 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 855 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 856 let BO = bo; 857 let BI = bi; 858 let BH = 0; 859} 860 861class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 862 InstrItinClass itin> 863 : I<opcode, OOL, IOL, asmstr, itin> { 864 bits<3> BF; 865 bits<3> BFA; 866 867 let Inst{6-8} = BF; 868 let Inst{9-10} = 0; 869 let Inst{11-13} = BFA; 870 let Inst{14-15} = 0; 871 let Inst{16-20} = 0; 872 let Inst{21-30} = xo; 873 let Inst{31} = 0; 874} 875 876// 1.7.8 XFX-Form 877class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 878 InstrItinClass itin> 879 : I<opcode, OOL, IOL, asmstr, itin> { 880 bits<5> RT; 881 bits<10> SPR; 882 883 let Inst{6-10} = RT; 884 let Inst{11} = SPR{4}; 885 let Inst{12} = SPR{3}; 886 let Inst{13} = SPR{2}; 887 let Inst{14} = SPR{1}; 888 let Inst{15} = SPR{0}; 889 let Inst{16} = SPR{9}; 890 let Inst{17} = SPR{8}; 891 let Inst{18} = SPR{7}; 892 let Inst{19} = SPR{6}; 893 let Inst{20} = SPR{5}; 894 let Inst{21-30} = xo; 895 let Inst{31} = 0; 896} 897 898class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 899 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 900 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 901 let SPR = spr; 902} 903 904class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 905 InstrItinClass itin> 906 : I<opcode, OOL, IOL, asmstr, itin> { 907 bits<5> RT; 908 909 let Inst{6-10} = RT; 910 let Inst{11-20} = 0; 911 let Inst{21-30} = xo; 912 let Inst{31} = 0; 913} 914 915class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 916 InstrItinClass itin> 917 : I<opcode, OOL, IOL, asmstr, itin> { 918 bits<8> FXM; 919 bits<5> rS; 920 921 let Inst{6-10} = rS; 922 let Inst{11} = 0; 923 let Inst{12-19} = FXM; 924 let Inst{20} = 0; 925 let Inst{21-30} = xo; 926 let Inst{31} = 0; 927} 928 929class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 930 InstrItinClass itin> 931 : I<opcode, OOL, IOL, asmstr, itin> { 932 bits<5> ST; 933 bits<8> FXM; 934 935 let Inst{6-10} = ST; 936 let Inst{11} = 1; 937 let Inst{12-19} = FXM; 938 let Inst{20} = 0; 939 let Inst{21-30} = xo; 940 let Inst{31} = 0; 941} 942 943class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 944 InstrItinClass itin> 945 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 946 947class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 948 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 949 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 950 let SPR = spr; 951} 952 953// XFL-Form - MTFSF 954// This is probably 1.7.9, but I don't have the reference that uses this 955// numbering scheme... 956class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 957 InstrItinClass itin, list<dag>pattern> 958 : I<opcode, OOL, IOL, asmstr, itin> { 959 bits<8> FM; 960 bits<5> rT; 961 962 bit RC = 0; // set by isDOT 963 let Pattern = pattern; 964 965 let Inst{6} = 0; 966 let Inst{7-14} = FM; 967 let Inst{15} = 0; 968 let Inst{16-20} = rT; 969 let Inst{21-30} = xo; 970 let Inst{31} = RC; 971} 972 973// 1.7.10 XS-Form - SRADI. 974class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 975 InstrItinClass itin, list<dag> pattern> 976 : I<opcode, OOL, IOL, asmstr, itin> { 977 bits<5> A; 978 bits<5> RS; 979 bits<6> SH; 980 981 bit RC = 0; // set by isDOT 982 let Pattern = pattern; 983 984 let Inst{6-10} = RS; 985 let Inst{11-15} = A; 986 let Inst{16-20} = SH{4,3,2,1,0}; 987 let Inst{21-29} = xo; 988 let Inst{30} = SH{5}; 989 let Inst{31} = RC; 990} 991 992// 1.7.11 XO-Form 993class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 994 InstrItinClass itin, list<dag> pattern> 995 : I<opcode, OOL, IOL, asmstr, itin> { 996 bits<5> RT; 997 bits<5> RA; 998 bits<5> RB; 999 1000 let Pattern = pattern; 1001 1002 bit RC = 0; // set by isDOT 1003 1004 let Inst{6-10} = RT; 1005 let Inst{11-15} = RA; 1006 let Inst{16-20} = RB; 1007 let Inst{21} = oe; 1008 let Inst{22-30} = xo; 1009 let Inst{31} = RC; 1010} 1011 1012class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1013 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1014 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1015 let RB = 0; 1016} 1017 1018// 1.7.12 A-Form 1019class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1020 InstrItinClass itin, list<dag> pattern> 1021 : I<opcode, OOL, IOL, asmstr, itin> { 1022 bits<5> FRT; 1023 bits<5> FRA; 1024 bits<5> FRC; 1025 bits<5> FRB; 1026 1027 let Pattern = pattern; 1028 1029 bit RC = 0; // set by isDOT 1030 1031 let Inst{6-10} = FRT; 1032 let Inst{11-15} = FRA; 1033 let Inst{16-20} = FRB; 1034 let Inst{21-25} = FRC; 1035 let Inst{26-30} = xo; 1036 let Inst{31} = RC; 1037} 1038 1039class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1040 InstrItinClass itin, list<dag> pattern> 1041 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1042 let FRC = 0; 1043} 1044 1045class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1046 InstrItinClass itin, list<dag> pattern> 1047 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1048 let FRB = 0; 1049} 1050 1051class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1052 InstrItinClass itin, list<dag> pattern> 1053 : I<opcode, OOL, IOL, asmstr, itin> { 1054 bits<5> RT; 1055 bits<5> RA; 1056 bits<5> RB; 1057 bits<5> COND; 1058 1059 let Pattern = pattern; 1060 1061 let Inst{6-10} = RT; 1062 let Inst{11-15} = RA; 1063 let Inst{16-20} = RB; 1064 let Inst{21-25} = COND; 1065 let Inst{26-30} = xo; 1066 let Inst{31} = 0; 1067} 1068 1069// 1.7.13 M-Form 1070class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1071 InstrItinClass itin, list<dag> pattern> 1072 : I<opcode, OOL, IOL, asmstr, itin> { 1073 bits<5> RA; 1074 bits<5> RS; 1075 bits<5> RB; 1076 bits<5> MB; 1077 bits<5> ME; 1078 1079 let Pattern = pattern; 1080 1081 bit RC = 0; // set by isDOT 1082 1083 let Inst{6-10} = RS; 1084 let Inst{11-15} = RA; 1085 let Inst{16-20} = RB; 1086 let Inst{21-25} = MB; 1087 let Inst{26-30} = ME; 1088 let Inst{31} = RC; 1089} 1090 1091class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1092 InstrItinClass itin, list<dag> pattern> 1093 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1094} 1095 1096// 1.7.14 MD-Form 1097class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1098 InstrItinClass itin, list<dag> pattern> 1099 : I<opcode, OOL, IOL, asmstr, itin> { 1100 bits<5> RA; 1101 bits<5> RS; 1102 bits<6> SH; 1103 bits<6> MBE; 1104 1105 let Pattern = pattern; 1106 1107 bit RC = 0; // set by isDOT 1108 1109 let Inst{6-10} = RS; 1110 let Inst{11-15} = RA; 1111 let Inst{16-20} = SH{4,3,2,1,0}; 1112 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1113 let Inst{27-29} = xo; 1114 let Inst{30} = SH{5}; 1115 let Inst{31} = RC; 1116} 1117 1118class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1119 InstrItinClass itin, list<dag> pattern> 1120 : I<opcode, OOL, IOL, asmstr, itin> { 1121 bits<5> RA; 1122 bits<5> RS; 1123 bits<5> RB; 1124 bits<6> MBE; 1125 1126 let Pattern = pattern; 1127 1128 bit RC = 0; // set by isDOT 1129 1130 let Inst{6-10} = RS; 1131 let Inst{11-15} = RA; 1132 let Inst{16-20} = RB; 1133 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1134 let Inst{27-30} = xo; 1135 let Inst{31} = RC; 1136} 1137 1138 1139// E-1 VA-Form 1140 1141// VAForm_1 - DACB ordering. 1142class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1143 InstrItinClass itin, list<dag> pattern> 1144 : I<4, OOL, IOL, asmstr, itin> { 1145 bits<5> VD; 1146 bits<5> VA; 1147 bits<5> VC; 1148 bits<5> VB; 1149 1150 let Pattern = pattern; 1151 1152 let Inst{6-10} = VD; 1153 let Inst{11-15} = VA; 1154 let Inst{16-20} = VB; 1155 let Inst{21-25} = VC; 1156 let Inst{26-31} = xo; 1157} 1158 1159// VAForm_1a - DABC ordering. 1160class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1161 InstrItinClass itin, list<dag> pattern> 1162 : I<4, OOL, IOL, asmstr, itin> { 1163 bits<5> VD; 1164 bits<5> VA; 1165 bits<5> VB; 1166 bits<5> VC; 1167 1168 let Pattern = pattern; 1169 1170 let Inst{6-10} = VD; 1171 let Inst{11-15} = VA; 1172 let Inst{16-20} = VB; 1173 let Inst{21-25} = VC; 1174 let Inst{26-31} = xo; 1175} 1176 1177class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1178 InstrItinClass itin, list<dag> pattern> 1179 : I<4, OOL, IOL, asmstr, itin> { 1180 bits<5> VD; 1181 bits<5> VA; 1182 bits<5> VB; 1183 bits<4> SH; 1184 1185 let Pattern = pattern; 1186 1187 let Inst{6-10} = VD; 1188 let Inst{11-15} = VA; 1189 let Inst{16-20} = VB; 1190 let Inst{21} = 0; 1191 let Inst{22-25} = SH; 1192 let Inst{26-31} = xo; 1193} 1194 1195// E-2 VX-Form 1196class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1197 InstrItinClass itin, list<dag> pattern> 1198 : I<4, OOL, IOL, asmstr, itin> { 1199 bits<5> VD; 1200 bits<5> VA; 1201 bits<5> VB; 1202 1203 let Pattern = pattern; 1204 1205 let Inst{6-10} = VD; 1206 let Inst{11-15} = VA; 1207 let Inst{16-20} = VB; 1208 let Inst{21-31} = xo; 1209} 1210 1211class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1212 InstrItinClass itin, list<dag> pattern> 1213 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1214 let VA = VD; 1215 let VB = VD; 1216} 1217 1218 1219class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1220 InstrItinClass itin, list<dag> pattern> 1221 : I<4, OOL, IOL, asmstr, itin> { 1222 bits<5> VD; 1223 bits<5> VB; 1224 1225 let Pattern = pattern; 1226 1227 let Inst{6-10} = VD; 1228 let Inst{11-15} = 0; 1229 let Inst{16-20} = VB; 1230 let Inst{21-31} = xo; 1231} 1232 1233class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1234 InstrItinClass itin, list<dag> pattern> 1235 : I<4, OOL, IOL, asmstr, itin> { 1236 bits<5> VD; 1237 bits<5> IMM; 1238 1239 let Pattern = pattern; 1240 1241 let Inst{6-10} = VD; 1242 let Inst{11-15} = IMM; 1243 let Inst{16-20} = 0; 1244 let Inst{21-31} = xo; 1245} 1246 1247/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1248class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1249 InstrItinClass itin, list<dag> pattern> 1250 : I<4, OOL, IOL, asmstr, itin> { 1251 bits<5> VD; 1252 1253 let Pattern = pattern; 1254 1255 let Inst{6-10} = VD; 1256 let Inst{11-15} = 0; 1257 let Inst{16-20} = 0; 1258 let Inst{21-31} = xo; 1259} 1260 1261/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1262class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1263 InstrItinClass itin, list<dag> pattern> 1264 : I<4, OOL, IOL, asmstr, itin> { 1265 bits<5> VB; 1266 1267 let Pattern = pattern; 1268 1269 let Inst{6-10} = 0; 1270 let Inst{11-15} = 0; 1271 let Inst{16-20} = VB; 1272 let Inst{21-31} = xo; 1273} 1274 1275// E-4 VXR-Form 1276class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 1277 InstrItinClass itin, list<dag> pattern> 1278 : I<4, OOL, IOL, asmstr, itin> { 1279 bits<5> VD; 1280 bits<5> VA; 1281 bits<5> VB; 1282 bit RC = 0; 1283 1284 let Pattern = pattern; 1285 1286 let Inst{6-10} = VD; 1287 let Inst{11-15} = VA; 1288 let Inst{16-20} = VB; 1289 let Inst{21} = RC; 1290 let Inst{22-31} = xo; 1291} 1292 1293//===----------------------------------------------------------------------===// 1294class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 1295 : I<0, OOL, IOL, asmstr, NoItinerary> { 1296 let isCodeGenOnly = 1; 1297 let PPC64 = 0; 1298 let Pattern = pattern; 1299 let Inst{31-0} = 0; 1300} 1301