PPCInstrInfo.h revision 354362524a72b3fa43a6c09380b7ae3b2380cbba
18bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// The LLVM Compiler Infrastructure 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 58bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// License. See LICENSE.TXT for details. 75821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 85821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file contains the PowerPC implementation of the TargetInstrInfo class. 115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#ifndef POWERPC_INSTRUCTIONINFO_H 155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define POWERPC_INSTRUCTIONINFO_H 16cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "PPC.h" 18cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "PPCRegisterInfo.h" 19cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "llvm/Target/TargetInstrInfo.h" 20cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define GET_INSTRINFO_HEADER 22cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "PPCGenInstrInfo.inc" 23cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 24cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)namespace llvm { 25cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 26cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// PPCII - This namespace holds all of the PowerPC target-specific 27cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// per-instruction flags. These must match the corresponding definitions in 28cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// PPC.td and PPCInstrFormats.td. 29cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)namespace PPCII { 30cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)enum { 31cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // PPC970 Instruction Flags. These flags describe the characteristics of the 32cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 33cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // raw machine instructions. 34cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 35cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// PPC970_First - This instruction starts a new dispatch group, so it will 36cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// always be the first one in the group. 37cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PPC970_First = 0x1, 385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 39cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// PPC970_Single - This instruction starts a new dispatch group and 408bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) /// terminates it, so it will be the sole instruction in the group. 418bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) PPC970_Single = 0x2, 425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 44cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// two dispatch pipes to be available to issue. 45cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PPC970_Cracked = 0x4, 46cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 47cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 48cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// an instruction is issued to. 49cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PPC970_Shift = 3, 50cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PPC970_Mask = 0x07 << PPC970_Shift 51cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)}; 52cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)enum PPC970_Unit { 53cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// These are the various PPC970 execution unit pipelines. Each instruction 54cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// is one of these. 55cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 56cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 57cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 58cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 59cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 60cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 61cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 62cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PPC970_BRU = 7 << PPC970_Shift // Branch Unit 63cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)}; 64cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} // end namespace PPCII 65cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 66cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 67cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)class PPCInstrInfo : public PPCGenInstrInfo { 68cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PPCTargetMachine &TM; 69cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const PPCRegisterInfo RI; 70cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 71cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) bool StoreRegToStackSlot(MachineFunction &MF, 72cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) unsigned SrcReg, bool isKill, int FrameIdx, 73cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const TargetRegisterClass *RC, 74cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) SmallVectorImpl<MachineInstr*> &NewMIs, 75cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) bool &NonRI, bool &SpillsVRS) const; 76cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 77cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) unsigned DestReg, int FrameIdx, 78cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const TargetRegisterClass *RC, 79cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) SmallVectorImpl<MachineInstr*> &NewMIs, 80cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) bool &NonRI, bool &SpillsVRS) const; 81cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) virtual void anchor(); 82cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)public: 83cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) explicit PPCInstrInfo(PPCTargetMachine &TM); 84cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 85cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 86cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// such, whenever a client has an instance of instruction info, it should 87cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// always be able to get register info as well (through this method). 88cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// 89cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; } 90cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 91cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) ScheduleHazardRecognizer * 92cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) CreateTargetHazardRecognizer(const TargetMachine *TM, 93cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const ScheduleDAG *DAG) const; 94cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) ScheduleHazardRecognizer * 95cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 96cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const ScheduleDAG *DAG) const; 97cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 98cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) bool isCoalescableExtInstr(const MachineInstr &MI, 99cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) unsigned &SrcReg, unsigned &DstReg, 100cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) unsigned &SubIdx) const; 101cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) unsigned isLoadFromStackSlot(const MachineInstr *MI, 102cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) int &FrameIndex) const; 103cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) unsigned isStoreToStackSlot(const MachineInstr *MI, 104cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) int &FrameIndex) const; 105cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 106cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // commuteInstruction - We can commute rlwimi instructions, but only if the 107cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // rotate amt is zero. We also have to munge the immediates a bit. 108cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 109cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 110cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) virtual void insertNoop(MachineBasicBlock &MBB, 111cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MachineBasicBlock::iterator MI) const; 112cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 113cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 1142a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Branch analysis. 1152a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 11646d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) MachineBasicBlock *&FBB, 11746d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) SmallVectorImpl<MachineOperand> &Cond, 1185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool AllowModify) const; 1198bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 1205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 12146d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) MachineBasicBlock *FBB, 12246d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) const SmallVectorImpl<MachineOperand> &Cond, 12346d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) DebugLoc DL) const; 12446d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) 1258bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) // Select analysis. 126d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) virtual bool canInsertSelect(const MachineBasicBlock&, 1275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const SmallVectorImpl<MachineOperand> &Cond, 12846d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) unsigned, unsigned, int&, int&, int&) const; 12946d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) virtual void insertSelect(MachineBasicBlock &MBB, 13046d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) MachineBasicBlock::iterator MI, DebugLoc DL, 13146d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) unsigned DstReg, 13246d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) const SmallVectorImpl<MachineOperand> &Cond, 1338bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) unsigned TrueReg, unsigned FalseReg) const; 134d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 1355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual void copyPhysReg(MachineBasicBlock &MBB, 1365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineBasicBlock::iterator I, DebugLoc DL, 1372a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) unsigned DestReg, unsigned SrcReg, 1382a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) bool KillSrc) const; 13946d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) 14046d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 1415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineBasicBlock::iterator MBBI, 1428bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) unsigned SrcReg, bool isKill, int FrameIndex, 1435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterClass *RC, 14446d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) const TargetRegisterInfo *TRI) const; 14590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 1468bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles) virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 147d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) MachineBasicBlock::iterator MBBI, 148d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) unsigned DestReg, int FrameIndex, 1495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterClass *RC, 1505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterInfo *TRI) const; 1515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 152 virtual 153 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 154 155 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 156 unsigned Reg, MachineRegisterInfo *MRI) const; 157 158 // If conversion by predication (only supported by some branch instructions). 159 // All of the profitability checks always return true; it is always 160 // profitable to use the predicated branches. 161 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, 162 unsigned NumCycles, unsigned ExtraPredCycles, 163 const BranchProbability &Probability) const { 164 return true; 165 } 166 167 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 168 unsigned NumT, unsigned ExtraT, 169 MachineBasicBlock &FMBB, 170 unsigned NumF, unsigned ExtraF, 171 const BranchProbability &Probability) const; 172 173 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, 174 unsigned NumCycles, 175 const BranchProbability 176 &Probability) const { 177 return true; 178 } 179 180 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 181 MachineBasicBlock &FMBB) const { 182 return false; 183 } 184 185 // Predication support. 186 bool isPredicated(const MachineInstr *MI) const; 187 188 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 189 190 virtual 191 bool PredicateInstruction(MachineInstr *MI, 192 const SmallVectorImpl<MachineOperand> &Pred) const; 193 194 virtual 195 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 196 const SmallVectorImpl<MachineOperand> &Pred2) const; 197 198 virtual bool DefinesPredicate(MachineInstr *MI, 199 std::vector<MachineOperand> &Pred) const; 200 201 virtual bool isPredicable(MachineInstr *MI) const; 202 203 // Comparison optimization. 204 205 206 virtual bool analyzeCompare(const MachineInstr *MI, 207 unsigned &SrcReg, unsigned &SrcReg2, 208 int &Mask, int &Value) const; 209 210 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, 211 unsigned SrcReg, unsigned SrcReg2, 212 int Mask, int Value, 213 const MachineRegisterInfo *MRI) const; 214 215 /// GetInstSize - Return the number of bytes of code the specified 216 /// instruction may be. This returns the maximum number of bytes. 217 /// 218 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 219}; 220 221} 222 223#endif 224