PPCInstrInfo.h revision 5a364c5561ec04e33a6f5d52c14f1bac6f247ea0 
1//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef POWERPC_INSTRUCTIONINFO_H
15#define POWERPC_INSTRUCTIONINFO_H
16
17#include "PPC.h"
18#include "PPCRegisterInfo.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "PPCGenInstrInfo.inc"
23
24namespace llvm {
25
26/// PPCII - This namespace holds all of the PowerPC target-specific
27/// per-instruction flags.  These must match the corresponding definitions in
28/// PPC.td and PPCInstrFormats.td.
29namespace PPCII {
30enum {
31  // PPC970 Instruction Flags.  These flags describe the characteristics of the
32  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
33  // raw machine instructions.
34
35  /// PPC970_First - This instruction starts a new dispatch group, so it will
36  /// always be the first one in the group.
37  PPC970_First = 0x1,
38
39  /// PPC970_Single - This instruction starts a new dispatch group and
40  /// terminates it, so it will be the sole instruction in the group.
41  PPC970_Single = 0x2,
42
43  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
44  /// two dispatch pipes to be available to issue.
45  PPC970_Cracked = 0x4,
46
47  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
48  /// an instruction is issued to.
49  PPC970_Shift = 3,
50  PPC970_Mask = 0x07 << PPC970_Shift
51};
52enum PPC970_Unit {
53  /// These are the various PPC970 execution unit pipelines.  Each instruction
54  /// is one of these.
55  PPC970_Pseudo = 0 << PPC970_Shift,   // Pseudo instruction
56  PPC970_FXU    = 1 << PPC970_Shift,   // Fixed Point (aka Integer/ALU) Unit
57  PPC970_LSU    = 2 << PPC970_Shift,   // Load Store Unit
58  PPC970_FPU    = 3 << PPC970_Shift,   // Floating Point Unit
59  PPC970_CRU    = 4 << PPC970_Shift,   // Control Register Unit
60  PPC970_VALU   = 5 << PPC970_Shift,   // Vector ALU
61  PPC970_VPERM  = 6 << PPC970_Shift,   // Vector Permute Unit
62  PPC970_BRU    = 7 << PPC970_Shift    // Branch Unit
63};
64} // end namespace PPCII
65
66
67class PPCInstrInfo : public PPCGenInstrInfo {
68  PPCTargetMachine &TM;
69  const PPCRegisterInfo RI;
70
71  bool StoreRegToStackSlot(MachineFunction &MF,
72                           unsigned SrcReg, bool isKill, int FrameIdx,
73                           const TargetRegisterClass *RC,
74                           SmallVectorImpl<MachineInstr*> &NewMIs,
75                           bool &NonRI, bool &SpillsVRS) const;
76  bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
77                            unsigned DestReg, int FrameIdx,
78                            const TargetRegisterClass *RC,
79                            SmallVectorImpl<MachineInstr*> &NewMIs,
80                            bool &NonRI, bool &SpillsVRS) const;
81  virtual void anchor();
82public:
83  explicit PPCInstrInfo(PPCTargetMachine &TM);
84
85  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
86  /// such, whenever a client has an instance of instruction info, it should
87  /// always be able to get register info as well (through this method).
88  ///
89  virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
90
91  ScheduleHazardRecognizer *
92  CreateTargetHazardRecognizer(const TargetMachine *TM,
93                               const ScheduleDAG *DAG) const;
94  ScheduleHazardRecognizer *
95  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
96                                     const ScheduleDAG *DAG) const;
97
98  bool isCoalescableExtInstr(const MachineInstr &MI,
99                             unsigned &SrcReg, unsigned &DstReg,
100                             unsigned &SubIdx) const;
101  unsigned isLoadFromStackSlot(const MachineInstr *MI,
102                               int &FrameIndex) const;
103  unsigned isStoreToStackSlot(const MachineInstr *MI,
104                              int &FrameIndex) const;
105
106  // commuteInstruction - We can commute rlwimi instructions, but only if the
107  // rotate amt is zero.  We also have to munge the immediates a bit.
108  virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
109
110  virtual void insertNoop(MachineBasicBlock &MBB,
111                          MachineBasicBlock::iterator MI) const;
112
113
114  // Branch analysis.
115  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
116                             MachineBasicBlock *&FBB,
117                             SmallVectorImpl<MachineOperand> &Cond,
118                             bool AllowModify) const;
119  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
120  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
121                                MachineBasicBlock *FBB,
122                                const SmallVectorImpl<MachineOperand> &Cond,
123                                DebugLoc DL) const;
124
125  // Select analysis.
126  virtual bool canInsertSelect(const MachineBasicBlock&,
127                               const SmallVectorImpl<MachineOperand> &Cond,
128                               unsigned, unsigned, int&, int&, int&) const;
129  virtual void insertSelect(MachineBasicBlock &MBB,
130                            MachineBasicBlock::iterator MI, DebugLoc DL,
131                            unsigned DstReg,
132                            const SmallVectorImpl<MachineOperand> &Cond,
133                            unsigned TrueReg, unsigned FalseReg) const;
134
135  virtual void copyPhysReg(MachineBasicBlock &MBB,
136                           MachineBasicBlock::iterator I, DebugLoc DL,
137                           unsigned DestReg, unsigned SrcReg,
138                           bool KillSrc) const;
139
140  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
141                                   MachineBasicBlock::iterator MBBI,
142                                   unsigned SrcReg, bool isKill, int FrameIndex,
143                                   const TargetRegisterClass *RC,
144                                   const TargetRegisterInfo *TRI) const;
145
146  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
147                                    MachineBasicBlock::iterator MBBI,
148                                    unsigned DestReg, int FrameIndex,
149                                    const TargetRegisterClass *RC,
150                                    const TargetRegisterInfo *TRI) const;
151
152  virtual
153  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
154
155  virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
156                             unsigned Reg, MachineRegisterInfo *MRI) const;
157
158  // If conversion by predication (only supported by some branch instructions).
159  // All of the profitability checks always return true; it is always
160  // profitable to use the predicated branches.
161  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
162                                   unsigned NumCycles, unsigned ExtraPredCycles,
163                                   const BranchProbability &Probability) const {
164    return true;
165  }
166
167  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
168                                   unsigned NumT, unsigned ExtraT,
169                                   MachineBasicBlock &FMBB,
170                                   unsigned NumF, unsigned ExtraF,
171                                   const BranchProbability &Probability) const;
172
173  virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
174                                         unsigned NumCycles,
175                                         const BranchProbability
176                                         &Probability) const {
177    return true;
178  }
179
180  virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
181                                         MachineBasicBlock &FMBB) const {
182    return false;
183  }
184
185  // Predication support.
186  bool isPredicated(const MachineInstr *MI) const;
187
188  virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
189
190  virtual
191  bool PredicateInstruction(MachineInstr *MI,
192                            const SmallVectorImpl<MachineOperand> &Pred) const;
193
194  virtual
195  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
196                         const SmallVectorImpl<MachineOperand> &Pred2) const;
197
198  virtual bool DefinesPredicate(MachineInstr *MI,
199                                std::vector<MachineOperand> &Pred) const;
200
201  virtual bool isPredicable(MachineInstr *MI) const;
202
203  // Comparison optimization.
204
205
206  virtual bool analyzeCompare(const MachineInstr *MI,
207                              unsigned &SrcReg, unsigned &SrcReg2,
208                              int &Mask, int &Value) const;
209
210  virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
211                                    unsigned SrcReg, unsigned SrcReg2,
212                                    int Mask, int Value,
213                                    const MachineRegisterInfo *MRI) const;
214
215  /// GetInstSize - Return the number of bytes of code the specified
216  /// instruction may be.  This returns the maximum number of bytes.
217  ///
218  virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
219};
220
221}
222
223#endif
224