PPCInstrInfo.h revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 
1//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef POWERPC_INSTRUCTIONINFO_H
15#define POWERPC_INSTRUCTIONINFO_H
16
17#include "PPC.h"
18#include "PPCRegisterInfo.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "PPCGenInstrInfo.inc"
23
24namespace llvm {
25
26/// PPCII - This namespace holds all of the PowerPC target-specific
27/// per-instruction flags.  These must match the corresponding definitions in
28/// PPC.td and PPCInstrFormats.td.
29namespace PPCII {
30enum {
31  // PPC970 Instruction Flags.  These flags describe the characteristics of the
32  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
33  // raw machine instructions.
34
35  /// PPC970_First - This instruction starts a new dispatch group, so it will
36  /// always be the first one in the group.
37  PPC970_First = 0x1,
38
39  /// PPC970_Single - This instruction starts a new dispatch group and
40  /// terminates it, so it will be the sole instruction in the group.
41  PPC970_Single = 0x2,
42
43  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
44  /// two dispatch pipes to be available to issue.
45  PPC970_Cracked = 0x4,
46
47  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
48  /// an instruction is issued to.
49  PPC970_Shift = 3,
50  PPC970_Mask = 0x07 << PPC970_Shift
51};
52enum PPC970_Unit {
53  /// These are the various PPC970 execution unit pipelines.  Each instruction
54  /// is one of these.
55  PPC970_Pseudo = 0 << PPC970_Shift,   // Pseudo instruction
56  PPC970_FXU    = 1 << PPC970_Shift,   // Fixed Point (aka Integer/ALU) Unit
57  PPC970_LSU    = 2 << PPC970_Shift,   // Load Store Unit
58  PPC970_FPU    = 3 << PPC970_Shift,   // Floating Point Unit
59  PPC970_CRU    = 4 << PPC970_Shift,   // Control Register Unit
60  PPC970_VALU   = 5 << PPC970_Shift,   // Vector ALU
61  PPC970_VPERM  = 6 << PPC970_Shift,   // Vector Permute Unit
62  PPC970_BRU    = 7 << PPC970_Shift    // Branch Unit
63};
64} // end namespace PPCII
65
66
67class PPCInstrInfo : public PPCGenInstrInfo {
68  PPCSubtarget &Subtarget;
69  const PPCRegisterInfo RI;
70
71  bool StoreRegToStackSlot(MachineFunction &MF,
72                           unsigned SrcReg, bool isKill, int FrameIdx,
73                           const TargetRegisterClass *RC,
74                           SmallVectorImpl<MachineInstr*> &NewMIs,
75                           bool &NonRI, bool &SpillsVRS) const;
76  bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
77                            unsigned DestReg, int FrameIdx,
78                            const TargetRegisterClass *RC,
79                            SmallVectorImpl<MachineInstr*> &NewMIs,
80                            bool &NonRI, bool &SpillsVRS) const;
81  virtual void anchor();
82public:
83  explicit PPCInstrInfo(PPCSubtarget &STI);
84
85  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
86  /// such, whenever a client has an instance of instruction info, it should
87  /// always be able to get register info as well (through this method).
88  ///
89  const PPCRegisterInfo &getRegisterInfo() const { return RI; }
90
91  ScheduleHazardRecognizer *
92  CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
93                               const ScheduleDAG *DAG) const override;
94  ScheduleHazardRecognizer *
95  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
96                                     const ScheduleDAG *DAG) const override;
97
98  int getOperandLatency(const InstrItineraryData *ItinData,
99                        const MachineInstr *DefMI, unsigned DefIdx,
100                        const MachineInstr *UseMI,
101                        unsigned UseIdx) const override;
102  int getOperandLatency(const InstrItineraryData *ItinData,
103                        SDNode *DefNode, unsigned DefIdx,
104                        SDNode *UseNode, unsigned UseIdx) const override {
105    return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
106                                              UseNode, UseIdx);
107  }
108
109  bool isCoalescableExtInstr(const MachineInstr &MI,
110                             unsigned &SrcReg, unsigned &DstReg,
111                             unsigned &SubIdx) const override;
112  unsigned isLoadFromStackSlot(const MachineInstr *MI,
113                               int &FrameIndex) const override;
114  unsigned isStoreToStackSlot(const MachineInstr *MI,
115                              int &FrameIndex) const override;
116
117  // commuteInstruction - We can commute rlwimi instructions, but only if the
118  // rotate amt is zero.  We also have to munge the immediates a bit.
119  MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
120
121  bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
122                             unsigned &SrcOpIdx2) const override;
123
124  void insertNoop(MachineBasicBlock &MBB,
125                  MachineBasicBlock::iterator MI) const override;
126
127
128  // Branch analysis.
129  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
130                     MachineBasicBlock *&FBB,
131                     SmallVectorImpl<MachineOperand> &Cond,
132                     bool AllowModify) const override;
133  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
134  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
135                        MachineBasicBlock *FBB,
136                        const SmallVectorImpl<MachineOperand> &Cond,
137                        DebugLoc DL) const override;
138
139  // Select analysis.
140  bool canInsertSelect(const MachineBasicBlock&,
141                       const SmallVectorImpl<MachineOperand> &Cond,
142                       unsigned, unsigned, int&, int&, int&) const override;
143  void insertSelect(MachineBasicBlock &MBB,
144                    MachineBasicBlock::iterator MI, DebugLoc DL,
145                    unsigned DstReg,
146                    const SmallVectorImpl<MachineOperand> &Cond,
147                    unsigned TrueReg, unsigned FalseReg) const override;
148
149  void copyPhysReg(MachineBasicBlock &MBB,
150                   MachineBasicBlock::iterator I, DebugLoc DL,
151                   unsigned DestReg, unsigned SrcReg,
152                   bool KillSrc) const override;
153
154  void storeRegToStackSlot(MachineBasicBlock &MBB,
155                           MachineBasicBlock::iterator MBBI,
156                           unsigned SrcReg, bool isKill, int FrameIndex,
157                           const TargetRegisterClass *RC,
158                           const TargetRegisterInfo *TRI) const override;
159
160  void loadRegFromStackSlot(MachineBasicBlock &MBB,
161                            MachineBasicBlock::iterator MBBI,
162                            unsigned DestReg, int FrameIndex,
163                            const TargetRegisterClass *RC,
164                            const TargetRegisterInfo *TRI) const override;
165
166  bool
167  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
168
169  bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
170                     unsigned Reg, MachineRegisterInfo *MRI) const override;
171
172  // If conversion by predication (only supported by some branch instructions).
173  // All of the profitability checks always return true; it is always
174  // profitable to use the predicated branches.
175  bool isProfitableToIfCvt(MachineBasicBlock &MBB,
176                          unsigned NumCycles, unsigned ExtraPredCycles,
177                          const BranchProbability &Probability) const override {
178    return true;
179  }
180
181  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
182                           unsigned NumT, unsigned ExtraT,
183                           MachineBasicBlock &FMBB,
184                           unsigned NumF, unsigned ExtraF,
185                           const BranchProbability &Probability) const override;
186
187  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
188                                 unsigned NumCycles,
189                                 const BranchProbability
190                                 &Probability) const override {
191    return true;
192  }
193
194  bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
195                                 MachineBasicBlock &FMBB) const override {
196    return false;
197  }
198
199  // Predication support.
200  bool isPredicated(const MachineInstr *MI) const override;
201
202  bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
203
204  bool PredicateInstruction(MachineInstr *MI,
205                    const SmallVectorImpl<MachineOperand> &Pred) const override;
206
207  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
208                   const SmallVectorImpl<MachineOperand> &Pred2) const override;
209
210  bool DefinesPredicate(MachineInstr *MI,
211                        std::vector<MachineOperand> &Pred) const override;
212
213  bool isPredicable(MachineInstr *MI) const override;
214
215  // Comparison optimization.
216
217
218  bool analyzeCompare(const MachineInstr *MI,
219                      unsigned &SrcReg, unsigned &SrcReg2,
220                      int &Mask, int &Value) const override;
221
222  bool optimizeCompareInstr(MachineInstr *CmpInstr,
223                            unsigned SrcReg, unsigned SrcReg2,
224                            int Mask, int Value,
225                            const MachineRegisterInfo *MRI) const override;
226
227  /// GetInstSize - Return the number of bytes of code the specified
228  /// instruction may be.  This returns the maximum number of bytes.
229  ///
230  unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
231};
232
233}
234
235#endif
236