PPCInstrInfo.td revision 00e86ad167e2d151d819ae7b691dadf9e1d9418c
1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 24 SDTCisVT<0, f64>, SDTCisPtrTy<1> 25]>; 26 27def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 28def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 29 SDTCisVT<1, i32> ]>; 30def SDT_PPCvperm : SDTypeProfile<1, 3, [ 31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 32]>; 33 34def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 36]>; 37 38def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 40]>; 41 42def SDT_PPClbrx : SDTypeProfile<1, 2, [ 43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 44]>; 45def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 47]>; 48 49def SDT_PPClarx : SDTypeProfile<1, 1, [ 50 SDTCisInt<0>, SDTCisPtrTy<1> 51]>; 52def SDT_PPCstcx : SDTypeProfile<0, 2, [ 53 SDTCisInt<0>, SDTCisPtrTy<1> 54]>; 55 56def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 57 SDTCisPtrTy<0>, SDTCisVT<1, i32> 58]>; 59 60 61//===----------------------------------------------------------------------===// 62// PowerPC specific DAG Nodes. 63// 64 65def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 66def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 67 68def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 69def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 70def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 71def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 72def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 73def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 74def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 75def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 76def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 77 [SDNPHasChain, SDNPMayStore]>; 78def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 79 [SDNPHasChain, SDNPMayLoad]>; 80def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 81 [SDNPHasChain, SDNPMayLoad]>; 82 83// Extract FPSCR (not modeled at the DAG level). 84def PPCmffs : SDNode<"PPCISD::MFFS", 85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>; 86 87// Perform FADD in round-to-zero mode. 88def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 89 90 91def PPCfsel : SDNode<"PPCISD::FSEL", 92 // Type constraint for fsel. 93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 95 96def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 97def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 98def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>; 99def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 100def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 101 102def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 103def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 104 [SDNPMayLoad]>; 105def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 106def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 107def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 108def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 109def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 110def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 111def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 112def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp, 113 [SDNPHasChain]>; 114def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 115 116def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 117 118// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 119// amounts. These nodes are generated by the multi-precision shift code. 120def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 121def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 122def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 123 124// These are target-independent nodes, but have target-specific formats. 125def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 126 [SDNPHasChain, SDNPOutGlue]>; 127def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 129 130def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 131def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 133 SDNPVariadic]>; 134def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 136 SDNPVariadic]>; 137def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>, 138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 139def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>, 140 [SDNPHasChain, SDNPSideEffect, 141 SDNPInGlue, SDNPOutGlue]>; 142def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>, 143 [SDNPHasChain, SDNPSideEffect, 144 SDNPInGlue, SDNPOutGlue]>; 145def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 147def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 149 SDNPVariadic]>; 150 151def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 153 154def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 156 157def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 158 SDTypeProfile<1, 1, [SDTCisInt<0>, 159 SDTCisPtrTy<1>]>, 160 [SDNPHasChain, SDNPSideEffect]>; 161def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 162 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 163 [SDNPHasChain, SDNPSideEffect]>; 164 165def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 166def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 167 168def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 169 [SDNPHasChain, SDNPOptInGlue]>; 170 171def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 172 [SDNPHasChain, SDNPMayLoad]>; 173def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 174 [SDNPHasChain, SDNPMayStore]>; 175 176// Instructions to set/unset CR bit 6 for SVR4 vararg calls 177def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 178 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 179def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 180 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 181 182// Instructions to support atomic operations 183def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, 184 [SDNPHasChain, SDNPMayLoad]>; 185def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, 186 [SDNPHasChain, SDNPMayStore]>; 187 188// Instructions to support medium and large code model 189def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>; 190def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>; 191def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>; 192 193 194// Instructions to support dynamic alloca. 195def SDTDynOp : SDTypeProfile<1, 2, []>; 196def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 197 198//===----------------------------------------------------------------------===// 199// PowerPC specific transformation functions and pattern fragments. 200// 201 202def SHL32 : SDNodeXForm<imm, [{ 203 // Transformation function: 31 - imm 204 return getI32Imm(31 - N->getZExtValue()); 205}]>; 206 207def SRL32 : SDNodeXForm<imm, [{ 208 // Transformation function: 32 - imm 209 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0); 210}]>; 211 212def LO16 : SDNodeXForm<imm, [{ 213 // Transformation function: get the low 16 bits. 214 return getI32Imm((unsigned short)N->getZExtValue()); 215}]>; 216 217def HI16 : SDNodeXForm<imm, [{ 218 // Transformation function: shift the immediate value down into the low bits. 219 return getI32Imm((unsigned)N->getZExtValue() >> 16); 220}]>; 221 222def HA16 : SDNodeXForm<imm, [{ 223 // Transformation function: shift the immediate value down into the low bits. 224 signed int Val = N->getZExtValue(); 225 return getI32Imm((Val - (signed short)Val) >> 16); 226}]>; 227def MB : SDNodeXForm<imm, [{ 228 // Transformation function: get the start bit of a mask 229 unsigned mb = 0, me; 230 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 231 return getI32Imm(mb); 232}]>; 233 234def ME : SDNodeXForm<imm, [{ 235 // Transformation function: get the end bit of a mask 236 unsigned mb, me = 0; 237 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 238 return getI32Imm(me); 239}]>; 240def maskimm32 : PatLeaf<(imm), [{ 241 // maskImm predicate - True if immediate is a run of ones. 242 unsigned mb, me; 243 if (N->getValueType(0) == MVT::i32) 244 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 245 else 246 return false; 247}]>; 248 249def immSExt16 : PatLeaf<(imm), [{ 250 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 251 // field. Used by instructions like 'addi'. 252 if (N->getValueType(0) == MVT::i32) 253 return (int32_t)N->getZExtValue() == (short)N->getZExtValue(); 254 else 255 return (int64_t)N->getZExtValue() == (short)N->getZExtValue(); 256}]>; 257def immZExt16 : PatLeaf<(imm), [{ 258 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 259 // field. Used by instructions like 'ori'. 260 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 261}], LO16>; 262 263// imm16Shifted* - These match immediates where the low 16-bits are zero. There 264// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 265// identical in 32-bit mode, but in 64-bit mode, they return true if the 266// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 267// clear). 268def imm16ShiftedZExt : PatLeaf<(imm), [{ 269 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 270 // immediate are set. Used by instructions like 'xoris'. 271 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 272}], HI16>; 273 274def imm16ShiftedSExt : PatLeaf<(imm), [{ 275 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 276 // immediate are set. Used by instructions like 'addis'. Identical to 277 // imm16ShiftedZExt in 32-bit mode. 278 if (N->getZExtValue() & 0xFFFF) return false; 279 if (N->getValueType(0) == MVT::i32) 280 return true; 281 // For 64-bit, make sure it is sext right. 282 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 283}], HI16>; 284 285// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 286// restricted memrix (offset/4) constants are alignment sensitive. If these 287// offsets are hidden behind TOC entries than the values of the lower-order 288// bits cannot be checked directly. As a result, we need to also incorporate 289// an alignment check into the relevant patterns. 290 291def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 292 return cast<LoadSDNode>(N)->getAlignment() >= 4; 293}]>; 294def aligned4store : PatFrag<(ops node:$val, node:$ptr), 295 (store node:$val, node:$ptr), [{ 296 return cast<StoreSDNode>(N)->getAlignment() >= 4; 297}]>; 298def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 299 return cast<LoadSDNode>(N)->getAlignment() >= 4; 300}]>; 301def aligned4pre_store : PatFrag< 302 (ops node:$val, node:$base, node:$offset), 303 (pre_store node:$val, node:$base, node:$offset), [{ 304 return cast<StoreSDNode>(N)->getAlignment() >= 4; 305}]>; 306 307def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 308 return cast<LoadSDNode>(N)->getAlignment() < 4; 309}]>; 310def unaligned4store : PatFrag<(ops node:$val, node:$ptr), 311 (store node:$val, node:$ptr), [{ 312 return cast<StoreSDNode>(N)->getAlignment() < 4; 313}]>; 314def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 315 return cast<LoadSDNode>(N)->getAlignment() < 4; 316}]>; 317 318//===----------------------------------------------------------------------===// 319// PowerPC Flag Definitions. 320 321class isPPC64 { bit PPC64 = 1; } 322class isDOT { bit RC = 1; } 323 324class RegConstraint<string C> { 325 string Constraints = C; 326} 327class NoEncode<string E> { 328 string DisableEncoding = E; 329} 330 331 332//===----------------------------------------------------------------------===// 333// PowerPC Operand Definitions. 334 335def s5imm : Operand<i32> { 336 let PrintMethod = "printS5ImmOperand"; 337} 338def u5imm : Operand<i32> { 339 let PrintMethod = "printU5ImmOperand"; 340} 341def u6imm : Operand<i32> { 342 let PrintMethod = "printU6ImmOperand"; 343} 344def s16imm : Operand<i32> { 345 let PrintMethod = "printS16ImmOperand"; 346} 347def u16imm : Operand<i32> { 348 let PrintMethod = "printU16ImmOperand"; 349} 350def directbrtarget : Operand<OtherVT> { 351 let PrintMethod = "printBranchOperand"; 352 let EncoderMethod = "getDirectBrEncoding"; 353} 354def condbrtarget : Operand<OtherVT> { 355 let PrintMethod = "printBranchOperand"; 356 let EncoderMethod = "getCondBrEncoding"; 357} 358def calltarget : Operand<iPTR> { 359 let EncoderMethod = "getDirectBrEncoding"; 360} 361def aaddr : Operand<iPTR> { 362 let PrintMethod = "printAbsAddrOperand"; 363} 364def symbolHi: Operand<i32> { 365 let PrintMethod = "printSymbolHi"; 366 let EncoderMethod = "getHA16Encoding"; 367} 368def symbolLo: Operand<i32> { 369 let PrintMethod = "printSymbolLo"; 370 let EncoderMethod = "getLO16Encoding"; 371} 372def crbitm: Operand<i8> { 373 let PrintMethod = "printcrbitm"; 374 let EncoderMethod = "get_crbitm_encoding"; 375} 376// Address operands 377// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 378def ptr_rc_nor0 : PointerLikeRegClass<1>; 379 380def dispRI : Operand<iPTR>; 381def dispRIX : Operand<iPTR>; 382 383def memri : Operand<iPTR> { 384 let PrintMethod = "printMemRegImm"; 385 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 386 let EncoderMethod = "getMemRIEncoding"; 387} 388def memrr : Operand<iPTR> { 389 let PrintMethod = "printMemRegReg"; 390 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc:$offreg); 391} 392def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 393 let PrintMethod = "printMemRegImmShifted"; 394 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 395 let EncoderMethod = "getMemRIXEncoding"; 396} 397 398// A single-register address. This is used with the SjLj 399// pseudo-instructions. 400def memr : Operand<iPTR> { 401 let MIOperandInfo = (ops ptr_rc:$ptrreg); 402} 403 404// PowerPC Predicate operand. 405def pred : Operand<OtherVT> { 406 let PrintMethod = "printPredicateOperand"; 407 let MIOperandInfo = (ops i32imm:$bibo, CRRC:$reg); 408} 409 410// Define PowerPC specific addressing mode. 411def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 412def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 413def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 414def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 415 416// The address in a single register. This is used with the SjLj 417// pseudo-instructions. 418def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 419 420/// This is just the offset part of iaddr, used for preinc. 421def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 422 423//===----------------------------------------------------------------------===// 424// PowerPC Instruction Predicate Definitions. 425def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">; 426def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">; 427def IsBookE : Predicate<"PPCSubTarget.isBookE()">; 428 429//===----------------------------------------------------------------------===// 430// PowerPC Multiclass Definitions. 431 432multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 433 string asmbase, string asmstr, InstrItinClass itin, 434 list<dag> pattern> { 435 let BaseName = asmbase in { 436 def NAME : XForm_6<opcode, xo, OOL, IOL, 437 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 438 pattern>, RecFormRel; 439 let Defs = [CR0] in 440 def o : XForm_6<opcode, xo, OOL, IOL, 441 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 442 []>, isDOT, RecFormRel; 443 } 444} 445 446multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 447 string asmbase, string asmstr, InstrItinClass itin, 448 list<dag> pattern> { 449 let BaseName = asmbase in { 450 let Defs = [CARRY] in 451 def NAME : XForm_6<opcode, xo, OOL, IOL, 452 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 453 pattern>, RecFormRel; 454 let Defs = [CARRY, CR0] in 455 def o : XForm_6<opcode, xo, OOL, IOL, 456 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 457 []>, isDOT, RecFormRel; 458 } 459} 460 461multiclass XForm_10r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 462 string asmbase, string asmstr, InstrItinClass itin, 463 list<dag> pattern> { 464 let BaseName = asmbase in { 465 def NAME : XForm_10<opcode, xo, OOL, IOL, 466 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 467 pattern>, RecFormRel; 468 let Defs = [CR0] in 469 def o : XForm_10<opcode, xo, OOL, IOL, 470 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 471 []>, isDOT, RecFormRel; 472 } 473} 474 475multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 476 string asmbase, string asmstr, InstrItinClass itin, 477 list<dag> pattern> { 478 let BaseName = asmbase in { 479 let Defs = [CARRY] in 480 def NAME : XForm_10<opcode, xo, OOL, IOL, 481 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 482 pattern>, RecFormRel; 483 let Defs = [CARRY, CR0] in 484 def o : XForm_10<opcode, xo, OOL, IOL, 485 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 486 []>, isDOT, RecFormRel; 487 } 488} 489 490multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 491 string asmbase, string asmstr, InstrItinClass itin, 492 list<dag> pattern> { 493 let BaseName = asmbase in { 494 def NAME : XForm_11<opcode, xo, OOL, IOL, 495 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 496 pattern>, RecFormRel; 497 let Defs = [CR0] in 498 def o : XForm_11<opcode, xo, OOL, IOL, 499 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 500 []>, isDOT, RecFormRel; 501 } 502} 503 504multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 505 string asmbase, string asmstr, InstrItinClass itin, 506 list<dag> pattern> { 507 let BaseName = asmbase in { 508 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 509 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 510 pattern>, RecFormRel; 511 let Defs = [CR0] in 512 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 513 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 514 []>, isDOT, RecFormRel; 515 } 516} 517 518multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 519 string asmbase, string asmstr, InstrItinClass itin, 520 list<dag> pattern> { 521 let BaseName = asmbase in { 522 let Defs = [CARRY] in 523 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 524 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 525 pattern>, RecFormRel; 526 let Defs = [CARRY, CR0] in 527 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 528 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 529 []>, isDOT, RecFormRel; 530 } 531} 532 533multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 534 string asmbase, string asmstr, InstrItinClass itin, 535 list<dag> pattern> { 536 let BaseName = asmbase in { 537 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 538 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 539 pattern>, RecFormRel; 540 let Defs = [CR0] in 541 def o : XOForm_3<opcode, xo, oe, OOL, IOL, 542 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 543 []>, isDOT, RecFormRel; 544 } 545} 546 547multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 548 string asmbase, string asmstr, InstrItinClass itin, 549 list<dag> pattern> { 550 let BaseName = asmbase in { 551 let Defs = [CARRY] in 552 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 553 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 554 pattern>, RecFormRel; 555 let Defs = [CARRY, CR0] in 556 def o : XOForm_3<opcode, xo, oe, OOL, IOL, 557 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 558 []>, isDOT, RecFormRel; 559 } 560} 561 562multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 563 string asmbase, string asmstr, InstrItinClass itin, 564 list<dag> pattern> { 565 let BaseName = asmbase in { 566 def NAME : MForm_2<opcode, OOL, IOL, 567 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 568 pattern>, RecFormRel; 569 let Defs = [CR0] in 570 def o : MForm_2<opcode, OOL, IOL, 571 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 572 []>, isDOT, RecFormRel; 573 } 574} 575 576multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 577 string asmbase, string asmstr, InstrItinClass itin, 578 list<dag> pattern> { 579 let BaseName = asmbase in { 580 def NAME : MDForm_1<opcode, xo, OOL, IOL, 581 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 582 pattern>, RecFormRel; 583 let Defs = [CR0] in 584 def o : MDForm_1<opcode, xo, OOL, IOL, 585 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 586 []>, isDOT, RecFormRel; 587 } 588} 589 590multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 591 string asmbase, string asmstr, InstrItinClass itin, 592 list<dag> pattern> { 593 let BaseName = asmbase in { 594 let Defs = [CARRY] in 595 def NAME : XSForm_1<opcode, xo, OOL, IOL, 596 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 597 pattern>, RecFormRel; 598 let Defs = [CARRY, CR0] in 599 def o : XSForm_1<opcode, xo, OOL, IOL, 600 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 601 []>, isDOT, RecFormRel; 602 } 603} 604 605multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 606 string asmbase, string asmstr, InstrItinClass itin, 607 list<dag> pattern> { 608 let BaseName = asmbase in { 609 def NAME : XForm_26<opcode, xo, OOL, IOL, 610 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 611 pattern>, RecFormRel; 612 let Defs = [CR1] in 613 def o : XForm_26<opcode, xo, OOL, IOL, 614 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 615 []>, isDOT, RecFormRel; 616 } 617} 618 619multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 620 string asmbase, string asmstr, InstrItinClass itin, 621 list<dag> pattern> { 622 let BaseName = asmbase in { 623 def NAME : AForm_1<opcode, xo, OOL, IOL, 624 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 625 pattern>, RecFormRel; 626 let Defs = [CR1] in 627 def o : AForm_1<opcode, xo, OOL, IOL, 628 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 629 []>, isDOT, RecFormRel; 630 } 631} 632 633multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 634 string asmbase, string asmstr, InstrItinClass itin, 635 list<dag> pattern> { 636 let BaseName = asmbase in { 637 def NAME : AForm_2<opcode, xo, OOL, IOL, 638 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 639 pattern>, RecFormRel; 640 let Defs = [CR1] in 641 def o : AForm_2<opcode, xo, OOL, IOL, 642 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 643 []>, isDOT, RecFormRel; 644 } 645} 646 647multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 648 string asmbase, string asmstr, InstrItinClass itin, 649 list<dag> pattern> { 650 let BaseName = asmbase in { 651 def NAME : AForm_3<opcode, xo, OOL, IOL, 652 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 653 pattern>, RecFormRel; 654 let Defs = [CR1] in 655 def o : AForm_3<opcode, xo, OOL, IOL, 656 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 657 []>, isDOT, RecFormRel; 658 } 659} 660 661//===----------------------------------------------------------------------===// 662// PowerPC Instruction Definitions. 663 664// Pseudo-instructions: 665 666let hasCtrlDep = 1 in { 667let Defs = [R1], Uses = [R1] in { 668def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt", 669 [(callseq_start timm:$amt)]>; 670def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2", 671 [(callseq_end timm:$amt1, timm:$amt2)]>; 672} 673 674def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), 675 "UPDATE_VRSAVE $rD, $rS", []>; 676} 677 678let Defs = [R1], Uses = [R1] in 679def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC", 680 [(set i32:$result, 681 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 682 683// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 684// instruction selection into a branch sequence. 685let usesCustomInserter = 1, // Expanded after instruction selection. 686 PPC970_Single = 1 in { 687 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 688 // because either operand might become the first operand in an isel, and 689 // that operand cannot be r0. 690 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, 691 GPRC_NOR0:$T, GPRC_NOR0:$F, 692 i32imm:$BROPC), "#SELECT_CC_I4", 693 []>; 694 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, 695 G8RC_NOX0:$T, G8RC_NOX0:$F, 696 i32imm:$BROPC), "#SELECT_CC_I8", 697 []>; 698 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F, 699 i32imm:$BROPC), "#SELECT_CC_F4", 700 []>; 701 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F, 702 i32imm:$BROPC), "#SELECT_CC_F8", 703 []>; 704 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F, 705 i32imm:$BROPC), "#SELECT_CC_VRRC", 706 []>; 707} 708 709// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 710// scavenge a register for it. 711let mayStore = 1 in 712def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F), 713 "#SPILL_CR", []>; 714 715// RESTORE_CR - Indicate that we're restoring the CR register (previously 716// spilled), so we'll need to scavenge a register for it. 717let mayLoad = 1 in 718def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F), 719 "#RESTORE_CR", []>; 720 721let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 722 let isReturn = 1, Uses = [LR, RM] in 723 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB, 724 [(retflag)]>; 725 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 726 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; 727 728 def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 729 "b${cond:cc}ctr ${cond:reg}", BrB, []>; 730 } 731} 732 733let Defs = [LR] in 734 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>, 735 PPC970_Unit_BRU; 736 737let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 738 let isBarrier = 1 in { 739 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 740 "b $dst", BrB, 741 [(br bb:$dst)]>; 742 } 743 744 // BCC represents an arbitrary conditional branch on a predicate. 745 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 746 // a two-value operand where a dag node expects two operands. :( 747 let isCodeGenOnly = 1 in { 748 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 749 "b${cond:cc} ${cond:reg}, $dst" 750 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; 751 let isReturn = 1, Uses = [LR, RM] in 752 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), 753 "b${cond:cc}lr ${cond:reg}", BrB, []>; 754 755 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 756 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 757 "bdzlr", BrB, []>; 758 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 759 "bdnzlr", BrB, []>; 760 } 761 } 762 763 let Defs = [CTR], Uses = [CTR] in { 764 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 765 "bdz $dst">; 766 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 767 "bdnz $dst">; 768 } 769} 770 771// The unconditional BCL used by the SjLj setjmp code. 772let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in { 773 let Defs = [LR], Uses = [RM] in { 774 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), 775 "bcl 20, 31, $dst">; 776 } 777} 778 779let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 780 // Convenient aliases for call instructions 781 let Uses = [RM] in { 782 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), 783 "bl $func", BrB, []>; // See Pat patterns below. 784 def BLA : IForm<18, 1, 1, (outs), (ins aaddr:$func), 785 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>; 786 } 787 let Uses = [CTR, RM] in { 788 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 789 "bctrl", BrB, [(PPCbctrl)]>, 790 Requires<[In32BitMode]>; 791 def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 792 "b${cond:cc}ctrl ${cond:reg}", BrB, []>; 793 } 794} 795 796let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 797def TCRETURNdi :Pseudo< (outs), 798 (ins calltarget:$dst, i32imm:$offset), 799 "#TC_RETURNd $dst $offset", 800 []>; 801 802 803let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 804def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), 805 "#TC_RETURNa $func $offset", 806 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 807 808let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 809def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 810 "#TC_RETURNr $dst $offset", 811 []>; 812 813 814let isCodeGenOnly = 1 in { 815 816let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 817 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 818def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 819 Requires<[In32BitMode]>; 820 821 822 823let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 824 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 825def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 826 "b $dst", BrB, 827 []>; 828 829} 830 831let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 832 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 833def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 834 "ba $dst", BrB, 835 []>; 836 837let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 838 def EH_SjLj_SetJmp32 : Pseudo<(outs GPRC:$dst), (ins memr:$buf), 839 "#EH_SJLJ_SETJMP32", 840 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 841 Requires<[In32BitMode]>; 842 let isTerminator = 1 in 843 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf), 844 "#EH_SJLJ_LONGJMP32", 845 [(PPCeh_sjlj_longjmp addr:$buf)]>, 846 Requires<[In32BitMode]>; 847} 848 849let isBranch = 1, isTerminator = 1 in { 850 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst), 851 "#EH_SjLj_Setup\t$dst", []>; 852} 853 854// DCB* instructions. 855def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), 856 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 857 PPC970_DGroup_Single; 858def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), 859 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 860 PPC970_DGroup_Single; 861def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), 862 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 863 PPC970_DGroup_Single; 864def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), 865 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 866 PPC970_DGroup_Single; 867def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), 868 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 869 PPC970_DGroup_Single; 870def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), 871 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 872 PPC970_DGroup_Single; 873def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), 874 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 875 PPC970_DGroup_Single; 876def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), 877 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 878 PPC970_DGroup_Single; 879 880def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 881 (DCBT xoaddr:$dst)>; 882 883// Atomic operations 884let usesCustomInserter = 1 in { 885 let Defs = [CR0] in { 886 def ATOMIC_LOAD_ADD_I8 : Pseudo< 887 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8", 888 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>; 889 def ATOMIC_LOAD_SUB_I8 : Pseudo< 890 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8", 891 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>; 892 def ATOMIC_LOAD_AND_I8 : Pseudo< 893 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8", 894 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>; 895 def ATOMIC_LOAD_OR_I8 : Pseudo< 896 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8", 897 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>; 898 def ATOMIC_LOAD_XOR_I8 : Pseudo< 899 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8", 900 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>; 901 def ATOMIC_LOAD_NAND_I8 : Pseudo< 902 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8", 903 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>; 904 def ATOMIC_LOAD_ADD_I16 : Pseudo< 905 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16", 906 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>; 907 def ATOMIC_LOAD_SUB_I16 : Pseudo< 908 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16", 909 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>; 910 def ATOMIC_LOAD_AND_I16 : Pseudo< 911 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16", 912 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>; 913 def ATOMIC_LOAD_OR_I16 : Pseudo< 914 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16", 915 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>; 916 def ATOMIC_LOAD_XOR_I16 : Pseudo< 917 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16", 918 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>; 919 def ATOMIC_LOAD_NAND_I16 : Pseudo< 920 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16", 921 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>; 922 def ATOMIC_LOAD_ADD_I32 : Pseudo< 923 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32", 924 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>; 925 def ATOMIC_LOAD_SUB_I32 : Pseudo< 926 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32", 927 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>; 928 def ATOMIC_LOAD_AND_I32 : Pseudo< 929 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32", 930 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>; 931 def ATOMIC_LOAD_OR_I32 : Pseudo< 932 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32", 933 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>; 934 def ATOMIC_LOAD_XOR_I32 : Pseudo< 935 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32", 936 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>; 937 def ATOMIC_LOAD_NAND_I32 : Pseudo< 938 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32", 939 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>; 940 941 def ATOMIC_CMP_SWAP_I8 : Pseudo< 942 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8", 943 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>; 944 def ATOMIC_CMP_SWAP_I16 : Pseudo< 945 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 946 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>; 947 def ATOMIC_CMP_SWAP_I32 : Pseudo< 948 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 949 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>; 950 951 def ATOMIC_SWAP_I8 : Pseudo< 952 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8", 953 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>; 954 def ATOMIC_SWAP_I16 : Pseudo< 955 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16", 956 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>; 957 def ATOMIC_SWAP_I32 : Pseudo< 958 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32", 959 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>; 960 } 961} 962 963// Instructions to support atomic operations 964def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src), 965 "lwarx $rD, $src", LdStLWARX, 966 [(set i32:$rD, (PPClarx xoaddr:$src))]>; 967 968let Defs = [CR0] in 969def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst), 970 "stwcx. $rS, $dst", LdStSTWCX, 971 [(PPCstcx i32:$rS, xoaddr:$dst)]>, 972 isDOT; 973 974let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 975def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>; 976 977//===----------------------------------------------------------------------===// 978// PPC32 Load Instructions. 979// 980 981// Unindexed (r+i) Loads. 982let canFoldAsLoad = 1, PPC970_Unit = 2 in { 983def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), 984 "lbz $rD, $src", LdStLoad, 985 [(set i32:$rD, (zextloadi8 iaddr:$src))]>; 986def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), 987 "lha $rD, $src", LdStLHA, 988 [(set i32:$rD, (sextloadi16 iaddr:$src))]>, 989 PPC970_DGroup_Cracked; 990def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src), 991 "lhz $rD, $src", LdStLoad, 992 [(set i32:$rD, (zextloadi16 iaddr:$src))]>; 993def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src), 994 "lwz $rD, $src", LdStLoad, 995 [(set i32:$rD, (load iaddr:$src))]>; 996 997def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src), 998 "lfs $rD, $src", LdStLFD, 999 [(set f32:$rD, (load iaddr:$src))]>; 1000def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), 1001 "lfd $rD, $src", LdStLFD, 1002 [(set f64:$rD, (load iaddr:$src))]>; 1003 1004 1005// Unindexed (r+i) Loads with Update (preinc). 1006let mayLoad = 1, neverHasSideEffects = 1 in { 1007def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1008 "lbzu $rD, $addr", LdStLoadUpd, 1009 []>, RegConstraint<"$addr.reg = $ea_result">, 1010 NoEncode<"$ea_result">; 1011 1012def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1013 "lhau $rD, $addr", LdStLHAU, 1014 []>, RegConstraint<"$addr.reg = $ea_result">, 1015 NoEncode<"$ea_result">; 1016 1017def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1018 "lhzu $rD, $addr", LdStLoadUpd, 1019 []>, RegConstraint<"$addr.reg = $ea_result">, 1020 NoEncode<"$ea_result">; 1021 1022def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1023 "lwzu $rD, $addr", LdStLoadUpd, 1024 []>, RegConstraint<"$addr.reg = $ea_result">, 1025 NoEncode<"$ea_result">; 1026 1027def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1028 "lfsu $rD, $addr", LdStLFDU, 1029 []>, RegConstraint<"$addr.reg = $ea_result">, 1030 NoEncode<"$ea_result">; 1031 1032def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1033 "lfdu $rD, $addr", LdStLFDU, 1034 []>, RegConstraint<"$addr.reg = $ea_result">, 1035 NoEncode<"$ea_result">; 1036 1037 1038// Indexed (r+r) Loads with Update (preinc). 1039def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), 1040 (ins memrr:$addr), 1041 "lbzux $rD, $addr", LdStLoadUpd, 1042 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1043 NoEncode<"$ea_result">; 1044 1045def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), 1046 (ins memrr:$addr), 1047 "lhaux $rD, $addr", LdStLHAU, 1048 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1049 NoEncode<"$ea_result">; 1050 1051def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), 1052 (ins memrr:$addr), 1053 "lhzux $rD, $addr", LdStLoadUpd, 1054 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1055 NoEncode<"$ea_result">; 1056 1057def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), 1058 (ins memrr:$addr), 1059 "lwzux $rD, $addr", LdStLoadUpd, 1060 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1061 NoEncode<"$ea_result">; 1062 1063def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc_nor0:$ea_result), 1064 (ins memrr:$addr), 1065 "lfsux $rD, $addr", LdStLFDU, 1066 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1067 NoEncode<"$ea_result">; 1068 1069def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc_nor0:$ea_result), 1070 (ins memrr:$addr), 1071 "lfdux $rD, $addr", LdStLFDU, 1072 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1073 NoEncode<"$ea_result">; 1074} 1075} 1076 1077// Indexed (r+r) Loads. 1078// 1079let canFoldAsLoad = 1, PPC970_Unit = 2 in { 1080def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), 1081 "lbzx $rD, $src", LdStLoad, 1082 [(set i32:$rD, (zextloadi8 xaddr:$src))]>; 1083def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src), 1084 "lhax $rD, $src", LdStLHA, 1085 [(set i32:$rD, (sextloadi16 xaddr:$src))]>, 1086 PPC970_DGroup_Cracked; 1087def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src), 1088 "lhzx $rD, $src", LdStLoad, 1089 [(set i32:$rD, (zextloadi16 xaddr:$src))]>; 1090def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src), 1091 "lwzx $rD, $src", LdStLoad, 1092 [(set i32:$rD, (load xaddr:$src))]>; 1093 1094 1095def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src), 1096 "lhbrx $rD, $src", LdStLoad, 1097 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>; 1098def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src), 1099 "lwbrx $rD, $src", LdStLoad, 1100 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>; 1101 1102def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src), 1103 "lfsx $frD, $src", LdStLFD, 1104 [(set f32:$frD, (load xaddr:$src))]>; 1105def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src), 1106 "lfdx $frD, $src", LdStLFD, 1107 [(set f64:$frD, (load xaddr:$src))]>; 1108 1109def LFIWAX : XForm_25<31, 855, (outs F8RC:$frD), (ins memrr:$src), 1110 "lfiwax $frD, $src", LdStLFD, 1111 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>; 1112def LFIWZX : XForm_25<31, 887, (outs F8RC:$frD), (ins memrr:$src), 1113 "lfiwzx $frD, $src", LdStLFD, 1114 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>; 1115} 1116 1117//===----------------------------------------------------------------------===// 1118// PPC32 Store Instructions. 1119// 1120 1121// Unindexed (r+i) Stores. 1122let PPC970_Unit = 2 in { 1123def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src), 1124 "stb $rS, $src", LdStStore, 1125 [(truncstorei8 i32:$rS, iaddr:$src)]>; 1126def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src), 1127 "sth $rS, $src", LdStStore, 1128 [(truncstorei16 i32:$rS, iaddr:$src)]>; 1129def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src), 1130 "stw $rS, $src", LdStStore, 1131 [(store i32:$rS, iaddr:$src)]>; 1132def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst), 1133 "stfs $rS, $dst", LdStSTFD, 1134 [(store f32:$rS, iaddr:$dst)]>; 1135def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst), 1136 "stfd $rS, $dst", LdStSTFD, 1137 [(store f64:$rS, iaddr:$dst)]>; 1138} 1139 1140// Unindexed (r+i) Stores with Update (preinc). 1141let PPC970_Unit = 2, mayStore = 1 in { 1142def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst), 1143 "stbu $rS, $dst", LdStStoreUpd, []>, 1144 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1145def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst), 1146 "sthu $rS, $dst", LdStStoreUpd, []>, 1147 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1148def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst), 1149 "stwu $rS, $dst", LdStStoreUpd, []>, 1150 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1151def STFSU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memri:$dst), 1152 "stfsu $rS, $dst", LdStSTFDU, []>, 1153 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1154def STFDU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst), 1155 "stfdu $rS, $dst", LdStSTFDU, []>, 1156 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1157} 1158 1159// Patterns to match the pre-inc stores. We can't put the patterns on 1160// the instruction definitions directly as ISel wants the address base 1161// and offset to be separate operands, not a single complex operand. 1162def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1163 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 1164def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1165 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 1166def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1167 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 1168def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1169 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 1170def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1171 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 1172 1173// Indexed (r+r) Stores. 1174let PPC970_Unit = 2 in { 1175def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst), 1176 "stbx $rS, $dst", LdStStore, 1177 [(truncstorei8 i32:$rS, xaddr:$dst)]>, 1178 PPC970_DGroup_Cracked; 1179def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst), 1180 "sthx $rS, $dst", LdStStore, 1181 [(truncstorei16 i32:$rS, xaddr:$dst)]>, 1182 PPC970_DGroup_Cracked; 1183def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst), 1184 "stwx $rS, $dst", LdStStore, 1185 [(store i32:$rS, xaddr:$dst)]>, 1186 PPC970_DGroup_Cracked; 1187 1188def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), 1189 "sthbrx $rS, $dst", LdStStore, 1190 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>, 1191 PPC970_DGroup_Cracked; 1192def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst), 1193 "stwbrx $rS, $dst", LdStStore, 1194 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>, 1195 PPC970_DGroup_Cracked; 1196 1197def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), 1198 "stfiwx $frS, $dst", LdStSTFD, 1199 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>; 1200 1201def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), 1202 "stfsx $frS, $dst", LdStSTFD, 1203 [(store f32:$frS, xaddr:$dst)]>; 1204def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst), 1205 "stfdx $frS, $dst", LdStSTFD, 1206 [(store f64:$frS, xaddr:$dst)]>; 1207} 1208 1209// Indexed (r+r) Stores with Update (preinc). 1210let PPC970_Unit = 2, mayStore = 1 in { 1211def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst), 1212 "stbux $rS, $dst", LdStStoreUpd, []>, 1213 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1214 PPC970_DGroup_Cracked; 1215def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst), 1216 "sthux $rS, $dst", LdStStoreUpd, []>, 1217 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1218 PPC970_DGroup_Cracked; 1219def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst), 1220 "stwux $rS, $dst", LdStStoreUpd, []>, 1221 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1222 PPC970_DGroup_Cracked; 1223def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memrr:$dst), 1224 "stfsux $rS, $dst", LdStSTFDU, []>, 1225 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1226 PPC970_DGroup_Cracked; 1227def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memrr:$dst), 1228 "stfdux $rS, $dst", LdStSTFDU, []>, 1229 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1230 PPC970_DGroup_Cracked; 1231} 1232 1233// Patterns to match the pre-inc stores. We can't put the patterns on 1234// the instruction definitions directly as ISel wants the address base 1235// and offset to be separate operands, not a single complex operand. 1236def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1237 (STBUX $rS, $ptrreg, $ptroff)>; 1238def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1239 (STHUX $rS, $ptrreg, $ptroff)>; 1240def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1241 (STWUX $rS, $ptrreg, $ptroff)>; 1242def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1243 (STFSUX $rS, $ptrreg, $ptroff)>; 1244def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1245 (STFDUX $rS, $ptrreg, $ptroff)>; 1246 1247def SYNC : XForm_24_sync<31, 598, (outs), (ins), 1248 "sync", LdStSync, 1249 [(int_ppc_sync)]>; 1250 1251//===----------------------------------------------------------------------===// 1252// PPC32 Arithmetic Instructions. 1253// 1254 1255let PPC970_Unit = 1 in { // FXU Operations. 1256def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$imm), 1257 "addi $rD, $rA, $imm", IntSimple, 1258 [(set i32:$rD, (add i32:$rA, immSExt16:$imm))]>; 1259let BaseName = "addic" in { 1260let Defs = [CARRY] in 1261def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 1262 "addic $rD, $rA, $imm", IntGeneral, 1263 [(set i32:$rD, (addc i32:$rA, immSExt16:$imm))]>, 1264 RecFormRel, PPC970_DGroup_Cracked; 1265let Defs = [CARRY, CR0] in 1266def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 1267 "addic. $rD, $rA, $imm", IntGeneral, 1268 []>, isDOT, RecFormRel; 1269} 1270def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolHi:$imm), 1271 "addis $rD, $rA, $imm", IntSimple, 1272 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; 1273let isCodeGenOnly = 1 in 1274def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$sym), 1275 "la $rD, $sym($rA)", IntGeneral, 1276 [(set i32:$rD, (add i32:$rA, 1277 (PPClo tglobaladdr:$sym, 0)))]>; 1278def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 1279 "mulli $rD, $rA, $imm", IntMulLI, 1280 [(set i32:$rD, (mul i32:$rA, immSExt16:$imm))]>; 1281let Defs = [CARRY] in 1282def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 1283 "subfic $rD, $rA, $imm", IntGeneral, 1284 [(set i32:$rD, (subc immSExt16:$imm, i32:$rA))]>; 1285 1286let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 1287 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), 1288 "li $rD, $imm", IntSimple, 1289 [(set i32:$rD, immSExt16:$imm)]>; 1290 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), 1291 "lis $rD, $imm", IntSimple, 1292 [(set i32:$rD, imm16ShiftedSExt:$imm)]>; 1293} 1294} 1295 1296let PPC970_Unit = 1 in { // FXU Operations. 1297let Defs = [CR0] in { 1298def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1299 "andi. $dst, $src1, $src2", IntGeneral, 1300 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, 1301 isDOT; 1302def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1303 "andis. $dst, $src1, $src2", IntGeneral, 1304 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, 1305 isDOT; 1306} 1307def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1308 "ori $dst, $src1, $src2", IntSimple, 1309 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; 1310def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1311 "oris $dst, $src1, $src2", IntSimple, 1312 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; 1313def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1314 "xori $dst, $src1, $src2", IntSimple, 1315 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; 1316def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1317 "xoris $dst, $src1, $src2", IntSimple, 1318 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; 1319def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple, 1320 []>; 1321let isCompare = 1, neverHasSideEffects = 1 in { 1322 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm), 1323 "cmpwi $crD, $rA, $imm", IntCompare>; 1324 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1325 "cmplwi $dst, $src1, $src2", IntCompare>; 1326} 1327} 1328 1329let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations. 1330defm NAND : XForm_6r<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1331 "nand", "$rA, $rS, $rB", IntSimple, 1332 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; 1333defm AND : XForm_6r<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1334 "and", "$rA, $rS, $rB", IntSimple, 1335 [(set i32:$rA, (and i32:$rS, i32:$rB))]>; 1336defm ANDC : XForm_6r<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1337 "andc", "$rA, $rS, $rB", IntSimple, 1338 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; 1339defm OR : XForm_6r<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1340 "or", "$rA, $rS, $rB", IntSimple, 1341 [(set i32:$rA, (or i32:$rS, i32:$rB))]>; 1342defm NOR : XForm_6r<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1343 "nor", "$rA, $rS, $rB", IntSimple, 1344 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; 1345defm ORC : XForm_6r<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1346 "orc", "$rA, $rS, $rB", IntSimple, 1347 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; 1348defm EQV : XForm_6r<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1349 "eqv", "$rA, $rS, $rB", IntSimple, 1350 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; 1351defm XOR : XForm_6r<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1352 "xor", "$rA, $rS, $rB", IntSimple, 1353 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; 1354defm SLW : XForm_6r<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1355 "slw", "$rA, $rS, $rB", IntGeneral, 1356 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>; 1357defm SRW : XForm_6r<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1358 "srw", "$rA, $rS, $rB", IntGeneral, 1359 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>; 1360defm SRAW : XForm_6rc<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1361 "sraw", "$rA, $rS, $rB", IntShift, 1362 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>; 1363} 1364 1365let PPC970_Unit = 1 in { // FXU Operations. 1366let neverHasSideEffects = 1 in { 1367defm SRAWI : XForm_10rc<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH), 1368 "srawi", "$rA, $rS, $SH", IntShift, 1369 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>; 1370defm CNTLZW : XForm_11r<31, 26, (outs GPRC:$rA), (ins GPRC:$rS), 1371 "cntlzw", "$rA, $rS", IntGeneral, 1372 [(set i32:$rA, (ctlz i32:$rS))]>; 1373defm EXTSB : XForm_11r<31, 954, (outs GPRC:$rA), (ins GPRC:$rS), 1374 "extsb", "$rA, $rS", IntSimple, 1375 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>; 1376defm EXTSH : XForm_11r<31, 922, (outs GPRC:$rA), (ins GPRC:$rS), 1377 "extsh", "$rA, $rS", IntSimple, 1378 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>; 1379} 1380let isCompare = 1, neverHasSideEffects = 1 in { 1381 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 1382 "cmpw $crD, $rA, $rB", IntCompare>; 1383 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 1384 "cmplw $crD, $rA, $rB", IntCompare>; 1385} 1386} 1387let PPC970_Unit = 3 in { // FPU Operations. 1388//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 1389// "fcmpo $crD, $fA, $fB", FPCompare>; 1390let isCompare = 1, neverHasSideEffects = 1 in { 1391 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB), 1392 "fcmpu $crD, $fA, $fB", FPCompare>; 1393 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB), 1394 "fcmpu $crD, $fA, $fB", FPCompare>; 1395} 1396 1397let Uses = [RM] in { 1398 let neverHasSideEffects = 1 in { 1399 defm FCTIWZ : XForm_26r<63, 15, (outs F8RC:$frD), (ins F8RC:$frB), 1400 "fctiwz", "$frD, $frB", FPGeneral, 1401 [(set f64:$frD, (PPCfctiwz f64:$frB))]>; 1402 1403 defm FRSP : XForm_26r<63, 12, (outs F4RC:$frD), (ins F8RC:$frB), 1404 "frsp", "$frD, $frB", FPGeneral, 1405 [(set f32:$frD, (fround f64:$frB))]>; 1406 1407 // The frin -> nearbyint mapping is valid only in fast-math mode. 1408 let Interpretation64Bit = 1 in 1409 defm FRIND : XForm_26r<63, 392, (outs F8RC:$frD), (ins F8RC:$frB), 1410 "frin", "$frD, $frB", FPGeneral, 1411 [(set f64:$frD, (fnearbyint f64:$frB))]>; 1412 defm FRINS : XForm_26r<63, 392, (outs F4RC:$frD), (ins F4RC:$frB), 1413 "frin", "$frD, $frB", FPGeneral, 1414 [(set f32:$frD, (fnearbyint f32:$frB))]>; 1415 } 1416 1417 // These pseudos expand to rint but also set FE_INEXACT when the result does 1418 // not equal the argument. 1419 let usesCustomInserter = 1, Defs = [RM] in { // FIXME: Model FPSCR! 1420 def FRINDrint : Pseudo<(outs F8RC:$frD), (ins F8RC:$frB), 1421 "#FRINDrint", [(set f64:$frD, (frint f64:$frB))]>; 1422 def FRINSrint : Pseudo<(outs F4RC:$frD), (ins F4RC:$frB), 1423 "#FRINSrint", [(set f32:$frD, (frint f32:$frB))]>; 1424 } 1425 1426 let neverHasSideEffects = 1 in { 1427 let Interpretation64Bit = 1 in 1428 defm FRIPD : XForm_26r<63, 456, (outs F8RC:$frD), (ins F8RC:$frB), 1429 "frip", "$frD, $frB", FPGeneral, 1430 [(set f64:$frD, (fceil f64:$frB))]>; 1431 defm FRIPS : XForm_26r<63, 456, (outs F4RC:$frD), (ins F4RC:$frB), 1432 "frip", "$frD, $frB", FPGeneral, 1433 [(set f32:$frD, (fceil f32:$frB))]>; 1434 let Interpretation64Bit = 1 in 1435 defm FRIZD : XForm_26r<63, 424, (outs F8RC:$frD), (ins F8RC:$frB), 1436 "friz", "$frD, $frB", FPGeneral, 1437 [(set f64:$frD, (ftrunc f64:$frB))]>; 1438 defm FRIZS : XForm_26r<63, 424, (outs F4RC:$frD), (ins F4RC:$frB), 1439 "friz", "$frD, $frB", FPGeneral, 1440 [(set f32:$frD, (ftrunc f32:$frB))]>; 1441 let Interpretation64Bit = 1 in 1442 defm FRIMD : XForm_26r<63, 488, (outs F8RC:$frD), (ins F8RC:$frB), 1443 "frim", "$frD, $frB", FPGeneral, 1444 [(set f64:$frD, (ffloor f64:$frB))]>; 1445 defm FRIMS : XForm_26r<63, 488, (outs F4RC:$frD), (ins F4RC:$frB), 1446 "frim", "$frD, $frB", FPGeneral, 1447 [(set f32:$frD, (ffloor f32:$frB))]>; 1448 1449 defm FSQRT : XForm_26r<63, 22, (outs F8RC:$frD), (ins F8RC:$frB), 1450 "fsqrt", "$frD, $frB", FPSqrt, 1451 [(set f64:$frD, (fsqrt f64:$frB))]>; 1452 defm FSQRTS : XForm_26r<59, 22, (outs F4RC:$frD), (ins F4RC:$frB), 1453 "fsqrts", "$frD, $frB", FPSqrt, 1454 [(set f32:$frD, (fsqrt f32:$frB))]>; 1455 } 1456 } 1457} 1458 1459/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 1460/// often coalesced away and we don't want the dispatch group builder to think 1461/// that they will fill slots (which could cause the load of a LSU reject to 1462/// sneak into a d-group with a store). 1463let neverHasSideEffects = 1 in 1464defm FMR : XForm_26r<63, 72, (outs F4RC:$frD), (ins F4RC:$frB), 1465 "fmr", "$frD, $frB", FPGeneral, 1466 []>, // (set f32:$frD, f32:$frB) 1467 PPC970_Unit_Pseudo; 1468 1469let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations. 1470// These are artificially split into two different forms, for 4/8 byte FP. 1471defm FABSS : XForm_26r<63, 264, (outs F4RC:$frD), (ins F4RC:$frB), 1472 "fabs", "$frD, $frB", FPGeneral, 1473 [(set f32:$frD, (fabs f32:$frB))]>; 1474let Interpretation64Bit = 1 in 1475defm FABSD : XForm_26r<63, 264, (outs F8RC:$frD), (ins F8RC:$frB), 1476 "fabs", "$frD, $frB", FPGeneral, 1477 [(set f64:$frD, (fabs f64:$frB))]>; 1478defm FNABSS : XForm_26r<63, 136, (outs F4RC:$frD), (ins F4RC:$frB), 1479 "fnabs", "$frD, $frB", FPGeneral, 1480 [(set f32:$frD, (fneg (fabs f32:$frB)))]>; 1481let Interpretation64Bit = 1 in 1482defm FNABSD : XForm_26r<63, 136, (outs F8RC:$frD), (ins F8RC:$frB), 1483 "fnabs", "$frD, $frB", FPGeneral, 1484 [(set f64:$frD, (fneg (fabs f64:$frB)))]>; 1485defm FNEGS : XForm_26r<63, 40, (outs F4RC:$frD), (ins F4RC:$frB), 1486 "fneg", "$frD, $frB", FPGeneral, 1487 [(set f32:$frD, (fneg f32:$frB))]>; 1488let Interpretation64Bit = 1 in 1489defm FNEGD : XForm_26r<63, 40, (outs F8RC:$frD), (ins F8RC:$frB), 1490 "fneg", "$frD, $frB", FPGeneral, 1491 [(set f64:$frD, (fneg f64:$frB))]>; 1492 1493// Reciprocal estimates. 1494defm FRE : XForm_26r<63, 24, (outs F8RC:$frD), (ins F8RC:$frB), 1495 "fre", "$frD, $frB", FPGeneral, 1496 [(set f64:$frD, (PPCfre f64:$frB))]>; 1497defm FRES : XForm_26r<59, 24, (outs F4RC:$frD), (ins F4RC:$frB), 1498 "fres", "$frD, $frB", FPGeneral, 1499 [(set f32:$frD, (PPCfre f32:$frB))]>; 1500defm FRSQRTE : XForm_26r<63, 26, (outs F8RC:$frD), (ins F8RC:$frB), 1501 "frsqrte", "$frD, $frB", FPGeneral, 1502 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; 1503defm FRSQRTES : XForm_26r<59, 26, (outs F4RC:$frD), (ins F4RC:$frB), 1504 "frsqrtes", "$frD, $frB", FPGeneral, 1505 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; 1506} 1507 1508// XL-Form instructions. condition register logical ops. 1509// 1510let neverHasSideEffects = 1 in 1511def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA), 1512 "mcrf $BF, $BFA", BrMCR>, 1513 PPC970_DGroup_First, PPC970_Unit_CRU; 1514 1515def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD), 1516 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1517 "creqv $CRD, $CRA, $CRB", BrCR, 1518 []>; 1519 1520def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD), 1521 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1522 "cror $CRD, $CRA, $CRB", BrCR, 1523 []>; 1524 1525let isCodeGenOnly = 1 in { 1526def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins), 1527 "creqv $dst, $dst, $dst", BrCR, 1528 []>; 1529 1530def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins), 1531 "crxor $dst, $dst, $dst", BrCR, 1532 []>; 1533 1534let Defs = [CR1EQ], CRD = 6 in { 1535def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 1536 "creqv 6, 6, 6", BrCR, 1537 [(PPCcr6set)]>; 1538 1539def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 1540 "crxor 6, 6, 6", BrCR, 1541 [(PPCcr6unset)]>; 1542} 1543} 1544 1545// XFX-Form instructions. Instructions that deal with SPRs. 1546// 1547let Uses = [CTR] in { 1548def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins), 1549 "mfctr $rT", SprMFSPR>, 1550 PPC970_DGroup_First, PPC970_Unit_FXU; 1551} 1552let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { 1553def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS), 1554 "mtctr $rS", SprMTSPR>, 1555 PPC970_DGroup_First, PPC970_Unit_FXU; 1556} 1557 1558let Defs = [LR] in { 1559def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS), 1560 "mtlr $rS", SprMTSPR>, 1561 PPC970_DGroup_First, PPC970_Unit_FXU; 1562} 1563let Uses = [LR] in { 1564def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins), 1565 "mflr $rT", SprMFSPR>, 1566 PPC970_DGroup_First, PPC970_Unit_FXU; 1567} 1568 1569// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 1570// a GPR on the PPC970. As such, copies in and out have the same performance 1571// characteristics as an OR instruction. 1572def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS), 1573 "mtspr 256, $rS", IntGeneral>, 1574 PPC970_DGroup_Single, PPC970_Unit_FXU; 1575def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins), 1576 "mfspr $rT, 256", IntGeneral>, 1577 PPC970_DGroup_First, PPC970_Unit_FXU; 1578 1579let isCodeGenOnly = 1 in { 1580 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, 1581 (outs VRSAVERC:$reg), (ins GPRC:$rS), 1582 "mtspr 256, $rS", IntGeneral>, 1583 PPC970_DGroup_Single, PPC970_Unit_FXU; 1584 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), 1585 (ins VRSAVERC:$reg), 1586 "mfspr $rT, 256", IntGeneral>, 1587 PPC970_DGroup_First, PPC970_Unit_FXU; 1588} 1589 1590// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register, 1591// so we'll need to scavenge a register for it. 1592let mayStore = 1 in 1593def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F), 1594 "#SPILL_VRSAVE", []>; 1595 1596// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously 1597// spilled), so we'll need to scavenge a register for it. 1598let mayLoad = 1 in 1599def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F), 1600 "#RESTORE_VRSAVE", []>; 1601 1602let neverHasSideEffects = 1 in { 1603def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS), 1604 "mtcrf $FXM, $rS", BrMCRX>, 1605 PPC970_MicroCode, PPC970_Unit_CRU; 1606 1607// This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters; 1608// declaring that here gives the local register allocator problems with this: 1609// vreg = MCRF CR0 1610// MFCR <kill of whatever preg got assigned to vreg> 1611// while not declaring it breaks DeadMachineInstructionElimination. 1612// As it turns out, in all cases where we currently use this, 1613// we're only interested in one subregister of it. Represent this in the 1614// instruction to keep the register allocator from becoming confused. 1615// 1616// FIXME: Make this a real Pseudo instruction when the JIT switches to MC. 1617let isCodeGenOnly = 1 in 1618def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1619 "#MFCRpseud", SprMFCR>, 1620 PPC970_MicroCode, PPC970_Unit_CRU; 1621 1622def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1623 "mfocrf $rT, $FXM", SprMFCR>, 1624 PPC970_DGroup_First, PPC970_Unit_CRU; 1625} // neverHasSideEffects = 1 1626 1627let neverHasSideEffects = 1 in 1628def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), 1629 "mfcr $rT", SprMFCR>, 1630 PPC970_MicroCode, PPC970_Unit_CRU; 1631 1632// Pseudo instruction to perform FADD in round-to-zero mode. 1633let usesCustomInserter = 1, Uses = [RM] in { 1634 def FADDrtz: Pseudo<(outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "", 1635 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>; 1636} 1637 1638// The above pseudo gets expanded to make use of the following instructions 1639// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 1640let Uses = [RM], Defs = [RM] in { 1641 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 1642 "mtfsb0 $FM", IntMTFSB0, []>, 1643 PPC970_DGroup_Single, PPC970_Unit_FPU; 1644 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 1645 "mtfsb1 $FM", IntMTFSB0, []>, 1646 PPC970_DGroup_Single, PPC970_Unit_FPU; 1647 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, F8RC:$rT), 1648 "mtfsf $FM, $rT", IntMTFSB0, []>, 1649 PPC970_DGroup_Single, PPC970_Unit_FPU; 1650} 1651let Uses = [RM] in { 1652 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins), 1653 "mffs $rT", IntMFFS, 1654 [(set f64:$rT, (PPCmffs))]>, 1655 PPC970_DGroup_Single, PPC970_Unit_FPU; 1656} 1657 1658 1659let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations. 1660// XO-Form instructions. Arithmetic instructions that can set overflow bit 1661// 1662defm ADD4 : XOForm_1r<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1663 "add", "$rT, $rA, $rB", IntSimple, 1664 [(set i32:$rT, (add i32:$rA, i32:$rB))]>; 1665defm ADDC : XOForm_1rc<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1666 "addc", "$rT, $rA, $rB", IntGeneral, 1667 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, 1668 PPC970_DGroup_Cracked; 1669defm DIVW : XOForm_1r<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1670 "divw", "$rT, $rA, $rB", IntDivW, 1671 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>, 1672 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1673defm DIVWU : XOForm_1r<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1674 "divwu", "$rT, $rA, $rB", IntDivW, 1675 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>, 1676 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1677defm MULHW : XOForm_1r<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1678 "mulhw", "$rT, $rA, $rB", IntMulHW, 1679 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; 1680defm MULHWU : XOForm_1r<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1681 "mulhwu", "$rT, $rA, $rB", IntMulHWU, 1682 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; 1683defm MULLW : XOForm_1r<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1684 "mullw", "$rT, $rA, $rB", IntMulHW, 1685 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; 1686defm SUBF : XOForm_1r<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1687 "subf", "$rT, $rA, $rB", IntGeneral, 1688 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; 1689defm SUBFC : XOForm_1rc<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1690 "subfc", "$rT, $rA, $rB", IntGeneral, 1691 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, 1692 PPC970_DGroup_Cracked; 1693defm NEG : XOForm_3r<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1694 "neg", "$rT, $rA", IntSimple, 1695 [(set i32:$rT, (ineg i32:$rA))]>; 1696let Uses = [CARRY] in { 1697defm ADDE : XOForm_1rc<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1698 "adde", "$rT, $rA, $rB", IntGeneral, 1699 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; 1700defm ADDME : XOForm_3rc<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1701 "addme", "$rT, $rA", IntGeneral, 1702 [(set i32:$rT, (adde i32:$rA, -1))]>; 1703defm ADDZE : XOForm_3rc<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1704 "addze", "$rT, $rA", IntGeneral, 1705 [(set i32:$rT, (adde i32:$rA, 0))]>; 1706defm SUBFE : XOForm_1rc<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1707 "subfe", "$rT, $rA, $rB", IntGeneral, 1708 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; 1709defm SUBFME : XOForm_3rc<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1710 "subfme", "$rT, $rA", IntGeneral, 1711 [(set i32:$rT, (sube -1, i32:$rA))]>; 1712defm SUBFZE : XOForm_3rc<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1713 "subfze", "$rT, $rA", IntGeneral, 1714 [(set i32:$rT, (sube 0, i32:$rA))]>; 1715} 1716} 1717 1718// A-Form instructions. Most of the instructions executed in the FPU are of 1719// this type. 1720// 1721let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations. 1722let Uses = [RM] in { 1723 defm FMADD : AForm_1r<63, 29, 1724 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1725 "fmadd", "$FRT, $FRA, $FRC, $FRB", FPFused, 1726 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 1727 defm FMADDS : AForm_1r<59, 29, 1728 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1729 "fmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral, 1730 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 1731 defm FMSUB : AForm_1r<63, 28, 1732 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1733 "fmsub", "$FRT, $FRA, $FRC, $FRB", FPFused, 1734 [(set f64:$FRT, 1735 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 1736 defm FMSUBS : AForm_1r<59, 28, 1737 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1738 "fmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral, 1739 [(set f32:$FRT, 1740 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 1741 defm FNMADD : AForm_1r<63, 31, 1742 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1743 "fnmadd", "$FRT, $FRA, $FRC, $FRB", FPFused, 1744 [(set f64:$FRT, 1745 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 1746 defm FNMADDS : AForm_1r<59, 31, 1747 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1748 "fnmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral, 1749 [(set f32:$FRT, 1750 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 1751 defm FNMSUB : AForm_1r<63, 30, 1752 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1753 "fnmsub", "$FRT, $FRA, $FRC, $FRB", FPFused, 1754 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC, 1755 (fneg f64:$FRB))))]>; 1756 defm FNMSUBS : AForm_1r<59, 30, 1757 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1758 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral, 1759 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC, 1760 (fneg f32:$FRB))))]>; 1761} 1762// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 1763// having 4 of these, force the comparison to always be an 8-byte double (code 1764// should use an FMRSD if the input comparison value really wants to be a float) 1765// and 4/8 byte forms for the result and operand type.. 1766let Interpretation64Bit = 1 in 1767defm FSELD : AForm_1r<63, 23, 1768 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1769 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral, 1770 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 1771defm FSELS : AForm_1r<63, 23, 1772 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1773 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral, 1774 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 1775let Uses = [RM] in { 1776 defm FADD : AForm_2r<63, 21, 1777 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1778 "fadd", "$FRT, $FRA, $FRB", FPAddSub, 1779 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>; 1780 defm FADDS : AForm_2r<59, 21, 1781 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1782 "fadds", "$FRT, $FRA, $FRB", FPGeneral, 1783 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>; 1784 defm FDIV : AForm_2r<63, 18, 1785 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1786 "fdiv", "$FRT, $FRA, $FRB", FPDivD, 1787 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>; 1788 defm FDIVS : AForm_2r<59, 18, 1789 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1790 "fdivs", "$FRT, $FRA, $FRB", FPDivS, 1791 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>; 1792 defm FMUL : AForm_3r<63, 25, 1793 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC), 1794 "fmul", "$FRT, $FRA, $FRC", FPFused, 1795 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>; 1796 defm FMULS : AForm_3r<59, 25, 1797 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC), 1798 "fmuls", "$FRT, $FRA, $FRC", FPGeneral, 1799 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>; 1800 defm FSUB : AForm_2r<63, 20, 1801 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1802 "fsub", "$FRT, $FRA, $FRB", FPAddSub, 1803 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>; 1804 defm FSUBS : AForm_2r<59, 20, 1805 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1806 "fsubs", "$FRT, $FRA, $FRB", FPGeneral, 1807 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>; 1808 } 1809} 1810 1811let neverHasSideEffects = 1 in { 1812let PPC970_Unit = 1 in { // FXU Operations. 1813 let isSelect = 1 in 1814 def ISEL : AForm_4<31, 15, 1815 (outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB, CRBITRC:$cond), 1816 "isel $rT, $rA, $rB, $cond", IntGeneral, 1817 []>; 1818} 1819 1820let PPC970_Unit = 1 in { // FXU Operations. 1821// M-Form instructions. rotate and mask instructions. 1822// 1823let isCommutable = 1 in { 1824// RLWIMI can be commuted if the rotate amount is zero. 1825defm RLWIMI : MForm_2r<20, (outs GPRC:$rA), 1826 (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 1827 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", IntRotate, 1828 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 1829 NoEncode<"$rSi">; 1830} 1831let BaseName = "rlwinm" in { 1832def RLWINM : MForm_2<21, 1833 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1834 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 1835 []>, RecFormRel; 1836let Defs = [CR0] in 1837def RLWINMo : MForm_2<21, 1838 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1839 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 1840 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked; 1841} 1842defm RLWNM : MForm_2r<23, (outs GPRC:$rA), 1843 (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 1844 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IntGeneral, 1845 []>; 1846} 1847} // neverHasSideEffects = 1 1848 1849//===----------------------------------------------------------------------===// 1850// PowerPC Instruction Patterns 1851// 1852 1853// Arbitrary immediate support. Implement in terms of LIS/ORI. 1854def : Pat<(i32 imm:$imm), 1855 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1856 1857// Implement the 'not' operation with the NOR instruction. 1858def NOT : Pat<(not i32:$in), 1859 (NOR $in, $in)>; 1860 1861// ADD an arbitrary immediate. 1862def : Pat<(add i32:$in, imm:$imm), 1863 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1864// OR an arbitrary immediate. 1865def : Pat<(or i32:$in, imm:$imm), 1866 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1867// XOR an arbitrary immediate. 1868def : Pat<(xor i32:$in, imm:$imm), 1869 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1870// SUBFIC 1871def : Pat<(sub immSExt16:$imm, i32:$in), 1872 (SUBFIC $in, imm:$imm)>; 1873 1874// SHL/SRL 1875def : Pat<(shl i32:$in, (i32 imm:$imm)), 1876 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 1877def : Pat<(srl i32:$in, (i32 imm:$imm)), 1878 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 1879 1880// ROTL 1881def : Pat<(rotl i32:$in, i32:$sh), 1882 (RLWNM $in, $sh, 0, 31)>; 1883def : Pat<(rotl i32:$in, (i32 imm:$imm)), 1884 (RLWINM $in, imm:$imm, 0, 31)>; 1885 1886// RLWNM 1887def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 1888 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 1889 1890// Calls 1891def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 1892 (BL tglobaladdr:$dst)>; 1893def : Pat<(PPCcall (i32 texternalsym:$dst)), 1894 (BL texternalsym:$dst)>; 1895 1896 1897def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 1898 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 1899 1900def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 1901 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 1902 1903def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 1904 (TCRETURNri CTRRC:$dst, imm:$imm)>; 1905 1906 1907 1908// Hi and Lo for Darwin Global Addresses. 1909def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1910def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1911def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1912def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1913def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1914def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1915def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 1916def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 1917def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 1918 (ADDIS $in, tglobaltlsaddr:$g)>; 1919def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 1920 (ADDI $in, tglobaltlsaddr:$g)>; 1921def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 1922 (ADDIS $in, tglobaladdr:$g)>; 1923def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 1924 (ADDIS $in, tconstpool:$g)>; 1925def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 1926 (ADDIS $in, tjumptable:$g)>; 1927def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 1928 (ADDIS $in, tblockaddress:$g)>; 1929 1930// Standard shifts. These are represented separately from the real shifts above 1931// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1932// amounts. 1933def : Pat<(sra i32:$rS, i32:$rB), 1934 (SRAW $rS, $rB)>; 1935def : Pat<(srl i32:$rS, i32:$rB), 1936 (SRW $rS, $rB)>; 1937def : Pat<(shl i32:$rS, i32:$rB), 1938 (SLW $rS, $rB)>; 1939 1940def : Pat<(zextloadi1 iaddr:$src), 1941 (LBZ iaddr:$src)>; 1942def : Pat<(zextloadi1 xaddr:$src), 1943 (LBZX xaddr:$src)>; 1944def : Pat<(extloadi1 iaddr:$src), 1945 (LBZ iaddr:$src)>; 1946def : Pat<(extloadi1 xaddr:$src), 1947 (LBZX xaddr:$src)>; 1948def : Pat<(extloadi8 iaddr:$src), 1949 (LBZ iaddr:$src)>; 1950def : Pat<(extloadi8 xaddr:$src), 1951 (LBZX xaddr:$src)>; 1952def : Pat<(extloadi16 iaddr:$src), 1953 (LHZ iaddr:$src)>; 1954def : Pat<(extloadi16 xaddr:$src), 1955 (LHZX xaddr:$src)>; 1956def : Pat<(f64 (extloadf32 iaddr:$src)), 1957 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 1958def : Pat<(f64 (extloadf32 xaddr:$src)), 1959 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 1960 1961def : Pat<(f64 (fextend f32:$src)), 1962 (COPY_TO_REGCLASS $src, F8RC)>; 1963 1964// Memory barriers 1965def : Pat<(membarrier (i32 imm /*ll*/), 1966 (i32 imm /*ls*/), 1967 (i32 imm /*sl*/), 1968 (i32 imm /*ss*/), 1969 (i32 imm /*device*/)), 1970 (SYNC)>; 1971 1972def : Pat<(atomic_fence (imm), (imm)), (SYNC)>; 1973 1974// Additional FNMSUB patterns: -a*c + b == -(a*c - b) 1975def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B), 1976 (FNMSUB $A, $C, $B)>; 1977def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B), 1978 (FNMSUB $A, $C, $B)>; 1979def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B), 1980 (FNMSUBS $A, $C, $B)>; 1981def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B), 1982 (FNMSUBS $A, $C, $B)>; 1983 1984include "PPCInstrAltivec.td" 1985include "PPCInstr64Bit.td" 1986