PPCInstrInfo.td revision 0403862158a5a908b868b0b64b7725b39919a506
1//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl 24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32> 25]>; 26def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 27 28def SDT_PPCvperm : SDTypeProfile<1, 3, [ 29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 30]>; 31 32def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 34]>; 35 36def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 37 SDTCisVT<1, i32>, SDTCisVT<2, OtherVT> 38]>; 39 40def SDT_PPClbrx : SDTypeProfile<1, 3, [ 41 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> 42]>; 43def SDT_PPCstbrx : SDTypeProfile<0, 4, [ 44 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> 45]>; 46 47//===----------------------------------------------------------------------===// 48// PowerPC specific DAG Nodes. 49// 50 51def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 52def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 53def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 54def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>; 55 56def PPCfsel : SDNode<"PPCISD::FSEL", 57 // Type constraint for fsel. 58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 59 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 60 61def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 62def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 63def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 64def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 65 66def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 67 68// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 69// amounts. These nodes are generated by the multi-precision shift code. 70def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>; 71def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>; 72def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>; 73 74def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 75def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq, 79 [SDNPHasChain, SDNPOutFlag]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq, 81 [SDNPHasChain, SDNPOutFlag]>; 82 83def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 84def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 85 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 86def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 87 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 88def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet, 89 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 90 91def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet, 92 [SDNPHasChain, SDNPOptInFlag]>; 93 94def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 95def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>; 96 97def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 98 [SDNPHasChain, SDNPOptInFlag]>; 99 100def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>; 101def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>; 102 103//===----------------------------------------------------------------------===// 104// PowerPC specific transformation functions and pattern fragments. 105// 106 107def SHL32 : SDNodeXForm<imm, [{ 108 // Transformation function: 31 - imm 109 return getI32Imm(31 - N->getValue()); 110}]>; 111 112def SRL32 : SDNodeXForm<imm, [{ 113 // Transformation function: 32 - imm 114 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0); 115}]>; 116 117def LO16 : SDNodeXForm<imm, [{ 118 // Transformation function: get the low 16 bits. 119 return getI32Imm((unsigned short)N->getValue()); 120}]>; 121 122def HI16 : SDNodeXForm<imm, [{ 123 // Transformation function: shift the immediate value down into the low bits. 124 return getI32Imm((unsigned)N->getValue() >> 16); 125}]>; 126 127def HA16 : SDNodeXForm<imm, [{ 128 // Transformation function: shift the immediate value down into the low bits. 129 signed int Val = N->getValue(); 130 return getI32Imm((Val - (signed short)Val) >> 16); 131}]>; 132def MB : SDNodeXForm<imm, [{ 133 // Transformation function: get the start bit of a mask 134 unsigned mb, me; 135 (void)isRunOfOnes((unsigned)N->getValue(), mb, me); 136 return getI32Imm(mb); 137}]>; 138 139def ME : SDNodeXForm<imm, [{ 140 // Transformation function: get the end bit of a mask 141 unsigned mb, me; 142 (void)isRunOfOnes((unsigned)N->getValue(), mb, me); 143 return getI32Imm(me); 144}]>; 145def maskimm32 : PatLeaf<(imm), [{ 146 // maskImm predicate - True if immediate is a run of ones. 147 unsigned mb, me; 148 if (N->getValueType(0) == MVT::i32) 149 return isRunOfOnes((unsigned)N->getValue(), mb, me); 150 else 151 return false; 152}]>; 153 154def immSExt16 : PatLeaf<(imm), [{ 155 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 156 // field. Used by instructions like 'addi'. 157 if (N->getValueType(0) == MVT::i32) 158 return (int32_t)N->getValue() == (short)N->getValue(); 159 else 160 return (int64_t)N->getValue() == (short)N->getValue(); 161}]>; 162def immZExt16 : PatLeaf<(imm), [{ 163 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 164 // field. Used by instructions like 'ori'. 165 return (uint64_t)N->getValue() == (unsigned short)N->getValue(); 166}], LO16>; 167 168// imm16Shifted* - These match immediates where the low 16-bits are zero. There 169// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 170// identical in 32-bit mode, but in 64-bit mode, they return true if the 171// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 172// clear). 173def imm16ShiftedZExt : PatLeaf<(imm), [{ 174 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 175 // immediate are set. Used by instructions like 'xoris'. 176 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0; 177}], HI16>; 178 179def imm16ShiftedSExt : PatLeaf<(imm), [{ 180 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 181 // immediate are set. Used by instructions like 'addis'. Identical to 182 // imm16ShiftedZExt in 32-bit mode. 183 if (N->getValue() & 0xFFFF) return false; 184 if (N->getValueType(0) == MVT::i32) 185 return true; 186 // For 64-bit, make sure it is sext right. 187 return N->getValue() == (uint64_t)(int)N->getValue(); 188}], HI16>; 189 190 191//===----------------------------------------------------------------------===// 192// PowerPC Flag Definitions. 193 194class isPPC64 { bit PPC64 = 1; } 195class isDOT { 196 list<Register> Defs = [CR0]; 197 bit RC = 1; 198} 199 200class RegConstraint<string C> { 201 string Constraints = C; 202} 203class NoEncode<string E> { 204 string DisableEncoding = E; 205} 206 207 208//===----------------------------------------------------------------------===// 209// PowerPC Operand Definitions. 210 211def s5imm : Operand<i32> { 212 let PrintMethod = "printS5ImmOperand"; 213} 214def u5imm : Operand<i32> { 215 let PrintMethod = "printU5ImmOperand"; 216} 217def u6imm : Operand<i32> { 218 let PrintMethod = "printU6ImmOperand"; 219} 220def s16imm : Operand<i32> { 221 let PrintMethod = "printS16ImmOperand"; 222} 223def u16imm : Operand<i32> { 224 let PrintMethod = "printU16ImmOperand"; 225} 226def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 227 let PrintMethod = "printS16X4ImmOperand"; 228} 229def target : Operand<OtherVT> { 230 let PrintMethod = "printBranchOperand"; 231} 232def calltarget : Operand<iPTR> { 233 let PrintMethod = "printCallOperand"; 234} 235def aaddr : Operand<iPTR> { 236 let PrintMethod = "printAbsAddrOperand"; 237} 238def piclabel: Operand<iPTR> { 239 let PrintMethod = "printPICLabel"; 240} 241def symbolHi: Operand<i32> { 242 let PrintMethod = "printSymbolHi"; 243} 244def symbolLo: Operand<i32> { 245 let PrintMethod = "printSymbolLo"; 246} 247def crbitm: Operand<i8> { 248 let PrintMethod = "printcrbitm"; 249} 250// Address operands 251def memri : Operand<iPTR> { 252 let PrintMethod = "printMemRegImm"; 253 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 254} 255def memrr : Operand<iPTR> { 256 let PrintMethod = "printMemRegReg"; 257 let MIOperandInfo = (ops ptr_rc, ptr_rc); 258} 259def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 260 let PrintMethod = "printMemRegImmShifted"; 261 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 262} 263 264// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg 265// that doesn't matter. 266def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 20), CR0)> { 267 let PrintMethod = "printPredicateOperand"; 268} 269 270// Define PowerPC specific addressing mode. 271def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 272def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 273def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 274def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 275 276/// This is just the offset part of iaddr, used for preinc. 277def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 278 279//===----------------------------------------------------------------------===// 280// PowerPC Instruction Predicate Definitions. 281def FPContractions : Predicate<"!NoExcessFPPrecision">; 282 283 284//===----------------------------------------------------------------------===// 285// PowerPC Instruction Definitions. 286 287// Pseudo-instructions: 288 289let hasCtrlDep = 1 in { 290def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), 291 "${:comment} ADJCALLSTACKDOWN", 292 [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>; 293def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), 294 "${:comment} ADJCALLSTACKUP", 295 [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>; 296 297def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS), 298 "UPDATE_VRSAVE $rD, $rS", []>; 299} 300def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD),"${:comment}IMPLICIT_DEF_GPRC $rD", 301 [(set GPRC:$rD, (undef))]>; 302def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "${:comment} IMPLICIT_DEF_F8 $rD", 303 [(set F8RC:$rD, (undef))]>; 304def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "${:comment} IMPLICIT_DEF_F4 $rD", 305 [(set F4RC:$rD, (undef))]>; 306 307// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 308// scheduler into a branch sequence. 309let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler. 310 PPC970_Single = 1 in { 311 def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F, 312 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 313 []>; 314 def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F, 315 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 316 []>; 317 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F, 318 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 319 []>; 320 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F, 321 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 322 []>; 323 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F, 324 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 325 []>; 326} 327 328let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in { 329 let isReturn = 1 in 330 def BLR : XLForm_2_br<19, 16, 0, 331 (ops pred:$p), 332 "b${p:cc}lr ${p:reg}", BrB, 333 [(retflag)]>; 334 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>; 335} 336 337 338 339let Defs = [LR] in 340 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>, 341 PPC970_Unit_BRU; 342 343let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, 344 noResults = 1, PPC970_Unit = 7 in { 345 // COND_BRANCH is formed before branch selection, it is turned into Bcc below. 346 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst), 347 "${:comment} COND_BRANCH $crS, $opc, $dst", 348 [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>; 349 let isBarrier = 1 in { 350 def B : IForm<18, 0, 0, (ops target:$dst), 351 "b $dst", BrB, 352 [(br bb:$dst)]>; 353 } 354 355 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block), 356 "blt $crS, $block", BrB>; 357 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block), 358 "ble $crS, $block", BrB>; 359 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block), 360 "beq $crS, $block", BrB>; 361 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block), 362 "bge $crS, $block", BrB>; 363 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block), 364 "bgt $crS, $block", BrB>; 365 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block), 366 "bne $crS, $block", BrB>; 367 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block), 368 "bun $crS, $block", BrB>; 369 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block), 370 "bnu $crS, $block", BrB>; 371} 372 373let isCall = 1, noResults = 1, PPC970_Unit = 7, 374 // All calls clobber the non-callee saved registers... 375 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 376 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 377 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 378 LR,CTR, 379 CR0,CR1,CR5,CR6,CR7] in { 380 // Convenient aliases for call instructions 381 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops), 382 "bl $func", BrB, []>; // See Pat patterns below. 383 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), 384 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>; 385 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB, 386 [(PPCbctrl)]>; 387} 388 389// DCB* instructions. 390def DCBA : DCB_Form<758, 0, (ops memrr:$dst), 391 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 392 PPC970_DGroup_Single; 393def DCBF : DCB_Form<86, 0, (ops memrr:$dst), 394 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 395 PPC970_DGroup_Single; 396def DCBI : DCB_Form<470, 0, (ops memrr:$dst), 397 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 398 PPC970_DGroup_Single; 399def DCBST : DCB_Form<54, 0, (ops memrr:$dst), 400 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 401 PPC970_DGroup_Single; 402def DCBT : DCB_Form<278, 0, (ops memrr:$dst), 403 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 404 PPC970_DGroup_Single; 405def DCBTST : DCB_Form<246, 0, (ops memrr:$dst), 406 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 407 PPC970_DGroup_Single; 408def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst), 409 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 410 PPC970_DGroup_Single; 411def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst), 412 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 413 PPC970_DGroup_Single; 414 415//===----------------------------------------------------------------------===// 416// PPC32 Load Instructions. 417// 418 419// Unindexed (r+i) Loads. 420let isLoad = 1, PPC970_Unit = 2 in { 421def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src), 422 "lbz $rD, $src", LdStGeneral, 423 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 424def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src), 425 "lha $rD, $src", LdStLHA, 426 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, 427 PPC970_DGroup_Cracked; 428def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src), 429 "lhz $rD, $src", LdStGeneral, 430 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; 431def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src), 432 "lwz $rD, $src", LdStGeneral, 433 [(set GPRC:$rD, (load iaddr:$src))]>; 434 435def LFS : DForm_1<48, (ops F4RC:$rD, memri:$src), 436 "lfs $rD, $src", LdStLFDU, 437 [(set F4RC:$rD, (load iaddr:$src))]>; 438def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src), 439 "lfd $rD, $src", LdStLFD, 440 [(set F8RC:$rD, (load iaddr:$src))]>; 441 442 443// Unindexed (r+i) Loads with Update (preinc). 444def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), 445 "lbzu $rD, $addr", LdStGeneral, 446 []>, RegConstraint<"$addr.reg = $ea_result">, 447 NoEncode<"$ea_result">; 448 449def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), 450 "lhau $rD, $addr", LdStGeneral, 451 []>, RegConstraint<"$addr.reg = $ea_result">, 452 NoEncode<"$ea_result">; 453 454def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), 455 "lhzu $rD, $addr", LdStGeneral, 456 []>, RegConstraint<"$addr.reg = $ea_result">, 457 NoEncode<"$ea_result">; 458 459def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), 460 "lwzu $rD, $addr", LdStGeneral, 461 []>, RegConstraint<"$addr.reg = $ea_result">, 462 NoEncode<"$ea_result">; 463 464def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$ea_result, memri:$addr), 465 "lfs $rD, $addr", LdStLFDU, 466 []>, RegConstraint<"$addr.reg = $ea_result">, 467 NoEncode<"$ea_result">; 468 469def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$ea_result, memri:$addr), 470 "lfd $rD, $addr", LdStLFD, 471 []>, RegConstraint<"$addr.reg = $ea_result">, 472 NoEncode<"$ea_result">; 473} 474 475// Indexed (r+r) Loads. 476// 477let isLoad = 1, PPC970_Unit = 2 in { 478def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src), 479 "lbzx $rD, $src", LdStGeneral, 480 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; 481def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src), 482 "lhax $rD, $src", LdStLHA, 483 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, 484 PPC970_DGroup_Cracked; 485def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src), 486 "lhzx $rD, $src", LdStGeneral, 487 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; 488def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src), 489 "lwzx $rD, $src", LdStGeneral, 490 [(set GPRC:$rD, (load xaddr:$src))]>; 491 492 493def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src), 494 "lhbrx $rD, $src", LdStGeneral, 495 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>; 496def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src), 497 "lwbrx $rD, $src", LdStGeneral, 498 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>; 499 500def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src), 501 "lfsx $frD, $src", LdStLFDU, 502 [(set F4RC:$frD, (load xaddr:$src))]>; 503def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src), 504 "lfdx $frD, $src", LdStLFDU, 505 [(set F8RC:$frD, (load xaddr:$src))]>; 506} 507 508//===----------------------------------------------------------------------===// 509// PPC32 Store Instructions. 510// 511 512// Unindexed (r+i) Stores. 513let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 514def STB : DForm_1<38, (ops GPRC:$rS, memri:$src), 515 "stb $rS, $src", LdStGeneral, 516 [(truncstorei8 GPRC:$rS, iaddr:$src)]>; 517def STH : DForm_1<44, (ops GPRC:$rS, memri:$src), 518 "sth $rS, $src", LdStGeneral, 519 [(truncstorei16 GPRC:$rS, iaddr:$src)]>; 520def STW : DForm_1<36, (ops GPRC:$rS, memri:$src), 521 "stw $rS, $src", LdStGeneral, 522 [(store GPRC:$rS, iaddr:$src)]>; 523def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst), 524 "stfs $rS, $dst", LdStUX, 525 [(store F4RC:$rS, iaddr:$dst)]>; 526def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst), 527 "stfd $rS, $dst", LdStUX, 528 [(store F8RC:$rS, iaddr:$dst)]>; 529} 530 531// Unindexed (r+i) Stores with Update (preinc). 532let isStore = 1, PPC970_Unit = 2 in { 533def STBU : DForm_1<39, (ops ptr_rc:$ea_res, GPRC:$rS, 534 symbolLo:$ptroff, ptr_rc:$ptrreg), 535 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 536 [(set ptr_rc:$ea_res, 537 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, 538 iaddroff:$ptroff))]>, 539 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 540def STHU : DForm_1<45, (ops ptr_rc:$ea_res, GPRC:$rS, 541 symbolLo:$ptroff, ptr_rc:$ptrreg), 542 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 543 [(set ptr_rc:$ea_res, 544 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, 545 iaddroff:$ptroff))]>, 546 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 547def STWU : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS, 548 symbolLo:$ptroff, ptr_rc:$ptrreg), 549 "stwu $rS, $ptroff($ptrreg)", LdStGeneral, 550 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg, 551 iaddroff:$ptroff))]>, 552 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 553def STFSU : DForm_1<37, (ops ptr_rc:$ea_res, F4RC:$rS, 554 symbolLo:$ptroff, ptr_rc:$ptrreg), 555 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral, 556 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg, 557 iaddroff:$ptroff))]>, 558 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 559def STFDU : DForm_1<37, (ops ptr_rc:$ea_res, F8RC:$rS, 560 symbolLo:$ptroff, ptr_rc:$ptrreg), 561 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral, 562 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg, 563 iaddroff:$ptroff))]>, 564 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 565} 566 567 568// Indexed (r+r) Stores. 569// 570let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 571def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst), 572 "stbx $rS, $dst", LdStGeneral, 573 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, 574 PPC970_DGroup_Cracked; 575def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst), 576 "sthx $rS, $dst", LdStGeneral, 577 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, 578 PPC970_DGroup_Cracked; 579def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst), 580 "stwx $rS, $dst", LdStGeneral, 581 [(store GPRC:$rS, xaddr:$dst)]>, 582 PPC970_DGroup_Cracked; 583def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 584 "stwux $rS, $rA, $rB", LdStGeneral, 585 []>; 586def STHBRX: XForm_8<31, 918, (ops GPRC:$rS, memrr:$dst), 587 "sthbrx $rS, $dst", LdStGeneral, 588 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>, 589 PPC970_DGroup_Cracked; 590def STWBRX: XForm_8<31, 662, (ops GPRC:$rS, memrr:$dst), 591 "stwbrx $rS, $dst", LdStGeneral, 592 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>, 593 PPC970_DGroup_Cracked; 594 595def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst), 596 "stfiwx $frS, $dst", LdStUX, 597 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 598def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst), 599 "stfsx $frS, $dst", LdStUX, 600 [(store F4RC:$frS, xaddr:$dst)]>; 601def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst), 602 "stfdx $frS, $dst", LdStUX, 603 [(store F8RC:$frS, xaddr:$dst)]>; 604} 605 606 607//===----------------------------------------------------------------------===// 608// PPC32 Arithmetic Instructions. 609// 610 611let PPC970_Unit = 1 in { // FXU Operations. 612def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 613 "addi $rD, $rA, $imm", IntGeneral, 614 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 615def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 616 "addic $rD, $rA, $imm", IntGeneral, 617 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 618 PPC970_DGroup_Cracked; 619def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 620 "addic. $rD, $rA, $imm", IntGeneral, 621 []>; 622def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm), 623 "addis $rD, $rA, $imm", IntGeneral, 624 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; 625def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym), 626 "la $rD, $sym($rA)", IntGeneral, 627 [(set GPRC:$rD, (add GPRC:$rA, 628 (PPClo tglobaladdr:$sym, 0)))]>; 629def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 630 "mulli $rD, $rA, $imm", IntMulLI, 631 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 632def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 633 "subfic $rD, $rA, $imm", IntGeneral, 634 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 635def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm), 636 "li $rD, $imm", IntGeneral, 637 [(set GPRC:$rD, immSExt16:$imm)]>; 638def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm), 639 "lis $rD, $imm", IntGeneral, 640 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; 641} 642 643let PPC970_Unit = 1 in { // FXU Operations. 644def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 645 "andi. $dst, $src1, $src2", IntGeneral, 646 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 647 isDOT; 648def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 649 "andis. $dst, $src1, $src2", IntGeneral, 650 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, 651 isDOT; 652def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 653 "ori $dst, $src1, $src2", IntGeneral, 654 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 655def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 656 "oris $dst, $src1, $src2", IntGeneral, 657 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; 658def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 659 "xori $dst, $src1, $src2", IntGeneral, 660 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 661def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 662 "xoris $dst, $src1, $src2", IntGeneral, 663 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; 664def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral, 665 []>; 666def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 667 "cmpwi $crD, $rA, $imm", IntCompare>; 668def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 669 "cmplwi $dst, $src1, $src2", IntCompare>; 670} 671 672 673let PPC970_Unit = 1 in { // FXU Operations. 674def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 675 "nand $rA, $rS, $rB", IntGeneral, 676 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 677def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 678 "and $rA, $rS, $rB", IntGeneral, 679 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 680def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 681 "andc $rA, $rS, $rB", IntGeneral, 682 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 683def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 684 "or $rA, $rS, $rB", IntGeneral, 685 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 686def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 687 "nor $rA, $rS, $rB", IntGeneral, 688 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 689def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 690 "orc $rA, $rS, $rB", IntGeneral, 691 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 692def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 693 "eqv $rA, $rS, $rB", IntGeneral, 694 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 695def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 696 "xor $rA, $rS, $rB", IntGeneral, 697 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 698def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 699 "slw $rA, $rS, $rB", IntGeneral, 700 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 701def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 702 "srw $rA, $rS, $rB", IntGeneral, 703 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 704def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 705 "sraw $rA, $rS, $rB", IntShift, 706 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 707} 708 709let PPC970_Unit = 1 in { // FXU Operations. 710def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), 711 "srawi $rA, $rS, $SH", IntShift, 712 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 713def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS), 714 "cntlzw $rA, $rS", IntGeneral, 715 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 716def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS), 717 "extsb $rA, $rS", IntGeneral, 718 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 719def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS), 720 "extsh $rA, $rS", IntGeneral, 721 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 722 723def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 724 "cmpw $crD, $rA, $rB", IntCompare>; 725def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 726 "cmplw $crD, $rA, $rB", IntCompare>; 727} 728let PPC970_Unit = 3 in { // FPU Operations. 729//def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB), 730// "fcmpo $crD, $fA, $fB", FPCompare>; 731def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB), 732 "fcmpu $crD, $fA, $fB", FPCompare>; 733def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB), 734 "fcmpu $crD, $fA, $fB", FPCompare>; 735 736def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB), 737 "fctiwz $frD, $frB", FPGeneral, 738 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 739def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB), 740 "frsp $frD, $frB", FPGeneral, 741 [(set F4RC:$frD, (fround F8RC:$frB))]>; 742def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB), 743 "fsqrt $frD, $frB", FPSqrt, 744 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 745def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB), 746 "fsqrts $frD, $frB", FPSqrt, 747 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 748} 749 750/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending. 751/// 752/// Note that these are defined as pseudo-ops on the PPC970 because they are 753/// often coalesced away and we don't want the dispatch group builder to think 754/// that they will fill slots (which could cause the load of a LSU reject to 755/// sneak into a d-group with a store). 756def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB), 757 "fmr $frD, $frB", FPGeneral, 758 []>, // (set F4RC:$frD, F4RC:$frB) 759 PPC970_Unit_Pseudo; 760def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB), 761 "fmr $frD, $frB", FPGeneral, 762 []>, // (set F8RC:$frD, F8RC:$frB) 763 PPC970_Unit_Pseudo; 764def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB), 765 "fmr $frD, $frB", FPGeneral, 766 [(set F8RC:$frD, (fextend F4RC:$frB))]>, 767 PPC970_Unit_Pseudo; 768 769let PPC970_Unit = 3 in { // FPU Operations. 770// These are artificially split into two different forms, for 4/8 byte FP. 771def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB), 772 "fabs $frD, $frB", FPGeneral, 773 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 774def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB), 775 "fabs $frD, $frB", FPGeneral, 776 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 777def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB), 778 "fnabs $frD, $frB", FPGeneral, 779 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 780def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB), 781 "fnabs $frD, $frB", FPGeneral, 782 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 783def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB), 784 "fneg $frD, $frB", FPGeneral, 785 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 786def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB), 787 "fneg $frD, $frB", FPGeneral, 788 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 789} 790 791 792// XL-Form instructions. condition register logical ops. 793// 794def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA), 795 "mcrf $BF, $BFA", BrMCR>, 796 PPC970_DGroup_First, PPC970_Unit_CRU; 797 798// XFX-Form instructions. Instructions that deal with SPRs. 799// 800def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>, 801 PPC970_DGroup_First, PPC970_Unit_FXU; 802let Pattern = [(PPCmtctr GPRC:$rS)] in { 803def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>, 804 PPC970_DGroup_First, PPC970_Unit_FXU; 805} 806 807def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>, 808 PPC970_DGroup_First, PPC970_Unit_FXU; 809def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>, 810 PPC970_DGroup_First, PPC970_Unit_FXU; 811 812// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 813// a GPR on the PPC970. As such, copies in and out have the same performance 814// characteristics as an OR instruction. 815def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), 816 "mtspr 256, $rS", IntGeneral>, 817 PPC970_DGroup_Single, PPC970_Unit_FXU; 818def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), 819 "mfspr $rT, 256", IntGeneral>, 820 PPC970_DGroup_First, PPC970_Unit_FXU; 821 822def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS), 823 "mtcrf $FXM, $rS", BrMCRX>, 824 PPC970_MicroCode, PPC970_Unit_CRU; 825def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>, 826 PPC970_MicroCode, PPC970_Unit_CRU; 827def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM), 828 "mfcr $rT, $FXM", SprMFCR>, 829 PPC970_DGroup_First, PPC970_Unit_CRU; 830 831let PPC970_Unit = 1 in { // FXU Operations. 832 833// XO-Form instructions. Arithmetic instructions that can set overflow bit 834// 835def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 836 "add $rT, $rA, $rB", IntGeneral, 837 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 838def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 839 "addc $rT, $rA, $rB", IntGeneral, 840 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 841 PPC970_DGroup_Cracked; 842def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 843 "adde $rT, $rA, $rB", IntGeneral, 844 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 845def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 846 "divw $rT, $rA, $rB", IntDivW, 847 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 848 PPC970_DGroup_First, PPC970_DGroup_Cracked; 849def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 850 "divwu $rT, $rA, $rB", IntDivW, 851 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 852 PPC970_DGroup_First, PPC970_DGroup_Cracked; 853def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 854 "mulhw $rT, $rA, $rB", IntMulHW, 855 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 856def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 857 "mulhwu $rT, $rA, $rB", IntMulHWU, 858 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 859def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 860 "mullw $rT, $rA, $rB", IntMulHW, 861 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 862def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 863 "subf $rT, $rA, $rB", IntGeneral, 864 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 865def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 866 "subfc $rT, $rA, $rB", IntGeneral, 867 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 868 PPC970_DGroup_Cracked; 869def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 870 "subfe $rT, $rA, $rB", IntGeneral, 871 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 872def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA), 873 "addme $rT, $rA", IntGeneral, 874 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>; 875def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA), 876 "addze $rT, $rA", IntGeneral, 877 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 878def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA), 879 "neg $rT, $rA", IntGeneral, 880 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 881def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA), 882 "subfme $rT, $rA", IntGeneral, 883 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>; 884def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA), 885 "subfze $rT, $rA", IntGeneral, 886 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 887} 888 889// A-Form instructions. Most of the instructions executed in the FPU are of 890// this type. 891// 892let PPC970_Unit = 3 in { // FPU Operations. 893def FMADD : AForm_1<63, 29, 894 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 895 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 896 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), 897 F8RC:$FRB))]>, 898 Requires<[FPContractions]>; 899def FMADDS : AForm_1<59, 29, 900 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 901 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 902 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), 903 F4RC:$FRB))]>, 904 Requires<[FPContractions]>; 905def FMSUB : AForm_1<63, 28, 906 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 907 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 908 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), 909 F8RC:$FRB))]>, 910 Requires<[FPContractions]>; 911def FMSUBS : AForm_1<59, 28, 912 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 913 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 914 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), 915 F4RC:$FRB))]>, 916 Requires<[FPContractions]>; 917def FNMADD : AForm_1<63, 31, 918 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 919 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 920 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), 921 F8RC:$FRB)))]>, 922 Requires<[FPContractions]>; 923def FNMADDS : AForm_1<59, 31, 924 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 925 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 926 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), 927 F4RC:$FRB)))]>, 928 Requires<[FPContractions]>; 929def FNMSUB : AForm_1<63, 30, 930 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 931 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 932 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), 933 F8RC:$FRB)))]>, 934 Requires<[FPContractions]>; 935def FNMSUBS : AForm_1<59, 30, 936 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 937 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 938 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), 939 F4RC:$FRB)))]>, 940 Requires<[FPContractions]>; 941// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 942// having 4 of these, force the comparison to always be an 8-byte double (code 943// should use an FMRSD if the input comparison value really wants to be a float) 944// and 4/8 byte forms for the result and operand type.. 945def FSELD : AForm_1<63, 23, 946 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 947 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 948 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 949def FSELS : AForm_1<63, 23, 950 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 951 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 952 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 953def FADD : AForm_2<63, 21, 954 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 955 "fadd $FRT, $FRA, $FRB", FPGeneral, 956 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 957def FADDS : AForm_2<59, 21, 958 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 959 "fadds $FRT, $FRA, $FRB", FPGeneral, 960 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 961def FDIV : AForm_2<63, 18, 962 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 963 "fdiv $FRT, $FRA, $FRB", FPDivD, 964 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 965def FDIVS : AForm_2<59, 18, 966 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 967 "fdivs $FRT, $FRA, $FRB", FPDivS, 968 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 969def FMUL : AForm_3<63, 25, 970 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 971 "fmul $FRT, $FRA, $FRB", FPFused, 972 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 973def FMULS : AForm_3<59, 25, 974 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 975 "fmuls $FRT, $FRA, $FRB", FPGeneral, 976 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 977def FSUB : AForm_2<63, 20, 978 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 979 "fsub $FRT, $FRA, $FRB", FPGeneral, 980 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 981def FSUBS : AForm_2<59, 20, 982 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 983 "fsubs $FRT, $FRA, $FRB", FPGeneral, 984 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 985} 986 987let PPC970_Unit = 1 in { // FXU Operations. 988// M-Form instructions. rotate and mask instructions. 989// 990let isCommutable = 1 in { 991// RLWIMI can be commuted if the rotate amount is zero. 992def RLWIMI : MForm_2<20, 993 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 994 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 995 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 996 NoEncode<"$rSi">; 997} 998def RLWINM : MForm_2<21, 999 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1000 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 1001 []>; 1002def RLWINMo : MForm_2<21, 1003 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1004 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 1005 []>, isDOT, PPC970_DGroup_Cracked; 1006def RLWNM : MForm_2<23, 1007 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 1008 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 1009 []>; 1010} 1011 1012 1013//===----------------------------------------------------------------------===// 1014// DWARF Pseudo Instructions 1015// 1016 1017def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file), 1018 "${:comment} .loc $file, $line, $col", 1019 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), 1020 (i32 imm:$file))]>; 1021 1022def DWARF_LABEL : Pseudo<(ops i32imm:$id), 1023 "\n${:private}debug_loc$id:", 1024 [(dwarf_label (i32 imm:$id))]>; 1025 1026//===----------------------------------------------------------------------===// 1027// PowerPC Instruction Patterns 1028// 1029 1030// Arbitrary immediate support. Implement in terms of LIS/ORI. 1031def : Pat<(i32 imm:$imm), 1032 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1033 1034// Implement the 'not' operation with the NOR instruction. 1035def NOT : Pat<(not GPRC:$in), 1036 (NOR GPRC:$in, GPRC:$in)>; 1037 1038// ADD an arbitrary immediate. 1039def : Pat<(add GPRC:$in, imm:$imm), 1040 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1041// OR an arbitrary immediate. 1042def : Pat<(or GPRC:$in, imm:$imm), 1043 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1044// XOR an arbitrary immediate. 1045def : Pat<(xor GPRC:$in, imm:$imm), 1046 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1047// SUBFIC 1048def : Pat<(sub immSExt16:$imm, GPRC:$in), 1049 (SUBFIC GPRC:$in, imm:$imm)>; 1050 1051// Return void support. 1052def : Pat<(ret), (BLR)>; 1053 1054// SHL/SRL 1055def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1056 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1057def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1058 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1059 1060// ROTL 1061def : Pat<(rotl GPRC:$in, GPRC:$sh), 1062 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1063def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1064 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1065 1066// RLWNM 1067def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm), 1068 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 1069 1070// Calls 1071def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 1072 (BL tglobaladdr:$dst)>; 1073def : Pat<(PPCcall (i32 texternalsym:$dst)), 1074 (BL texternalsym:$dst)>; 1075 1076// Hi and Lo for Darwin Global Addresses. 1077def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1078def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1079def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1080def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1081def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1082def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1083def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1084 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1085def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1086 (ADDIS GPRC:$in, tconstpool:$g)>; 1087def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 1088 (ADDIS GPRC:$in, tjumptable:$g)>; 1089 1090// Fused negative multiply subtract, alternate pattern 1091def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), 1092 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>, 1093 Requires<[FPContractions]>; 1094def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)), 1095 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>, 1096 Requires<[FPContractions]>; 1097 1098// Standard shifts. These are represented separately from the real shifts above 1099// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1100// amounts. 1101def : Pat<(sra GPRC:$rS, GPRC:$rB), 1102 (SRAW GPRC:$rS, GPRC:$rB)>; 1103def : Pat<(srl GPRC:$rS, GPRC:$rB), 1104 (SRW GPRC:$rS, GPRC:$rB)>; 1105def : Pat<(shl GPRC:$rS, GPRC:$rB), 1106 (SLW GPRC:$rS, GPRC:$rB)>; 1107 1108def : Pat<(zextloadi1 iaddr:$src), 1109 (LBZ iaddr:$src)>; 1110def : Pat<(zextloadi1 xaddr:$src), 1111 (LBZX xaddr:$src)>; 1112def : Pat<(extloadi1 iaddr:$src), 1113 (LBZ iaddr:$src)>; 1114def : Pat<(extloadi1 xaddr:$src), 1115 (LBZX xaddr:$src)>; 1116def : Pat<(extloadi8 iaddr:$src), 1117 (LBZ iaddr:$src)>; 1118def : Pat<(extloadi8 xaddr:$src), 1119 (LBZX xaddr:$src)>; 1120def : Pat<(extloadi16 iaddr:$src), 1121 (LHZ iaddr:$src)>; 1122def : Pat<(extloadi16 xaddr:$src), 1123 (LHZX xaddr:$src)>; 1124def : Pat<(extloadf32 iaddr:$src), 1125 (FMRSD (LFS iaddr:$src))>; 1126def : Pat<(extloadf32 xaddr:$src), 1127 (FMRSD (LFSX xaddr:$src))>; 1128 1129include "PPCInstrAltivec.td" 1130include "PPCInstr64Bit.td" 1131