PPCInstrInfo.td revision 06ab2c828a5605abec36eb0d6749940fa6eb7391
1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 24def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 25 SDTCisVT<1, i32> ]>; 26def SDT_PPCvperm : SDTypeProfile<1, 3, [ 27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 28]>; 29 30def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 32]>; 33 34def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 36]>; 37 38def SDT_PPClbrx : SDTypeProfile<1, 2, [ 39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 40]>; 41def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 43]>; 44 45def SDT_PPClarx : SDTypeProfile<1, 1, [ 46 SDTCisInt<0>, SDTCisPtrTy<1> 47]>; 48def SDT_PPCstcx : SDTypeProfile<0, 2, [ 49 SDTCisInt<0>, SDTCisPtrTy<1> 50]>; 51 52def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 53 SDTCisPtrTy<0>, SDTCisVT<1, i32> 54]>; 55 56def SDT_PPCnop : SDTypeProfile<0, 0, []>; 57 58//===----------------------------------------------------------------------===// 59// PowerPC specific DAG Nodes. 60// 61 62def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 63def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 64def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 65def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 66 [SDNPHasChain, SDNPMayStore]>; 67 68// This sequence is used for long double->int conversions. It changes the 69// bits in the FPSCR which is not modelled. 70def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 71 [SDNPOutGlue]>; 72def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 73 [SDNPInGlue, SDNPOutGlue]>; 74def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 75 [SDNPInGlue, SDNPOutGlue]>; 76def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, 77 [SDNPInGlue, SDNPOutGlue]>; 78def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3, 79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>, 80 SDTCisVT<3, f64>]>, 81 [SDNPInGlue]>; 82 83def PPCfsel : SDNode<"PPCISD::FSEL", 84 // Type constraint for fsel. 85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 87 88def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 89def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 90def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>; 91def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 92def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 93 94def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 95def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 96 [SDNPMayLoad]>; 97def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 98def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 99def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 100def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 101def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 102def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 103def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 104def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp, 105 [SDNPHasChain]>; 106def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 107 108def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 109 110// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 111// amounts. These nodes are generated by the multi-precision shift code. 112def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 113def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 114def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 115 116def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 117def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, 118 [SDNPHasChain, SDNPMayStore]>; 119 120// These are target-independent nodes, but have target-specific formats. 121def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 122 [SDNPHasChain, SDNPOutGlue]>; 123def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 125 126def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 127def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall, 128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 129 SDNPVariadic]>; 130def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall, 131 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 132 SDNPVariadic]>; 133def PPCcall_nop_SVR4 : SDNode<"PPCISD::CALL_NOP_SVR4", SDT_PPCCall, 134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 135 SDNPVariadic]>; 136def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>; 137def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>, 138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 139def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>, 140 [SDNPHasChain, SDNPSideEffect, 141 SDNPInGlue, SDNPOutGlue]>; 142def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>, 143 [SDNPHasChain, SDNPSideEffect, 144 SDNPInGlue, SDNPOutGlue]>; 145def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 147def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone, 148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 149 SDNPVariadic]>; 150 151def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone, 152 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 153 SDNPVariadic]>; 154 155def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 156 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 157 158def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 159 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 160 161def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 162def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 163 164def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 165 [SDNPHasChain, SDNPOptInGlue]>; 166 167def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 168 [SDNPHasChain, SDNPMayLoad]>; 169def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 170 [SDNPHasChain, SDNPMayStore]>; 171 172// Instructions to set/unset CR bit 6 for SVR4 vararg calls 173def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 175def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 176 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 177 178// Instructions to support atomic operations 179def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, 180 [SDNPHasChain, SDNPMayLoad]>; 181def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, 182 [SDNPHasChain, SDNPMayStore]>; 183 184// Instructions to support medium code model 185def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>; 186def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>; 187def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>; 188 189 190// Instructions to support dynamic alloca. 191def SDTDynOp : SDTypeProfile<1, 2, []>; 192def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 193 194//===----------------------------------------------------------------------===// 195// PowerPC specific transformation functions and pattern fragments. 196// 197 198def SHL32 : SDNodeXForm<imm, [{ 199 // Transformation function: 31 - imm 200 return getI32Imm(31 - N->getZExtValue()); 201}]>; 202 203def SRL32 : SDNodeXForm<imm, [{ 204 // Transformation function: 32 - imm 205 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0); 206}]>; 207 208def LO16 : SDNodeXForm<imm, [{ 209 // Transformation function: get the low 16 bits. 210 return getI32Imm((unsigned short)N->getZExtValue()); 211}]>; 212 213def HI16 : SDNodeXForm<imm, [{ 214 // Transformation function: shift the immediate value down into the low bits. 215 return getI32Imm((unsigned)N->getZExtValue() >> 16); 216}]>; 217 218def HA16 : SDNodeXForm<imm, [{ 219 // Transformation function: shift the immediate value down into the low bits. 220 signed int Val = N->getZExtValue(); 221 return getI32Imm((Val - (signed short)Val) >> 16); 222}]>; 223def MB : SDNodeXForm<imm, [{ 224 // Transformation function: get the start bit of a mask 225 unsigned mb = 0, me; 226 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 227 return getI32Imm(mb); 228}]>; 229 230def ME : SDNodeXForm<imm, [{ 231 // Transformation function: get the end bit of a mask 232 unsigned mb, me = 0; 233 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 234 return getI32Imm(me); 235}]>; 236def maskimm32 : PatLeaf<(imm), [{ 237 // maskImm predicate - True if immediate is a run of ones. 238 unsigned mb, me; 239 if (N->getValueType(0) == MVT::i32) 240 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 241 else 242 return false; 243}]>; 244 245def immSExt16 : PatLeaf<(imm), [{ 246 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 247 // field. Used by instructions like 'addi'. 248 if (N->getValueType(0) == MVT::i32) 249 return (int32_t)N->getZExtValue() == (short)N->getZExtValue(); 250 else 251 return (int64_t)N->getZExtValue() == (short)N->getZExtValue(); 252}]>; 253def immZExt16 : PatLeaf<(imm), [{ 254 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 255 // field. Used by instructions like 'ori'. 256 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 257}], LO16>; 258 259// imm16Shifted* - These match immediates where the low 16-bits are zero. There 260// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 261// identical in 32-bit mode, but in 64-bit mode, they return true if the 262// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 263// clear). 264def imm16ShiftedZExt : PatLeaf<(imm), [{ 265 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 266 // immediate are set. Used by instructions like 'xoris'. 267 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 268}], HI16>; 269 270def imm16ShiftedSExt : PatLeaf<(imm), [{ 271 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 272 // immediate are set. Used by instructions like 'addis'. Identical to 273 // imm16ShiftedZExt in 32-bit mode. 274 if (N->getZExtValue() & 0xFFFF) return false; 275 if (N->getValueType(0) == MVT::i32) 276 return true; 277 // For 64-bit, make sure it is sext right. 278 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 279}], HI16>; 280 281 282//===----------------------------------------------------------------------===// 283// PowerPC Flag Definitions. 284 285class isPPC64 { bit PPC64 = 1; } 286class isDOT { 287 list<Register> Defs = [CR0]; 288 bit RC = 1; 289} 290 291class RegConstraint<string C> { 292 string Constraints = C; 293} 294class NoEncode<string E> { 295 string DisableEncoding = E; 296} 297 298 299//===----------------------------------------------------------------------===// 300// PowerPC Operand Definitions. 301 302def s5imm : Operand<i32> { 303 let PrintMethod = "printS5ImmOperand"; 304} 305def u5imm : Operand<i32> { 306 let PrintMethod = "printU5ImmOperand"; 307} 308def u6imm : Operand<i32> { 309 let PrintMethod = "printU6ImmOperand"; 310} 311def s16imm : Operand<i32> { 312 let PrintMethod = "printS16ImmOperand"; 313} 314def u16imm : Operand<i32> { 315 let PrintMethod = "printU16ImmOperand"; 316} 317def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 318 let PrintMethod = "printS16X4ImmOperand"; 319} 320def directbrtarget : Operand<OtherVT> { 321 let PrintMethod = "printBranchOperand"; 322 let EncoderMethod = "getDirectBrEncoding"; 323} 324def condbrtarget : Operand<OtherVT> { 325 let PrintMethod = "printBranchOperand"; 326 let EncoderMethod = "getCondBrEncoding"; 327} 328def calltarget : Operand<iPTR> { 329 let EncoderMethod = "getDirectBrEncoding"; 330} 331def aaddr : Operand<iPTR> { 332 let PrintMethod = "printAbsAddrOperand"; 333} 334def symbolHi: Operand<i32> { 335 let PrintMethod = "printSymbolHi"; 336 let EncoderMethod = "getHA16Encoding"; 337} 338def symbolLo: Operand<i32> { 339 let PrintMethod = "printSymbolLo"; 340 let EncoderMethod = "getLO16Encoding"; 341} 342def crbitm: Operand<i8> { 343 let PrintMethod = "printcrbitm"; 344 let EncoderMethod = "get_crbitm_encoding"; 345} 346// Address operands 347def memri : Operand<iPTR> { 348 let PrintMethod = "printMemRegImm"; 349 let MIOperandInfo = (ops symbolLo:$imm, ptr_rc:$reg); 350 let EncoderMethod = "getMemRIEncoding"; 351} 352def memrr : Operand<iPTR> { 353 let PrintMethod = "printMemRegReg"; 354 let MIOperandInfo = (ops ptr_rc:$offreg, ptr_rc:$ptrreg); 355} 356def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 357 let PrintMethod = "printMemRegImmShifted"; 358 let MIOperandInfo = (ops symbolLo:$imm, ptr_rc:$reg); 359 let EncoderMethod = "getMemRIXEncoding"; 360} 361 362// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg 363// that doesn't matter. 364def pred : PredicateOperand<OtherVT, (ops imm, CRRC), 365 (ops (i32 20), (i32 zero_reg))> { 366 let PrintMethod = "printPredicateOperand"; 367} 368 369// Define PowerPC specific addressing mode. 370def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 371def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 372def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 373def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 374 375/// This is just the offset part of iaddr, used for preinc. 376def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 377def xaddroff : ComplexPattern<iPTR, 1, "SelectAddrIdxOffs", [], []>; 378 379//===----------------------------------------------------------------------===// 380// PowerPC Instruction Predicate Definitions. 381def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">; 382def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">; 383def IsBookE : Predicate<"PPCSubTarget.isBookE()">; 384 385//===----------------------------------------------------------------------===// 386// PowerPC Instruction Definitions. 387 388// Pseudo-instructions: 389 390let hasCtrlDep = 1 in { 391let Defs = [R1], Uses = [R1] in { 392def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt", 393 [(callseq_start timm:$amt)]>; 394def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2", 395 [(callseq_end timm:$amt1, timm:$amt2)]>; 396} 397 398def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), 399 "UPDATE_VRSAVE $rD, $rS", []>; 400} 401 402let Defs = [R1], Uses = [R1] in 403def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC", 404 [(set GPRC:$result, 405 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>; 406 407// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 408// instruction selection into a branch sequence. 409let usesCustomInserter = 1, // Expanded after instruction selection. 410 PPC970_Single = 1 in { 411 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F, 412 i32imm:$BROPC), "#SELECT_CC_I4", 413 []>; 414 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F, 415 i32imm:$BROPC), "#SELECT_CC_I8", 416 []>; 417 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F, 418 i32imm:$BROPC), "#SELECT_CC_F4", 419 []>; 420 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F, 421 i32imm:$BROPC), "#SELECT_CC_F8", 422 []>; 423 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F, 424 i32imm:$BROPC), "#SELECT_CC_VRRC", 425 []>; 426} 427 428// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 429// scavenge a register for it. 430let mayStore = 1 in 431def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F), 432 "#SPILL_CR", []>; 433 434// RESTORE_CR - Indicate that we're restoring the CR register (previously 435// spilled), so we'll need to scavenge a register for it. 436let mayLoad = 1 in 437def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F), 438 "#RESTORE_CR", []>; 439 440let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 441 let isCodeGenOnly = 1, isReturn = 1, Uses = [LR, RM] in 442 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), 443 "b${p:cc}lr ${p:reg}", BrB, 444 [(retflag)]>; 445 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in 446 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; 447} 448 449let Defs = [LR] in 450 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>, 451 PPC970_Unit_BRU; 452 453let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 454 let isBarrier = 1 in { 455 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 456 "b $dst", BrB, 457 [(br bb:$dst)]>; 458 } 459 460 // BCC represents an arbitrary conditional branch on a predicate. 461 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 462 // a two-value operand where a dag node expects two operands. :( 463 let isCodeGenOnly = 1 in 464 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 465 "b${cond:cc} ${cond:reg}, $dst" 466 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; 467 468 let Defs = [CTR], Uses = [CTR] in { 469 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 470 "bdz $dst">; 471 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 472 "bdnz $dst">; 473 } 474} 475 476// Darwin ABI Calls. 477let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 478 // Convenient aliases for call instructions 479 let Uses = [RM] in { 480 def BL_Darwin : IForm<18, 0, 1, 481 (outs), (ins calltarget:$func), 482 "bl $func", BrB, []>; // See Pat patterns below. 483 def BLA_Darwin : IForm<18, 1, 1, 484 (outs), (ins aaddr:$func), 485 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>; 486 } 487 let Uses = [CTR, RM] in { 488 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 489 (outs), (ins), 490 "bctrl", BrB, 491 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>; 492 } 493} 494 495// SVR4 ABI Calls. 496let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 497 // Convenient aliases for call instructions 498 let Uses = [RM] in { 499 def BL_SVR4 : IForm<18, 0, 1, 500 (outs), (ins calltarget:$func), 501 "bl $func", BrB, []>; // See Pat patterns below. 502 def BLA_SVR4 : IForm<18, 1, 1, 503 (outs), (ins aaddr:$func), 504 "bla $func", BrB, 505 [(PPCcall_SVR4 (i32 imm:$func))]>; 506 } 507 let Uses = [CTR, RM] in { 508 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1, 509 (outs), (ins), 510 "bctrl", BrB, 511 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>; 512 } 513} 514 515 516let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 517def TCRETURNdi :Pseudo< (outs), 518 (ins calltarget:$dst, i32imm:$offset), 519 "#TC_RETURNd $dst $offset", 520 []>; 521 522 523let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 524def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), 525 "#TC_RETURNa $func $offset", 526 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 527 528let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 529def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 530 "#TC_RETURNr $dst $offset", 531 []>; 532 533 534let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 535 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 536def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 537 Requires<[In32BitMode]>; 538 539 540 541let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 542 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 543def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 544 "b $dst", BrB, 545 []>; 546 547 548let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 549 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 550def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 551 "ba $dst", BrB, 552 []>; 553 554 555// DCB* instructions. 556def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), 557 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 558 PPC970_DGroup_Single; 559def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), 560 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 561 PPC970_DGroup_Single; 562def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), 563 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 564 PPC970_DGroup_Single; 565def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), 566 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 567 PPC970_DGroup_Single; 568def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), 569 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 570 PPC970_DGroup_Single; 571def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), 572 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 573 PPC970_DGroup_Single; 574def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), 575 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 576 PPC970_DGroup_Single; 577def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), 578 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 579 PPC970_DGroup_Single; 580 581def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 582 (DCBT xoaddr:$dst)>; 583 584// Atomic operations 585let usesCustomInserter = 1 in { 586 let Defs = [CR0] in { 587 def ATOMIC_LOAD_ADD_I8 : Pseudo< 588 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8", 589 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>; 590 def ATOMIC_LOAD_SUB_I8 : Pseudo< 591 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8", 592 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>; 593 def ATOMIC_LOAD_AND_I8 : Pseudo< 594 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8", 595 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>; 596 def ATOMIC_LOAD_OR_I8 : Pseudo< 597 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8", 598 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>; 599 def ATOMIC_LOAD_XOR_I8 : Pseudo< 600 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8", 601 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>; 602 def ATOMIC_LOAD_NAND_I8 : Pseudo< 603 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8", 604 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>; 605 def ATOMIC_LOAD_ADD_I16 : Pseudo< 606 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16", 607 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>; 608 def ATOMIC_LOAD_SUB_I16 : Pseudo< 609 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16", 610 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>; 611 def ATOMIC_LOAD_AND_I16 : Pseudo< 612 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16", 613 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>; 614 def ATOMIC_LOAD_OR_I16 : Pseudo< 615 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16", 616 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>; 617 def ATOMIC_LOAD_XOR_I16 : Pseudo< 618 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16", 619 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>; 620 def ATOMIC_LOAD_NAND_I16 : Pseudo< 621 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16", 622 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>; 623 def ATOMIC_LOAD_ADD_I32 : Pseudo< 624 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32", 625 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>; 626 def ATOMIC_LOAD_SUB_I32 : Pseudo< 627 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32", 628 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>; 629 def ATOMIC_LOAD_AND_I32 : Pseudo< 630 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32", 631 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>; 632 def ATOMIC_LOAD_OR_I32 : Pseudo< 633 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32", 634 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>; 635 def ATOMIC_LOAD_XOR_I32 : Pseudo< 636 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32", 637 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>; 638 def ATOMIC_LOAD_NAND_I32 : Pseudo< 639 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32", 640 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>; 641 642 def ATOMIC_CMP_SWAP_I8 : Pseudo< 643 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8", 644 [(set GPRC:$dst, 645 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 646 def ATOMIC_CMP_SWAP_I16 : Pseudo< 647 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 648 [(set GPRC:$dst, 649 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 650 def ATOMIC_CMP_SWAP_I32 : Pseudo< 651 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 652 [(set GPRC:$dst, 653 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 654 655 def ATOMIC_SWAP_I8 : Pseudo< 656 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8", 657 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>; 658 def ATOMIC_SWAP_I16 : Pseudo< 659 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16", 660 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>; 661 def ATOMIC_SWAP_I32 : Pseudo< 662 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32", 663 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>; 664 } 665} 666 667// Instructions to support atomic operations 668def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src), 669 "lwarx $rD, $src", LdStLWARX, 670 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>; 671 672let Defs = [CR0] in 673def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst), 674 "stwcx. $rS, $dst", LdStSTWCX, 675 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, 676 isDOT; 677 678let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 679def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>; 680 681//===----------------------------------------------------------------------===// 682// PPC32 Load Instructions. 683// 684 685// Unindexed (r+i) Loads. 686let canFoldAsLoad = 1, PPC970_Unit = 2 in { 687def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), 688 "lbz $rD, $src", LdStLoad, 689 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 690def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), 691 "lha $rD, $src", LdStLHA, 692 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, 693 PPC970_DGroup_Cracked; 694def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src), 695 "lhz $rD, $src", LdStLoad, 696 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; 697def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src), 698 "lwz $rD, $src", LdStLoad, 699 [(set GPRC:$rD, (load iaddr:$src))]>; 700 701def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src), 702 "lfs $rD, $src", LdStLFD, 703 [(set F4RC:$rD, (load iaddr:$src))]>; 704def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), 705 "lfd $rD, $src", LdStLFD, 706 [(set F8RC:$rD, (load iaddr:$src))]>; 707 708 709// Unindexed (r+i) Loads with Update (preinc). 710let mayLoad = 1 in { 711def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 712 "lbzu $rD, $addr", LdStLoadUpd, 713 []>, RegConstraint<"$addr.reg = $ea_result">, 714 NoEncode<"$ea_result">; 715 716def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 717 "lhau $rD, $addr", LdStLHAU, 718 []>, RegConstraint<"$addr.reg = $ea_result">, 719 NoEncode<"$ea_result">; 720 721def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 722 "lhzu $rD, $addr", LdStLoadUpd, 723 []>, RegConstraint<"$addr.reg = $ea_result">, 724 NoEncode<"$ea_result">; 725 726def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 727 "lwzu $rD, $addr", LdStLoadUpd, 728 []>, RegConstraint<"$addr.reg = $ea_result">, 729 NoEncode<"$ea_result">; 730 731def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 732 "lfsu $rD, $addr", LdStLFDU, 733 []>, RegConstraint<"$addr.reg = $ea_result">, 734 NoEncode<"$ea_result">; 735 736def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 737 "lfdu $rD, $addr", LdStLFDU, 738 []>, RegConstraint<"$addr.reg = $ea_result">, 739 NoEncode<"$ea_result">; 740 741 742// Indexed (r+r) Loads with Update (preinc). 743def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc:$ea_result), 744 (ins memrr:$addr), 745 "lbzux $rD, $addr", LdStLoadUpd, 746 []>, RegConstraint<"$addr.offreg = $ea_result">, 747 NoEncode<"$ea_result">; 748 749def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc:$ea_result), 750 (ins memrr:$addr), 751 "lhaux $rD, $addr", LdStLHAU, 752 []>, RegConstraint<"$addr.offreg = $ea_result">, 753 NoEncode<"$ea_result">; 754 755def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc:$ea_result), 756 (ins memrr:$addr), 757 "lhzux $rD, $addr", LdStLoadUpd, 758 []>, RegConstraint<"$addr.offreg = $ea_result">, 759 NoEncode<"$ea_result">; 760 761def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc:$ea_result), 762 (ins memrr:$addr), 763 "lwzux $rD, $addr", LdStLoadUpd, 764 []>, RegConstraint<"$addr.offreg = $ea_result">, 765 NoEncode<"$ea_result">; 766 767def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc:$ea_result), 768 (ins memrr:$addr), 769 "lfsux $rD, $addr", LdStLFDU, 770 []>, RegConstraint<"$addr.offreg = $ea_result">, 771 NoEncode<"$ea_result">; 772 773def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc:$ea_result), 774 (ins memrr:$addr), 775 "lfdux $rD, $addr", LdStLFDU, 776 []>, RegConstraint<"$addr.offreg = $ea_result">, 777 NoEncode<"$ea_result">; 778} 779} 780 781// Indexed (r+r) Loads. 782// 783let canFoldAsLoad = 1, PPC970_Unit = 2 in { 784def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), 785 "lbzx $rD, $src", LdStLoad, 786 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; 787def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src), 788 "lhax $rD, $src", LdStLHA, 789 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, 790 PPC970_DGroup_Cracked; 791def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src), 792 "lhzx $rD, $src", LdStLoad, 793 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; 794def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src), 795 "lwzx $rD, $src", LdStLoad, 796 [(set GPRC:$rD, (load xaddr:$src))]>; 797 798 799def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src), 800 "lhbrx $rD, $src", LdStLoad, 801 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>; 802def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src), 803 "lwbrx $rD, $src", LdStLoad, 804 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>; 805 806def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src), 807 "lfsx $frD, $src", LdStLFD, 808 [(set F4RC:$frD, (load xaddr:$src))]>; 809def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src), 810 "lfdx $frD, $src", LdStLFD, 811 [(set F8RC:$frD, (load xaddr:$src))]>; 812} 813 814//===----------------------------------------------------------------------===// 815// PPC32 Store Instructions. 816// 817 818// Unindexed (r+i) Stores. 819let PPC970_Unit = 2 in { 820def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src), 821 "stb $rS, $src", LdStStore, 822 [(truncstorei8 GPRC:$rS, iaddr:$src)]>; 823def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src), 824 "sth $rS, $src", LdStStore, 825 [(truncstorei16 GPRC:$rS, iaddr:$src)]>; 826def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src), 827 "stw $rS, $src", LdStStore, 828 [(store GPRC:$rS, iaddr:$src)]>; 829def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst), 830 "stfs $rS, $dst", LdStSTFD, 831 [(store F4RC:$rS, iaddr:$dst)]>; 832def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst), 833 "stfd $rS, $dst", LdStSTFD, 834 [(store F8RC:$rS, iaddr:$dst)]>; 835} 836 837// Unindexed (r+i) Stores with Update (preinc). 838let PPC970_Unit = 2 in { 839def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 840 symbolLo:$ptroff, ptr_rc:$ptrreg), 841 "stbu $rS, $ptroff($ptrreg)", LdStStoreUpd, 842 [(set ptr_rc:$ea_res, 843 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, 844 iaddroff:$ptroff))]>, 845 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 846def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 847 symbolLo:$ptroff, ptr_rc:$ptrreg), 848 "sthu $rS, $ptroff($ptrreg)", LdStStoreUpd, 849 [(set ptr_rc:$ea_res, 850 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, 851 iaddroff:$ptroff))]>, 852 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 853def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 854 symbolLo:$ptroff, ptr_rc:$ptrreg), 855 "stwu $rS, $ptroff($ptrreg)", LdStStoreUpd, 856 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg, 857 iaddroff:$ptroff))]>, 858 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 859def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS, 860 symbolLo:$ptroff, ptr_rc:$ptrreg), 861 "stfsu $rS, $ptroff($ptrreg)", LdStSTFDU, 862 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg, 863 iaddroff:$ptroff))]>, 864 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 865def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS, 866 symbolLo:$ptroff, ptr_rc:$ptrreg), 867 "stfdu $rS, $ptroff($ptrreg)", LdStSTFDU, 868 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg, 869 iaddroff:$ptroff))]>, 870 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 871} 872 873 874// Indexed (r+r) Stores. 875// 876let PPC970_Unit = 2 in { 877def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst), 878 "stbx $rS, $dst", LdStStore, 879 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, 880 PPC970_DGroup_Cracked; 881def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst), 882 "sthx $rS, $dst", LdStStore, 883 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, 884 PPC970_DGroup_Cracked; 885def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst), 886 "stwx $rS, $dst", LdStStore, 887 [(store GPRC:$rS, xaddr:$dst)]>, 888 PPC970_DGroup_Cracked; 889 890def STBUX : XForm_8<31, 247, (outs ptr_rc:$ea_res), 891 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 892 "stbux $rS, $ptroff, $ptrreg", LdStStoreUpd, 893 [(set ptr_rc:$ea_res, 894 (pre_truncsti8 GPRC:$rS, 895 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 896 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 897 PPC970_DGroup_Cracked; 898 899def STHUX : XForm_8<31, 439, (outs ptr_rc:$ea_res), 900 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 901 "sthux $rS, $ptroff, $ptrreg", LdStStoreUpd, 902 [(set ptr_rc:$ea_res, 903 (pre_truncsti16 GPRC:$rS, 904 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 905 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 906 PPC970_DGroup_Cracked; 907 908def STWUX : XForm_8<31, 183, (outs ptr_rc:$ea_res), 909 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 910 "stwux $rS, $ptroff, $ptrreg", LdStStoreUpd, 911 [(set ptr_rc:$ea_res, 912 (pre_store GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 913 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 914 PPC970_DGroup_Cracked; 915 916def STFSUX : XForm_8<31, 695, (outs ptr_rc:$ea_res), 917 (ins F4RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 918 "stfsux $rS, $ptroff, $ptrreg", LdStSTFDU, 919 [(set ptr_rc:$ea_res, 920 (pre_store F4RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 921 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 922 PPC970_DGroup_Cracked; 923 924def STFDUX : XForm_8<31, 759, (outs ptr_rc:$ea_res), 925 (ins F8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 926 "stfdux $rS, $ptroff, $ptrreg", LdStSTFDU, 927 [(set ptr_rc:$ea_res, 928 (pre_store F8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 929 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 930 PPC970_DGroup_Cracked; 931 932def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), 933 "sthbrx $rS, $dst", LdStStore, 934 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>, 935 PPC970_DGroup_Cracked; 936def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst), 937 "stwbrx $rS, $dst", LdStStore, 938 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>, 939 PPC970_DGroup_Cracked; 940 941def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), 942 "stfiwx $frS, $dst", LdStSTFD, 943 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 944 945def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), 946 "stfsx $frS, $dst", LdStSTFD, 947 [(store F4RC:$frS, xaddr:$dst)]>; 948def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst), 949 "stfdx $frS, $dst", LdStSTFD, 950 [(store F8RC:$frS, xaddr:$dst)]>; 951} 952 953def SYNC : XForm_24_sync<31, 598, (outs), (ins), 954 "sync", LdStSync, 955 [(int_ppc_sync)]>; 956 957//===----------------------------------------------------------------------===// 958// PPC32 Arithmetic Instructions. 959// 960 961let PPC970_Unit = 1 in { // FXU Operations. 962def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 963 "addi $rD, $rA, $imm", IntSimple, 964 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 965def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$imm), 966 "addi $rD, $rA, $imm", IntSimple, 967 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 968let Defs = [CARRY] in { 969def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 970 "addic $rD, $rA, $imm", IntGeneral, 971 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 972 PPC970_DGroup_Cracked; 973def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 974 "addic. $rD, $rA, $imm", IntGeneral, 975 []>; 976} 977def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm), 978 "addis $rD, $rA, $imm", IntSimple, 979 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; 980def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym), 981 "la $rD, $sym($rA)", IntGeneral, 982 [(set GPRC:$rD, (add GPRC:$rA, 983 (PPClo tglobaladdr:$sym, 0)))]>; 984def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 985 "mulli $rD, $rA, $imm", IntMulLI, 986 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 987let Defs = [CARRY] in { 988def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 989 "subfic $rD, $rA, $imm", IntGeneral, 990 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 991} 992 993let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 994 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), 995 "li $rD, $imm", IntSimple, 996 [(set GPRC:$rD, immSExt16:$imm)]>; 997 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), 998 "lis $rD, $imm", IntSimple, 999 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; 1000} 1001} 1002 1003let PPC970_Unit = 1 in { // FXU Operations. 1004def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1005 "andi. $dst, $src1, $src2", IntGeneral, 1006 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 1007 isDOT; 1008def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1009 "andis. $dst, $src1, $src2", IntGeneral, 1010 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, 1011 isDOT; 1012def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1013 "ori $dst, $src1, $src2", IntSimple, 1014 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 1015def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1016 "oris $dst, $src1, $src2", IntSimple, 1017 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; 1018def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1019 "xori $dst, $src1, $src2", IntSimple, 1020 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 1021def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1022 "xoris $dst, $src1, $src2", IntSimple, 1023 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; 1024def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple, 1025 []>; 1026def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm), 1027 "cmpwi $crD, $rA, $imm", IntCompare>; 1028def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1029 "cmplwi $dst, $src1, $src2", IntCompare>; 1030} 1031 1032 1033let PPC970_Unit = 1 in { // FXU Operations. 1034def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1035 "nand $rA, $rS, $rB", IntSimple, 1036 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 1037def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1038 "and $rA, $rS, $rB", IntSimple, 1039 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 1040def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1041 "andc $rA, $rS, $rB", IntSimple, 1042 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 1043def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1044 "or $rA, $rS, $rB", IntSimple, 1045 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 1046def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1047 "nor $rA, $rS, $rB", IntSimple, 1048 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 1049def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1050 "orc $rA, $rS, $rB", IntSimple, 1051 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 1052def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1053 "eqv $rA, $rS, $rB", IntSimple, 1054 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 1055def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1056 "xor $rA, $rS, $rB", IntSimple, 1057 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 1058def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1059 "slw $rA, $rS, $rB", IntGeneral, 1060 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 1061def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1062 "srw $rA, $rS, $rB", IntGeneral, 1063 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 1064let Defs = [CARRY] in { 1065def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1066 "sraw $rA, $rS, $rB", IntShift, 1067 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 1068} 1069} 1070 1071let PPC970_Unit = 1 in { // FXU Operations. 1072let Defs = [CARRY] in { 1073def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH), 1074 "srawi $rA, $rS, $SH", IntShift, 1075 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 1076} 1077def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS), 1078 "cntlzw $rA, $rS", IntGeneral, 1079 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 1080def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS), 1081 "extsb $rA, $rS", IntSimple, 1082 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 1083def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS), 1084 "extsh $rA, $rS", IntSimple, 1085 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 1086 1087def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 1088 "cmpw $crD, $rA, $rB", IntCompare>; 1089def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 1090 "cmplw $crD, $rA, $rB", IntCompare>; 1091} 1092let PPC970_Unit = 3 in { // FPU Operations. 1093//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 1094// "fcmpo $crD, $fA, $fB", FPCompare>; 1095def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB), 1096 "fcmpu $crD, $fA, $fB", FPCompare>; 1097def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB), 1098 "fcmpu $crD, $fA, $fB", FPCompare>; 1099 1100let Uses = [RM] in { 1101 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB), 1102 "fctiwz $frD, $frB", FPGeneral, 1103 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 1104 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB), 1105 "frsp $frD, $frB", FPGeneral, 1106 [(set F4RC:$frD, (fround F8RC:$frB))]>; 1107 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB), 1108 "fsqrt $frD, $frB", FPSqrt, 1109 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 1110 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB), 1111 "fsqrts $frD, $frB", FPSqrt, 1112 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 1113 } 1114} 1115 1116/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 1117/// often coalesced away and we don't want the dispatch group builder to think 1118/// that they will fill slots (which could cause the load of a LSU reject to 1119/// sneak into a d-group with a store). 1120def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB), 1121 "fmr $frD, $frB", FPGeneral, 1122 []>, // (set F4RC:$frD, F4RC:$frB) 1123 PPC970_Unit_Pseudo; 1124 1125let PPC970_Unit = 3 in { // FPU Operations. 1126// These are artificially split into two different forms, for 4/8 byte FP. 1127def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB), 1128 "fabs $frD, $frB", FPGeneral, 1129 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 1130def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB), 1131 "fabs $frD, $frB", FPGeneral, 1132 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 1133def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB), 1134 "fnabs $frD, $frB", FPGeneral, 1135 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 1136def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB), 1137 "fnabs $frD, $frB", FPGeneral, 1138 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 1139def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB), 1140 "fneg $frD, $frB", FPGeneral, 1141 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 1142def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB), 1143 "fneg $frD, $frB", FPGeneral, 1144 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 1145} 1146 1147 1148// XL-Form instructions. condition register logical ops. 1149// 1150def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA), 1151 "mcrf $BF, $BFA", BrMCR>, 1152 PPC970_DGroup_First, PPC970_Unit_CRU; 1153 1154def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD), 1155 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1156 "creqv $CRD, $CRA, $CRB", BrCR, 1157 []>; 1158 1159def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD), 1160 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1161 "cror $CRD, $CRA, $CRB", BrCR, 1162 []>; 1163 1164def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins), 1165 "creqv $dst, $dst, $dst", BrCR, 1166 []>; 1167 1168def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins), 1169 "crxor $dst, $dst, $dst", BrCR, 1170 []>; 1171 1172let Defs = [CR1EQ], CRD = 6 in { 1173def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 1174 "creqv 6, 6, 6", BrCR, 1175 [(PPCcr6set)]>; 1176 1177def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 1178 "crxor 6, 6, 6", BrCR, 1179 [(PPCcr6unset)]>; 1180} 1181 1182// XFX-Form instructions. Instructions that deal with SPRs. 1183// 1184let Uses = [CTR] in { 1185def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins), 1186 "mfctr $rT", SprMFSPR>, 1187 PPC970_DGroup_First, PPC970_Unit_FXU; 1188} 1189let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in { 1190def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS), 1191 "mtctr $rS", SprMTSPR>, 1192 PPC970_DGroup_First, PPC970_Unit_FXU; 1193} 1194 1195let Defs = [LR] in { 1196def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS), 1197 "mtlr $rS", SprMTSPR>, 1198 PPC970_DGroup_First, PPC970_Unit_FXU; 1199} 1200let Uses = [LR] in { 1201def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins), 1202 "mflr $rT", SprMFSPR>, 1203 PPC970_DGroup_First, PPC970_Unit_FXU; 1204} 1205 1206// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 1207// a GPR on the PPC970. As such, copies in and out have the same performance 1208// characteristics as an OR instruction. 1209def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS), 1210 "mtspr 256, $rS", IntGeneral>, 1211 PPC970_DGroup_Single, PPC970_Unit_FXU; 1212def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins), 1213 "mfspr $rT, 256", IntGeneral>, 1214 PPC970_DGroup_First, PPC970_Unit_FXU; 1215 1216def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS), 1217 "mtcrf $FXM, $rS", BrMCRX>, 1218 PPC970_MicroCode, PPC970_Unit_CRU; 1219 1220// This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters; 1221// declaring that here gives the local register allocator problems with this: 1222// vreg = MCRF CR0 1223// MFCR <kill of whatever preg got assigned to vreg> 1224// while not declaring it breaks DeadMachineInstructionElimination. 1225// As it turns out, in all cases where we currently use this, 1226// we're only interested in one subregister of it. Represent this in the 1227// instruction to keep the register allocator from becoming confused. 1228// 1229// FIXME: Make this a real Pseudo instruction when the JIT switches to MC. 1230def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1231 "#MFCRpseud", SprMFCR>, 1232 PPC970_MicroCode, PPC970_Unit_CRU; 1233 1234def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), 1235 "mfcr $rT", SprMFCR>, 1236 PPC970_MicroCode, PPC970_Unit_CRU; 1237 1238def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1239 "mfocrf $rT, $FXM", SprMFCR>, 1240 PPC970_DGroup_First, PPC970_Unit_CRU; 1241 1242// Instructions to manipulate FPSCR. Only long double handling uses these. 1243// FPSCR is not modelled; we use the SDNode Flag to keep things in order. 1244 1245let Uses = [RM], Defs = [RM] in { 1246 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 1247 "mtfsb0 $FM", IntMTFSB0, 1248 [(PPCmtfsb0 (i32 imm:$FM))]>, 1249 PPC970_DGroup_Single, PPC970_Unit_FPU; 1250 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 1251 "mtfsb1 $FM", IntMTFSB0, 1252 [(PPCmtfsb1 (i32 imm:$FM))]>, 1253 PPC970_DGroup_Single, PPC970_Unit_FPU; 1254 // MTFSF does not actually produce an FP result. We pretend it copies 1255 // input reg B to the output. If we didn't do this it would look like the 1256 // instruction had no outputs (because we aren't modelling the FPSCR) and 1257 // it would be deleted. 1258 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA), 1259 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB), 1260 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0, 1261 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM), 1262 F8RC:$rT, F8RC:$FRB))]>, 1263 PPC970_DGroup_Single, PPC970_Unit_FPU; 1264} 1265let Uses = [RM] in { 1266 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins), 1267 "mffs $rT", IntMFFS, 1268 [(set F8RC:$rT, (PPCmffs))]>, 1269 PPC970_DGroup_Single, PPC970_Unit_FPU; 1270 def FADDrtz: AForm_2<63, 21, 1271 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1272 "fadd $FRT, $FRA, $FRB", FPAddSub, 1273 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>, 1274 PPC970_DGroup_Single, PPC970_Unit_FPU; 1275} 1276 1277 1278let PPC970_Unit = 1 in { // FXU Operations. 1279 1280// XO-Form instructions. Arithmetic instructions that can set overflow bit 1281// 1282def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1283 "add $rT, $rA, $rB", IntSimple, 1284 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 1285let Defs = [CARRY] in { 1286def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1287 "addc $rT, $rA, $rB", IntGeneral, 1288 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 1289 PPC970_DGroup_Cracked; 1290} 1291def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1292 "divw $rT, $rA, $rB", IntDivW, 1293 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 1294 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1295def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1296 "divwu $rT, $rA, $rB", IntDivW, 1297 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 1298 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1299def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1300 "mulhw $rT, $rA, $rB", IntMulHW, 1301 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 1302def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1303 "mulhwu $rT, $rA, $rB", IntMulHWU, 1304 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 1305def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1306 "mullw $rT, $rA, $rB", IntMulHW, 1307 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 1308def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1309 "subf $rT, $rA, $rB", IntGeneral, 1310 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 1311let Defs = [CARRY] in { 1312def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1313 "subfc $rT, $rA, $rB", IntGeneral, 1314 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 1315 PPC970_DGroup_Cracked; 1316} 1317def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1318 "neg $rT, $rA", IntSimple, 1319 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 1320let Uses = [CARRY], Defs = [CARRY] in { 1321def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1322 "adde $rT, $rA, $rB", IntGeneral, 1323 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 1324def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1325 "addme $rT, $rA", IntGeneral, 1326 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>; 1327def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1328 "addze $rT, $rA", IntGeneral, 1329 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 1330def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1331 "subfe $rT, $rA, $rB", IntGeneral, 1332 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 1333def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1334 "subfme $rT, $rA", IntGeneral, 1335 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>; 1336def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1337 "subfze $rT, $rA", IntGeneral, 1338 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 1339} 1340} 1341 1342// A-Form instructions. Most of the instructions executed in the FPU are of 1343// this type. 1344// 1345let PPC970_Unit = 3 in { // FPU Operations. 1346let Uses = [RM] in { 1347 def FMADD : AForm_1<63, 29, 1348 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1349 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1350 [(set F8RC:$FRT, 1351 (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB))]>; 1352 def FMADDS : AForm_1<59, 29, 1353 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1354 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1355 [(set F4RC:$FRT, 1356 (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB))]>; 1357 def FMSUB : AForm_1<63, 28, 1358 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1359 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1360 [(set F8RC:$FRT, 1361 (fma F8RC:$FRA, F8RC:$FRC, (fneg F8RC:$FRB)))]>; 1362 def FMSUBS : AForm_1<59, 28, 1363 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1364 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1365 [(set F4RC:$FRT, 1366 (fma F4RC:$FRA, F4RC:$FRC, (fneg F4RC:$FRB)))]>; 1367 def FNMADD : AForm_1<63, 31, 1368 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1369 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1370 [(set F8RC:$FRT, 1371 (fneg (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB)))]>; 1372 def FNMADDS : AForm_1<59, 31, 1373 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1374 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1375 [(set F4RC:$FRT, 1376 (fneg (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB)))]>; 1377 def FNMSUB : AForm_1<63, 30, 1378 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1379 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1380 [(set F8RC:$FRT, (fneg (fma F8RC:$FRA, F8RC:$FRC, 1381 (fneg F8RC:$FRB))))]>; 1382 def FNMSUBS : AForm_1<59, 30, 1383 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1384 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1385 [(set F4RC:$FRT, (fneg (fma F4RC:$FRA, F4RC:$FRC, 1386 (fneg F4RC:$FRB))))]>; 1387} 1388// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 1389// having 4 of these, force the comparison to always be an 8-byte double (code 1390// should use an FMRSD if the input comparison value really wants to be a float) 1391// and 4/8 byte forms for the result and operand type.. 1392def FSELD : AForm_1<63, 23, 1393 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1394 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1395 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 1396def FSELS : AForm_1<63, 23, 1397 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1398 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1399 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 1400let Uses = [RM] in { 1401 def FADD : AForm_2<63, 21, 1402 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1403 "fadd $FRT, $FRA, $FRB", FPAddSub, 1404 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 1405 def FADDS : AForm_2<59, 21, 1406 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1407 "fadds $FRT, $FRA, $FRB", FPGeneral, 1408 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 1409 def FDIV : AForm_2<63, 18, 1410 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1411 "fdiv $FRT, $FRA, $FRB", FPDivD, 1412 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 1413 def FDIVS : AForm_2<59, 18, 1414 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1415 "fdivs $FRT, $FRA, $FRB", FPDivS, 1416 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 1417 def FMUL : AForm_3<63, 25, 1418 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC), 1419 "fmul $FRT, $FRA, $FRC", FPFused, 1420 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRC))]>; 1421 def FMULS : AForm_3<59, 25, 1422 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC), 1423 "fmuls $FRT, $FRA, $FRC", FPGeneral, 1424 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRC))]>; 1425 def FSUB : AForm_2<63, 20, 1426 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1427 "fsub $FRT, $FRA, $FRB", FPAddSub, 1428 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 1429 def FSUBS : AForm_2<59, 20, 1430 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1431 "fsubs $FRT, $FRA, $FRB", FPGeneral, 1432 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 1433 } 1434} 1435 1436let PPC970_Unit = 1 in { // FXU Operations. 1437 def ISEL : AForm_4<31, 15, 1438 (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB, pred:$cond), 1439 "isel $rT, $rA, $rB, $cond", IntGeneral, 1440 []>; 1441} 1442 1443let PPC970_Unit = 1 in { // FXU Operations. 1444// M-Form instructions. rotate and mask instructions. 1445// 1446let isCommutable = 1 in { 1447// RLWIMI can be commuted if the rotate amount is zero. 1448def RLWIMI : MForm_2<20, 1449 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 1450 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 1451 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 1452 NoEncode<"$rSi">; 1453} 1454def RLWINM : MForm_2<21, 1455 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1456 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 1457 []>; 1458def RLWINMo : MForm_2<21, 1459 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1460 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 1461 []>, isDOT, PPC970_DGroup_Cracked; 1462def RLWNM : MForm_2<23, 1463 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 1464 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 1465 []>; 1466} 1467 1468 1469//===----------------------------------------------------------------------===// 1470// PowerPC Instruction Patterns 1471// 1472 1473// Arbitrary immediate support. Implement in terms of LIS/ORI. 1474def : Pat<(i32 imm:$imm), 1475 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1476 1477// Implement the 'not' operation with the NOR instruction. 1478def NOT : Pat<(not GPRC:$in), 1479 (NOR GPRC:$in, GPRC:$in)>; 1480 1481// ADD an arbitrary immediate. 1482def : Pat<(add GPRC:$in, imm:$imm), 1483 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1484// OR an arbitrary immediate. 1485def : Pat<(or GPRC:$in, imm:$imm), 1486 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1487// XOR an arbitrary immediate. 1488def : Pat<(xor GPRC:$in, imm:$imm), 1489 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1490// SUBFIC 1491def : Pat<(sub immSExt16:$imm, GPRC:$in), 1492 (SUBFIC GPRC:$in, imm:$imm)>; 1493 1494// SHL/SRL 1495def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1496 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1497def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1498 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1499 1500// ROTL 1501def : Pat<(rotl GPRC:$in, GPRC:$sh), 1502 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1503def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1504 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1505 1506// RLWNM 1507def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm), 1508 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 1509 1510// Calls 1511def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)), 1512 (BL_Darwin tglobaladdr:$dst)>; 1513def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)), 1514 (BL_Darwin texternalsym:$dst)>; 1515def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)), 1516 (BL_SVR4 tglobaladdr:$dst)>; 1517def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)), 1518 (BL_SVR4 texternalsym:$dst)>; 1519 1520 1521def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 1522 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 1523 1524def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 1525 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 1526 1527def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 1528 (TCRETURNri CTRRC:$dst, imm:$imm)>; 1529 1530 1531 1532// Hi and Lo for Darwin Global Addresses. 1533def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1534def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1535def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1536def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1537def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1538def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1539def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 1540def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 1541def : Pat<(PPChi tglobaltlsaddr:$g, GPRC:$in), 1542 (ADDIS GPRC:$in, tglobaltlsaddr:$g)>; 1543def : Pat<(PPClo tglobaltlsaddr:$g, GPRC:$in), 1544 (ADDIL GPRC:$in, tglobaltlsaddr:$g)>; 1545def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1546 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1547def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1548 (ADDIS GPRC:$in, tconstpool:$g)>; 1549def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 1550 (ADDIS GPRC:$in, tjumptable:$g)>; 1551def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)), 1552 (ADDIS GPRC:$in, tblockaddress:$g)>; 1553 1554// Standard shifts. These are represented separately from the real shifts above 1555// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1556// amounts. 1557def : Pat<(sra GPRC:$rS, GPRC:$rB), 1558 (SRAW GPRC:$rS, GPRC:$rB)>; 1559def : Pat<(srl GPRC:$rS, GPRC:$rB), 1560 (SRW GPRC:$rS, GPRC:$rB)>; 1561def : Pat<(shl GPRC:$rS, GPRC:$rB), 1562 (SLW GPRC:$rS, GPRC:$rB)>; 1563 1564def : Pat<(zextloadi1 iaddr:$src), 1565 (LBZ iaddr:$src)>; 1566def : Pat<(zextloadi1 xaddr:$src), 1567 (LBZX xaddr:$src)>; 1568def : Pat<(extloadi1 iaddr:$src), 1569 (LBZ iaddr:$src)>; 1570def : Pat<(extloadi1 xaddr:$src), 1571 (LBZX xaddr:$src)>; 1572def : Pat<(extloadi8 iaddr:$src), 1573 (LBZ iaddr:$src)>; 1574def : Pat<(extloadi8 xaddr:$src), 1575 (LBZX xaddr:$src)>; 1576def : Pat<(extloadi16 iaddr:$src), 1577 (LHZ iaddr:$src)>; 1578def : Pat<(extloadi16 xaddr:$src), 1579 (LHZX xaddr:$src)>; 1580def : Pat<(f64 (extloadf32 iaddr:$src)), 1581 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 1582def : Pat<(f64 (extloadf32 xaddr:$src)), 1583 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 1584 1585def : Pat<(f64 (fextend F4RC:$src)), 1586 (COPY_TO_REGCLASS F4RC:$src, F8RC)>; 1587 1588// Memory barriers 1589def : Pat<(membarrier (i32 imm /*ll*/), 1590 (i32 imm /*ls*/), 1591 (i32 imm /*sl*/), 1592 (i32 imm /*ss*/), 1593 (i32 imm /*device*/)), 1594 (SYNC)>; 1595 1596def : Pat<(atomic_fence (imm), (imm)), (SYNC)>; 1597 1598include "PPCInstrAltivec.td" 1599include "PPCInstr64Bit.td" 1600