PPCInstrInfo.td revision 145a5a374631449bd0d483c036a3390150b7dc86
1//===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PowerPCInstrFormats.td" 16 17let isTerminator = 1 in { 18 let isReturn = 1 in 19 def BLR : XLForm_2_ext<19, 16, 20, 31, 1, 0, 0, (ops), "blr">; 20 def BCTR : XLForm_2_ext<19, 528, 20, 31, 1, 0, 0, (ops), "bctr">; 21} 22 23def u5imm : Operand<i8> { 24 let PrintMethod = "printU5ImmOperand"; 25} 26def u6imm : Operand<i8> { 27 let PrintMethod = "printU6ImmOperand"; 28} 29def s16imm : Operand<i16> { 30 let PrintMethod = "printS16ImmOperand"; 31} 32def u16imm : Operand<i16> { 33 let PrintMethod = "printU16ImmOperand"; 34} 35def target : Operand<i32> { 36 let PrintMethod = "printBranchOperand"; 37} 38def piclabel: Operand<i32> { 39 let PrintMethod = "printPICLabel"; 40} 41def symbolHi: Operand<i32> { 42 let PrintMethod = "printSymbolHi"; 43} 44def symbolLo: Operand<i32> { 45 let PrintMethod = "printSymbolLo"; 46} 47 48// Pseudo-instructions: 49def PHI : Pseudo<(ops), "; PHI">; 50let isLoad = 1 in { 51def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">; 52def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">; 53} 54def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">; 55def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">; 56 57let isBranch = 1, isTerminator = 1 in { 58 def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">; 59 def B : IForm<18, 0, 0, 0, 0, (ops target:$func), "b $func">; 60 def BA : IForm<18, 1, 0, 0, 0, (ops target:$func), "ba $func">; 61 def BL : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">; 62 def BLA : IForm<18, 1, 1, 0, 0, (ops target:$func), "bla $func">; 63 // FIXME: 4*CR# needs to be added to the BI field! 64 // This will only work for CR0 as it stands now 65 def BLT : BForm_ext<16, 0, 0, 12, 0, 0, 0, (ops CRRC:$crS, target:$block), 66 "blt $block">; 67 def BLE : BForm_ext<16, 0, 0, 4, 1, 0, 0, (ops CRRC:$crS, target:$block), 68 "ble $block">; 69 def BEQ : BForm_ext<16, 0, 0, 12, 2, 0, 0, (ops CRRC:$crS, target:$block), 70 "beq $block">; 71 def BGE : BForm_ext<16, 0, 0, 4, 0, 0, 0, (ops CRRC:$crS, target:$block), 72 "bge $block">; 73 def BGT : BForm_ext<16, 0, 0, 12, 1, 0, 0, (ops CRRC:$crS, target:$block), 74 "bgt $block">; 75 def BNE : BForm_ext<16, 0, 0, 4, 2, 0, 0, (ops CRRC:$crS, target:$block), 76 "bne $block">; 77} 78 79let isBranch = 1, isTerminator = 1, isCall = 1, 80 // All calls clobber the non-callee saved registers... 81 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 82 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 83 LR,XER,CTR, 84 CR0,CR1,CR5,CR6,CR7] in { 85 // Convenient aliases for call instructions 86 def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">; 87 def CALLindirect : XLForm_2_ext<19, 528, 20, 31, 1, 0, 0, (ops), "bctrl">; 88} 89 90// D-Form instructions. Most instructions that perform an operation on a 91// register and an immediate are of this type. 92// 93let isLoad = 1 in { 94def LBZ : DForm_1<35, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA), 95 "lbz $rD, $disp($rA)">; 96def LHA : DForm_1<42, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA), 97 "lha $rD, $disp($rA)">; 98def LHZ : DForm_1<40, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA), 99 "lhz $rD, $disp($rA)">; 100def LMW : DForm_1<46, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA), 101 "lmw $rD, $disp($rA)">; 102def LWZ : DForm_1<32, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA), 103 "lwz $rD, $disp($rA)">; 104def LWZU : DForm_1<33, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA), 105 "lwzu $rD, $disp($rA)">; 106} 107def ADDI : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 108 "addi $rD, $rA, $imm">; 109def ADDIC : DForm_2<12, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 110 "addic $rD, $rA, $imm">; 111def ADDICo : DForm_2<13, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 112 "addic. $rD, $rA, $imm">; 113def ADDIS : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 114 "addis $rD, $rA, $imm">; 115def LA : DForm_2<14, 0, 0, (ops GPRC:$rD, symbolLo:$sym, GPRC:$rA), 116 "la $rD, $sym($rA)">; 117def LOADHiAddr : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym), 118 "addis $rD, $rA, $sym">; 119def MULLI : DForm_2< 7, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 120 "mulli $rD, $rA, $imm">; 121def SUBFIC : DForm_2< 8, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 122 "subfic $rD, $rA, $imm">; 123def LI : DForm_2_r0<14, 0, 0, (ops GPRC:$rD, s16imm:$imm), 124 "li $rD, $imm">; 125def LIS : DForm_2_r0<15, 0, 0, (ops GPRC:$rD, s16imm:$imm), 126 "lis $rD, $imm">; 127let isStore = 1 in { 128def STMW : DForm_3<47, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 129 "stmw $rS, $disp($rA)">; 130def STB : DForm_3<38, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 131 "stb $rS, $disp($rA)">; 132def STBU : DForm_3<39, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 133 "stbu $rS, $disp($rA)">; 134def STH : DForm_3<44, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 135 "sth $rS, $disp($rA)">; 136def STHU : DForm_3<45, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 137 "sthu $rS, $disp($rA)">; 138def STW : DForm_3<36, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 139 "stw $rS, $disp($rA)">; 140def STWU : DForm_3<37, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 141 "stwu $rS, $disp($rA)">; 142} 143def ANDIo : DForm_4<28, 0, 0, 144 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 145 "andi. $dst, $src1, $src2">; 146def ANDISo : DForm_4<29, 0, 0, 147 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 148 "andis. $dst, $src1, $src2">; 149def ORI : DForm_4<24, 0, 0, 150 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 151 "ori $dst, $src1, $src2">; 152def ORIS : DForm_4<25, 0, 0, 153 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 154 "oris $dst, $src1, $src2">; 155def XORI : DForm_4<26, 0, 0, 156 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 157 "xori $dst, $src1, $src2">; 158def XORIS : DForm_4<27, 0, 0, 159 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 160 "xoris $dst, $src1, $src2">; 161def NOP : DForm_4_zero<24, 0, 0, (ops), "nop">; 162def CMPI : DForm_5<11, 0, 0, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm), 163 "cmpi $crD, $L, $rA, $imm">; 164def CMPWI : DForm_5_ext<11, 0, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 165 "cmpwi $crD, $rA, $imm">; 166def CMPDI : DForm_5_ext<11, 1, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 167 "cmpdi $crD, $rA, $imm">; 168def CMPLI : DForm_6<10, 0, 0, 169 (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2), 170 "cmpli $dst, $size, $src1, $src2">; 171def CMPLWI : DForm_6_ext<10, 0, 0, 172 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 173 "cmplwi $dst, $src1, $src2">; 174def CMPLDI : DForm_6_ext<10, 1, 0, 175 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 176 "cmpldi $dst, $src1, $src2">; 177let isLoad = 1 in { 178def LFS : DForm_8<48, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA), 179 "lfs $rD, $disp($rA)">; 180def LFD : DForm_8<50, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA), 181 "lfd $rD, $disp($rA)">; 182} 183let isStore = 1 in { 184def STFS : DForm_9<52, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 185 "stfs $rS, $disp($rA)">; 186def STFD : DForm_9<54, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 187 "stfd $rS, $disp($rA)">; 188} 189 190// DS-Form instructions. Load/Store instructions available in PPC-64 191// 192let isLoad = 1 in { 193def LWA : DSForm_1<58, 2, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA), 194 "lwa $rT, $DS($rA)">; 195def LD : DSForm_2<58, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA), 196 "ld $rT, $DS($rA)">; 197} 198let isStore = 1 in { 199def STD : DSForm_2<62, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA), 200 "std $rT, $DS($rA)">; 201def STDU : DSForm_2<62, 1, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA), 202 "stdu $rT, $DS($rA)">; 203} 204 205// X-Form instructions. Most instructions that perform an operation on a 206// register and another register are of this type. 207// 208let isLoad = 1 in { 209def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index), 210 "lbzx $dst, $base, $index">; 211def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index), 212 "lhax $dst, $base, $index">; 213def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index), 214 "lhzx $dst, $base, $index">; 215def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index), 216 "lwax $dst, $base, $index">; 217def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index), 218 "lwzx $dst, $base, $index">; 219def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index), 220 "ldx $dst, $base, $index">; 221} 222def MFCR : XForm_5<31, 19, 0, 0, (ops GPRC:$dst), "mfcr $dst">; 223def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 224 "and $rA, $rS, $rB">; 225def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 226 "andc $rA, $rS, $rB">; 227def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 228 "eqv $rA, $rS, $rB">; 229def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 230 "nand $rA, $rS, $rB">; 231def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 232 "nor $rA, $rS, $rB">; 233def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 234 "or $rA, $rS, $rB">; 235def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 236 "or. $rA, $rS, $rB">; 237def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 238 "orc $rA, $rS, $rB">; 239def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 240 "sld $rA, $rS, $rB">; 241def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 242 "slw $rA, $rS, $rB">; 243def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 244 "srd $rA, $rS, $rB">; 245def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 246 "srw $rA, $rS, $rB">; 247def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 248 "srad $rA, $rS, $rB">; 249def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 250 "sraw $rA, $rS, $rB">; 251def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 252 "xor $rA, $rS, $rB">; 253let isStore = 1 in { 254def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 255 "stbx $rS, $rA, $rB">; 256def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 257 "sthx $rS, $rA, $rB">; 258def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 259 "stwx $rS, $rA, $rB">; 260def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 261 "stwux $rS, $rA, $rB">; 262def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 263 "stdx $rS, $rA, $rB">; 264def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 265 "stdux $rS, $rA, $rB">; 266} 267def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), 268 "srawi $rA, $rS, $SH">; 269def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS), 270 "cntlzw $rA, $rS">; 271def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS), 272 "extsb $rA, $rS">; 273def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS), 274 "extsh $rA, $rS">; 275def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS), 276 "extsw $rA, $rS">; 277def CMP : XForm_16<31, 0, 0, 0, 278 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB), 279 "cmp $crD, $long, $rA, $rB">; 280def CMPL : XForm_16<31, 32, 0, 0, 281 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB), 282 "cmpl $crD, $long, $rA, $rB">; 283def CMPW : XForm_16_ext<31, 0, 0, 0, 284 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 285 "cmpw $crD, $rA, $rB">; 286def CMPD : XForm_16_ext<31, 0, 1, 0, 287 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 288 "cmpd $crD, $rA, $rB">; 289def CMPLW : XForm_16_ext<31, 32, 0, 0, 290 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 291 "cmplw $crD, $rA, $rB">; 292def CMPLD : XForm_16_ext<31, 32, 1, 0, 293 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 294 "cmpld $crD, $rA, $rB">; 295def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB), 296 "fcmpu $crD, $fA, $fB">; 297let isLoad = 1 in { 298def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index), 299 "lfsx $dst, $base, $index">; 300def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index), 301 "lfdx $dst, $base, $index">; 302} 303def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB), 304 "fcfid $frD, $frB">; 305def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB), 306 "fctidz $frD, $frB">; 307def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB), 308 "fctiwz $frD, $frB">; 309def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB), 310 "fmr $frD, $frB">; 311def FNEG : XForm_26<63, 80, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB), 312 "fneg $frD, $frB">; 313def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB), 314 "frsp $frD, $frB">; 315let isStore = 1 in { 316def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB), 317 "stfsx $frS, $rA, $rB">; 318def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB), 319 "stfdx $frS, $rA, $rB">; 320} 321 322// XL-Form instructions. condition register logical ops. 323// 324def CRAND : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B), 325 "crand $D, $A, $B">; 326def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B), 327 "crandc $D, $A, $B">; 328def CRNOR : XLForm_1<19, 33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B), 329 "crnor $D, $A, $B">; 330def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B), 331 "cror $D, $A, $B">; 332 333// XFX-Form instructions. Instructions that deal with SPRs 334// 335// Note that although LR should be listed as `8' and CTR as `9' in the SPR 336// field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9 337// which means the SPR value needs to be multiplied by a factor of 32. 338def MFCTR : XFXForm_1_ext<31, 339, 288, 0, 0, (ops GPRC:$rT), "mfctr $rT">; 339def MFLR : XFXForm_1_ext<31, 339, 256, 0, 0, (ops GPRC:$rT), "mflr $rT">; 340def MTCTR : XFXForm_7_ext<31, 467, 288, 0, 0, (ops GPRC:$rS), "mtctr $rS">; 341def MTLR : XFXForm_7_ext<31, 467, 256, 0, 0, (ops GPRC:$rS), "mtlr $rS">; 342 343 344// XS-Form instructions. Just 'sradi' 345// 346def SRADI : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH), 347 "sradi $rA, $rS, $SH">; 348 349// XO-Form instructions. Arithmetic instructions that can set overflow bit 350// 351def ADD : XOForm_1<31, 266, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 352 "add $rT, $rA, $rB">; 353def ADDC : XOForm_1<31, 10, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 354 "addc $rT, $rA, $rB">; 355def ADDE : XOForm_1<31, 138, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 356 "adde $rT, $rA, $rB">; 357def DIVD : XOForm_1<31, 489, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 358 "divd $rT, $rA, $rB">; 359def DIVDU : XOForm_1<31, 457, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 360 "divdu $rT, $rA, $rB">; 361def DIVW : XOForm_1<31, 491, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 362 "divw $rT, $rA, $rB">; 363def DIVWU : XOForm_1<31, 459, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 364 "divwu $rT, $rA, $rB">; 365def MULHWU : XOForm_1<31, 11, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 366 "mulhwu $rT, $rA, $rB">; 367def MULLD : XOForm_1<31, 233, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 368 "mulld $rT, $rA, $rB">; 369def MULLW : XOForm_1<31, 235, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 370 "mullw $rT, $rA, $rB">; 371def SUBF : XOForm_1<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 372 "subf $rT, $rA, $rB">; 373def SUBFC : XOForm_1<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 374 "subfc $rT, $rA, $rB">; 375def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 376 "subfe $rT, $rA, $rB">; 377def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 378 "sub $rT, $rA, $rB">; 379def SUBC : XOForm_1r<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 380 "subc $rT, $rA, $rB">; 381def ADDME : XOForm_3<31, 234, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA), 382 "addme $rT, $rA">; 383def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA), 384 "addze $rT, $rA">; 385def NEG : XOForm_3<31, 104, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA), 386 "neg $rT, $rA">; 387def SUBFZE : XOForm_3<31, 200, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA), 388 "subfze $rT, $rA">; 389 390// A-Form instructions. Most of the instructions executed in the FPU are of 391// this type. 392// 393def FMADD : AForm_1<63, 29, 0, 0, 0, 394 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB), 395 "fmadd $FRT, $FRA, $FRC, $FRB">; 396def FSEL : AForm_1<63, 23, 0, 0, 0, 397 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB), 398 "fsel $FRT, $FRA, $FRC, $FRB">; 399def FADD : AForm_2<63, 21, 0, 0, 0, 400 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB), 401 "fadd $FRT, $FRA, $FRB">; 402def FADDS : AForm_2<59, 21, 0, 0, 0, 403 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB), 404 "fadds $FRT, $FRA, $FRB">; 405def FDIV : AForm_2<63, 18, 0, 0, 0, 406 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB), 407 "fdiv $FRT, $FRA, $FRB">; 408def FDIVS : AForm_2<59, 18, 0, 0, 0, 409 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB), 410 "fdivs $FRT, $FRA, $FRB">; 411def FMUL : AForm_3<63, 25, 0, 0, 0, 412 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB), 413 "fmul $FRT, $FRA, $FRB">; 414def FMULS : AForm_3<59, 25, 0, 0, 0, 415 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB), 416 "fmuls $FRT, $FRA, $FRB">; 417def FSUB : AForm_2<63, 20, 0, 0, 0, 418 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB), 419 "fsub $FRT, $FRA, $FRB">; 420def FSUBS : AForm_2<59, 20, 0, 0, 0, 421 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB), 422 "fsubs $FRT, $FRA, $FRB">; 423 424// M-Form instructions. rotate and mask instructions. 425// 426let isTwoAddress = 1 in { 427def RLWIMI : MForm_2<20, 0, 0, 0, 428 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 429 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">; 430} 431def RLWINM : MForm_2<21, 0, 0, 0, 432 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 433 "rlwinm $rA, $rS, $SH, $MB, $ME">; 434 435 436// MD-Form instructions. 64 bit rotate instructions. 437// 438def RLDICL : MDForm_1<30, 0, 0, 1, 0, 439 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB), 440 "rldicl $rA, $rS, $SH, $MB">; 441def RLDICR : MDForm_1<30, 1, 0, 1, 0, 442 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME), 443 "rldicr $rA, $rS, $SH, $ME">; 444 445 446