PPCInstrInfo.td revision 35ef913ec21de0f4f1b39c811b4335438717a9b8
1//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific DAG Nodes. 19// 20 21def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 22def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 23def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 24 25def PPCfsel : SDNode<"PPCISD::FSEL", 26 // Type constraint for fsel. 27 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 28 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 29 30def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 31def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 32def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 33def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 34 35// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 36// amounts. These nodes are generated by the multi-precision shift code. 37def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl 38 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32> 39]>; 40def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>; 41def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>; 42def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>; 43 44// These are target-independent nodes, but have target-specific formats. 45def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 46def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>; 47def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>; 48 49def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>; 50def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag, 51 [SDNPHasChain, SDNPOptInFlag]>; 52 53//===----------------------------------------------------------------------===// 54// PowerPC specific transformation functions and pattern fragments. 55// 56 57def SHL32 : SDNodeXForm<imm, [{ 58 // Transformation function: 31 - imm 59 return getI32Imm(31 - N->getValue()); 60}]>; 61 62def SHL64 : SDNodeXForm<imm, [{ 63 // Transformation function: 63 - imm 64 return getI32Imm(63 - N->getValue()); 65}]>; 66 67def SRL32 : SDNodeXForm<imm, [{ 68 // Transformation function: 32 - imm 69 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0); 70}]>; 71 72def SRL64 : SDNodeXForm<imm, [{ 73 // Transformation function: 64 - imm 74 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0); 75}]>; 76 77def LO16 : SDNodeXForm<imm, [{ 78 // Transformation function: get the low 16 bits. 79 return getI32Imm((unsigned short)N->getValue()); 80}]>; 81 82def HI16 : SDNodeXForm<imm, [{ 83 // Transformation function: shift the immediate value down into the low bits. 84 return getI32Imm((unsigned)N->getValue() >> 16); 85}]>; 86 87def HA16 : SDNodeXForm<imm, [{ 88 // Transformation function: shift the immediate value down into the low bits. 89 signed int Val = N->getValue(); 90 return getI32Imm((Val - (signed short)Val) >> 16); 91}]>; 92 93 94def immSExt16 : PatLeaf<(imm), [{ 95 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 96 // field. Used by instructions like 'addi'. 97 return (int)N->getValue() == (short)N->getValue(); 98}]>; 99def immZExt16 : PatLeaf<(imm), [{ 100 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 101 // field. Used by instructions like 'ori'. 102 return (unsigned)N->getValue() == (unsigned short)N->getValue(); 103}], LO16>; 104 105def imm16Shifted : PatLeaf<(imm), [{ 106 // imm16Shifted predicate - True if only bits in the top 16-bits of the 107 // immediate are set. Used by instructions like 'addis'. 108 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue(); 109}], HI16>; 110 111/* 112// Example of a legalize expander: Only for PPC64. 113def : Expander<(set i64:$dst, (fp_to_sint f64:$src)), 114 [(set f64:$tmp , (FCTIDZ f64:$src)), 115 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)), 116 (store f64:$tmp, i32:$tmpFI), 117 (set i64:$dst, (load i32:$tmpFI))], 118 Subtarget_PPC64>; 119*/ 120 121//===----------------------------------------------------------------------===// 122// PowerPC Flag Definitions. 123 124class isPPC64 { bit PPC64 = 1; } 125class isVMX { bit VMX = 1; } 126class isDOT { 127 list<Register> Defs = [CR0]; 128 bit RC = 1; 129} 130 131 132 133//===----------------------------------------------------------------------===// 134// PowerPC Operand Definitions. 135 136def u5imm : Operand<i32> { 137 let PrintMethod = "printU5ImmOperand"; 138} 139def u6imm : Operand<i32> { 140 let PrintMethod = "printU6ImmOperand"; 141} 142def s16imm : Operand<i32> { 143 let PrintMethod = "printS16ImmOperand"; 144} 145def u16imm : Operand<i32> { 146 let PrintMethod = "printU16ImmOperand"; 147} 148def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 149 let PrintMethod = "printS16X4ImmOperand"; 150} 151def target : Operand<OtherVT> { 152 let PrintMethod = "printBranchOperand"; 153} 154def calltarget : Operand<i32> { 155 let PrintMethod = "printCallOperand"; 156} 157def aaddr : Operand<i32> { 158 let PrintMethod = "printAbsAddrOperand"; 159} 160def piclabel: Operand<i32> { 161 let PrintMethod = "printPICLabel"; 162} 163def symbolHi: Operand<i32> { 164 let PrintMethod = "printSymbolHi"; 165} 166def symbolLo: Operand<i32> { 167 let PrintMethod = "printSymbolLo"; 168} 169def crbitm: Operand<i8> { 170 let PrintMethod = "printcrbitm"; 171} 172// Address operands 173def memri : Operand<i32> { 174 let PrintMethod = "printMemRegImm"; 175 let NumMIOperands = 2; 176 let MIOperandInfo = (ops i32imm, GPRC); 177} 178def memrr : Operand<i32> { 179 let PrintMethod = "printMemRegReg"; 180 let NumMIOperands = 2; 181 let MIOperandInfo = (ops GPRC, GPRC); 182} 183 184// Define X86 specific addressing mode. 185def iaddr : ComplexPattern<i32, 2, "SelectAddrImm", []>; 186def xaddr : ComplexPattern<i32, 2, "SelectAddrIdx", []>; 187def xoaddr : ComplexPattern<i32, 2, "SelectAddrIdxOnly",[]>; 188 189//===----------------------------------------------------------------------===// 190// PowerPC Instruction Predicate Definitions. 191def FPContractions : Predicate<"!NoExcessFPPrecision">; 192 193//===----------------------------------------------------------------------===// 194// PowerPC Instruction Definitions. 195 196// Pseudo-instructions: 197def PHI : Pseudo<(ops variable_ops), "; PHI", []>; 198 199let isLoad = 1, hasCtrlDep = 1 in { 200def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), 201 "; ADJCALLSTACKDOWN", 202 [(callseq_start imm:$amt)]>; 203def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), 204 "; ADJCALLSTACKUP", 205 [(callseq_end imm:$amt)]>; 206} 207def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC", 208 [(set GPRC:$rD, (undef))]>; 209def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8", 210 [(set F8RC:$rD, (undef))]>; 211def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4", 212 [(set F4RC:$rD, (undef))]>; 213 214// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 215// scheduler into a branch sequence. 216let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 217 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F, 218 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>; 219 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F, 220 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>; 221 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F, 222 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>; 223} 224 225 226let isTerminator = 1, noResults = 1 in { 227 let isReturn = 1 in 228 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>; 229 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>; 230} 231 232let Defs = [LR] in 233 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>; 234 235let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in { 236 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, 237 target:$true, target:$false), 238 "; COND_BRANCH", []>; 239 def B : IForm<18, 0, 0, (ops target:$dst), 240 "b $dst", BrB, 241 [(br bb:$dst)]>; 242 243 // FIXME: 4*CR# needs to be added to the BI field! 244 // This will only work for CR0 as it stands now 245 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block), 246 "blt $crS, $block", BrB>; 247 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block), 248 "ble $crS, $block", BrB>; 249 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block), 250 "beq $crS, $block", BrB>; 251 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block), 252 "bge $crS, $block", BrB>; 253 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block), 254 "bgt $crS, $block", BrB>; 255 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block), 256 "bne $crS, $block", BrB>; 257 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block), 258 "bun $crS, $block", BrB>; 259 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block), 260 "bnu $crS, $block", BrB>; 261} 262 263let isCall = 1, noResults = 1, 264 // All calls clobber the non-callee saved registers... 265 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 266 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 267 LR,CTR, 268 CR0,CR1,CR5,CR6,CR7] in { 269 // Convenient aliases for call instructions 270 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops), 271 "bl $func", BrB, []>; 272 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), 273 "bla $func", BrB, []>; 274 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB, 275 []>; 276} 277 278// D-Form instructions. Most instructions that perform an operation on a 279// register and an immediate are of this type. 280// 281let isLoad = 1 in { 282def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src), 283 "lbz $rD, $src", LdStGeneral, 284 [(set GPRC:$rD, (zextload iaddr:$src, i8))]>; 285def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src), 286 "lha $rD, $src", LdStLHA, 287 [(set GPRC:$rD, (sextload iaddr:$src, i16))]>; 288def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src), 289 "lhz $rD, $src", LdStGeneral, 290 [(set GPRC:$rD, (zextload iaddr:$src, i16))]>; 291def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA), 292 "lmw $rD, $disp($rA)", LdStLMW, 293 []>; 294def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src), 295 "lwz $rD, $src", LdStGeneral, 296 [(set GPRC:$rD, (load iaddr:$src))]>; 297def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA), 298 "lwzu $rD, $disp($rA)", LdStGeneral, 299 []>; 300} 301def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 302 "addi $rD, $rA, $imm", IntGeneral, 303 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 304def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 305 "addic $rD, $rA, $imm", IntGeneral, 306 []>; 307def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 308 "addic. $rD, $rA, $imm", IntGeneral, 309 []>; 310def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm), 311 "addis $rD, $rA, $imm", IntGeneral, 312 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>; 313def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym), 314 "la $rD, $sym($rA)", IntGeneral, 315 [(set GPRC:$rD, (add GPRC:$rA, 316 (PPClo tglobaladdr:$sym, 0)))]>; 317def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 318 "mulli $rD, $rA, $imm", IntMulLI, 319 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 320def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 321 "subfic $rD, $rA, $imm", IntGeneral, 322 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>; 323def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm), 324 "li $rD, $imm", IntGeneral, 325 [(set GPRC:$rD, immSExt16:$imm)]>; 326def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm), 327 "lis $rD, $imm", IntGeneral, 328 [(set GPRC:$rD, imm16Shifted:$imm)]>; 329let isStore = 1, noResults = 1 in { 330def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 331 "stmw $rS, $disp($rA)", LdStLMW, 332 []>; 333def STB : DForm_3<38, (ops GPRC:$rS, memri:$src), 334 "stb $rS, $src", LdStGeneral, 335 [(truncstore GPRC:$rS, iaddr:$src, i8)]>; 336def STH : DForm_3<44, (ops GPRC:$rS, memri:$src), 337 "sth $rS, $src", LdStGeneral, 338 [(truncstore GPRC:$rS, iaddr:$src, i16)]>; 339def STW : DForm_3<36, (ops GPRC:$rS, memri:$src), 340 "stw $rS, $src", LdStGeneral, 341 [(store GPRC:$rS, iaddr:$src)]>; 342def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 343 "stwu $rS, $disp($rA)", LdStGeneral, 344 []>; 345} 346def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 347 "andi. $dst, $src1, $src2", IntGeneral, 348 []>, isDOT; 349def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 350 "andis. $dst, $src1, $src2", IntGeneral, 351 []>, isDOT; 352def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 353 "ori $dst, $src1, $src2", IntGeneral, 354 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 355def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 356 "oris $dst, $src1, $src2", IntGeneral, 357 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>; 358def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 359 "xori $dst, $src1, $src2", IntGeneral, 360 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 361def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 362 "xoris $dst, $src1, $src2", IntGeneral, 363 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>; 364def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral, 365 []>; 366def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm), 367 "cmpi $crD, $L, $rA, $imm", IntCompare>; 368def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 369 "cmpwi $crD, $rA, $imm", IntCompare>; 370def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 371 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 372def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2), 373 "cmpli $dst, $size, $src1, $src2", IntCompare>; 374def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 375 "cmplwi $dst, $src1, $src2", IntCompare>; 376def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 377 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 378let isLoad = 1 in { 379def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src), 380 "lfs $rD, $src", LdStLFDU, 381 [(set F4RC:$rD, (load iaddr:$src))]>; 382def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src), 383 "lfd $rD, $src", LdStLFD, 384 [(set F8RC:$rD, (load iaddr:$src))]>; 385} 386let isStore = 1, noResults = 1 in { 387def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst), 388 "stfs $rS, $dst", LdStUX, 389 [(store F4RC:$rS, iaddr:$dst)]>; 390def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst), 391 "stfd $rS, $dst", LdStUX, 392 [(store F8RC:$rS, iaddr:$dst)]>; 393} 394 395// DS-Form instructions. Load/Store instructions available in PPC-64 396// 397let isLoad = 1 in { 398def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 399 "lwa $rT, $DS($rA)", LdStLWA, 400 []>, isPPC64; 401def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 402 "ld $rT, $DS($rA)", LdStLD, 403 []>, isPPC64; 404} 405let isStore = 1, noResults = 1 in { 406def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 407 "std $rT, $DS($rA)", LdStSTD, 408 []>, isPPC64; 409def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 410 "stdu $rT, $DS($rA)", LdStSTD, 411 []>, isPPC64; 412} 413 414// X-Form instructions. Most instructions that perform an operation on a 415// register and another register are of this type. 416// 417let isLoad = 1 in { 418def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src), 419 "lbzx $rD, $src", LdStGeneral, 420 [(set GPRC:$rD, (zextload xaddr:$src, i8))]>; 421def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src), 422 "lhax $rD, $src", LdStLHA, 423 [(set GPRC:$rD, (sextload xaddr:$src, i16))]>; 424def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src), 425 "lhzx $rD, $src", LdStGeneral, 426 [(set GPRC:$rD, (zextload xaddr:$src, i16))]>; 427def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src), 428 "lwax $rD, $src", LdStLHA, 429 [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64; 430def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src), 431 "lwzx $rD, $src", LdStGeneral, 432 [(set GPRC:$rD, (load xaddr:$src))]>; 433def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src), 434 "ldx $rD, $src", LdStLD, 435 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 436def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), 437 "lvebx $vD, $base, $rA", LdStGeneral, 438 []>; 439def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), 440 "lvehx $vD, $base, $rA", LdStGeneral, 441 []>; 442def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), 443 "lvewx $vD, $base, $rA", LdStGeneral, 444 []>; 445def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src), 446 "lvx $vD, $src", LdStGeneral, 447 [(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>; 448} 449def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), 450 "lvsl $vD, $base, $rA", LdStGeneral, 451 []>; 452def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), 453 "lvsl $vD, $base, $rA", LdStGeneral, 454 []>; 455def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 456 "nand $rA, $rS, $rB", IntGeneral, 457 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 458def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 459 "and $rA, $rS, $rB", IntGeneral, 460 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 461def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 462 "and. $rA, $rS, $rB", IntGeneral, 463 []>, isDOT; 464def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 465 "andc $rA, $rS, $rB", IntGeneral, 466 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 467def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 468 "or $rA, $rS, $rB", IntGeneral, 469 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 470def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 471 "or $rA, $rS, $rB", IntGeneral, 472 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 473def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB), 474 "or $rA, $rS, $rB", IntGeneral, 475 []>; 476def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB), 477 "or $rA, $rS, $rB", IntGeneral, 478 []>; 479def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 480 "nor $rA, $rS, $rB", IntGeneral, 481 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 482def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 483 "or. $rA, $rS, $rB", IntGeneral, 484 []>, isDOT; 485def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 486 "orc $rA, $rS, $rB", IntGeneral, 487 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 488def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 489 "eqv $rA, $rS, $rB", IntGeneral, 490 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 491def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 492 "xor $rA, $rS, $rB", IntGeneral, 493 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 494def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 495 "sld $rA, $rS, $rB", IntRotateD, 496 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64; 497def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 498 "slw $rA, $rS, $rB", IntGeneral, 499 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 500def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 501 "srd $rA, $rS, $rB", IntRotateD, 502 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64; 503def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 504 "srw $rA, $rS, $rB", IntGeneral, 505 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 506def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 507 "srad $rA, $rS, $rB", IntRotateD, 508 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64; 509def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 510 "sraw $rA, $rS, $rB", IntShift, 511 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 512let isStore = 1, noResults = 1 in { 513def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst), 514 "stbx $rS, $dst", LdStGeneral, 515 [(truncstore GPRC:$rS, xaddr:$dst, i8)]>; 516def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst), 517 "sthx $rS, $dst", LdStGeneral, 518 [(truncstore GPRC:$rS, xaddr:$dst, i16)]>; 519def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst), 520 "stwx $rS, $dst", LdStGeneral, 521 [(store GPRC:$rS, xaddr:$dst)]>; 522def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 523 "stwux $rS, $rA, $rB", LdStGeneral, 524 []>; 525def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 526 "stdx $rS, $rA, $rB", LdStSTD, 527 []>, isPPC64; 528def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 529 "stdux $rS, $rA, $rB", LdStSTD, 530 []>, isPPC64; 531def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB), 532 "stvebx $rS, $rA, $rB", LdStGeneral, 533 []>; 534def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB), 535 "stvehx $rS, $rA, $rB", LdStGeneral, 536 []>; 537def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB), 538 "stvewx $rS, $rA, $rB", LdStGeneral, 539 []>; 540def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst), 541 "stvx $rS, $dst", LdStGeneral, 542 [(store (v4f32 VRRC:$rS), xoaddr:$dst)]>; 543} 544def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), 545 "srawi $rA, $rS, $SH", IntShift, 546 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 547def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS), 548 "cntlzw $rA, $rS", IntGeneral, 549 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 550def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS), 551 "extsb $rA, $rS", IntGeneral, 552 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 553def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS), 554 "extsh $rA, $rS", IntGeneral, 555 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 556def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS), 557 "extsw $rA, $rS", IntGeneral, 558 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 559def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB), 560 "cmp $crD, $long, $rA, $rB", IntCompare>; 561def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB), 562 "cmpl $crD, $long, $rA, $rB", IntCompare>; 563def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 564 "cmpw $crD, $rA, $rB", IntCompare>; 565def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 566 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 567def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 568 "cmplw $crD, $rA, $rB", IntCompare>; 569def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 570 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 571//def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB), 572// "fcmpo $crD, $fA, $fB", FPCompare>; 573def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB), 574 "fcmpu $crD, $fA, $fB", FPCompare>; 575def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB), 576 "fcmpu $crD, $fA, $fB", FPCompare>; 577 578let isLoad = 1 in { 579def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src), 580 "lfsx $frD, $src", LdStLFDU, 581 [(set F4RC:$frD, (load xaddr:$src))]>; 582def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src), 583 "lfdx $frD, $src", LdStLFDU, 584 [(set F8RC:$frD, (load xaddr:$src))]>; 585} 586def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB), 587 "fcfid $frD, $frB", FPGeneral, 588 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 589def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB), 590 "fctidz $frD, $frB", FPGeneral, 591 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 592def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB), 593 "fctiwz $frD, $frB", FPGeneral, 594 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 595def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB), 596 "frsp $frD, $frB", FPGeneral, 597 [(set F4RC:$frD, (fround F8RC:$frB))]>; 598def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB), 599 "fsqrt $frD, $frB", FPSqrt, 600 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 601def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB), 602 "fsqrts $frD, $frB", FPSqrt, 603 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 604 605/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending. 606def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB), 607 "fmr $frD, $frB", FPGeneral, 608 []>; // (set F4RC:$frD, F4RC:$frB) 609def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB), 610 "fmr $frD, $frB", FPGeneral, 611 []>; // (set F8RC:$frD, F8RC:$frB) 612def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB), 613 "fmr $frD, $frB", FPGeneral, 614 [(set F8RC:$frD, (fextend F4RC:$frB))]>; 615 616// These are artificially split into two different forms, for 4/8 byte FP. 617def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB), 618 "fabs $frD, $frB", FPGeneral, 619 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 620def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB), 621 "fabs $frD, $frB", FPGeneral, 622 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 623def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB), 624 "fnabs $frD, $frB", FPGeneral, 625 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 626def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB), 627 "fnabs $frD, $frB", FPGeneral, 628 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 629def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB), 630 "fneg $frD, $frB", FPGeneral, 631 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 632def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB), 633 "fneg $frD, $frB", FPGeneral, 634 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 635 636 637let isStore = 1, noResults = 1 in { 638def STFIWX: XForm_28<31, 983, (ops F4RC:$frS, memrr:$dst), 639 "stfiwx $frS, $dst", LdStUX, 640 []>; 641def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst), 642 "stfsx $frS, $dst", LdStUX, 643 [(store F4RC:$frS, xaddr:$dst)]>; 644def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst), 645 "stfdx $frS, $dst", LdStUX, 646 [(store F8RC:$frS, xaddr:$dst)]>; 647} 648 649// XL-Form instructions. condition register logical ops. 650// 651def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA), 652 "mcrf $BF, $BFA", BrMCR>; 653 654// XFX-Form instructions. Instructions that deal with SPRs 655// 656// Note that although LR should be listed as `8' and CTR as `9' in the SPR 657// field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9 658// which means the SPR value needs to be multiplied by a factor of 32. 659def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>; 660def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>; 661def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>; 662def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS), 663 "mtcrf $FXM, $rS", BrMCRX>; 664def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM), 665 "mfcr $rT, $FXM", SprMFCR>; 666def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>; 667def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>; 668def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM, $rS", 669 SprMTSPR>; 670 671// XS-Form instructions. Just 'sradi' 672// 673def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH), 674 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64; 675 676// XO-Form instructions. Arithmetic instructions that can set overflow bit 677// 678def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 679 "add $rT, $rA, $rB", IntGeneral, 680 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 681def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 682 "add $rT, $rA, $rB", IntGeneral, 683 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 684def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 685 "addc $rT, $rA, $rB", IntGeneral, 686 []>; 687def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 688 "adde $rT, $rA, $rB", IntGeneral, 689 []>; 690def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 691 "divd $rT, $rA, $rB", IntDivD, 692 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64; 693def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 694 "divdu $rT, $rA, $rB", IntDivD, 695 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64; 696def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 697 "divw $rT, $rA, $rB", IntDivW, 698 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>; 699def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 700 "divwu $rT, $rA, $rB", IntDivW, 701 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>; 702def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 703 "mulhd $rT, $rA, $rB", IntMulHW, 704 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 705def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 706 "mulhdu $rT, $rA, $rB", IntMulHWU, 707 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 708def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 709 "mulhw $rT, $rA, $rB", IntMulHW, 710 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 711def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 712 "mulhwu $rT, $rA, $rB", IntMulHWU, 713 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 714def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 715 "mulld $rT, $rA, $rB", IntMulHD, 716 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 717def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 718 "mullw $rT, $rA, $rB", IntMulHW, 719 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 720def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 721 "subf $rT, $rA, $rB", IntGeneral, 722 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 723def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 724 "subfc $rT, $rA, $rB", IntGeneral, 725 []>; 726def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 727 "subfe $rT, $rA, $rB", IntGeneral, 728 []>; 729def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA), 730 "addme $rT, $rA", IntGeneral, 731 []>; 732def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA), 733 "addze $rT, $rA", IntGeneral, 734 []>; 735def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA), 736 "neg $rT, $rA", IntGeneral, 737 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 738def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA), 739 "subfze $rT, $rA", IntGeneral, 740 []>; 741 742// A-Form instructions. Most of the instructions executed in the FPU are of 743// this type. 744// 745def FMADD : AForm_1<63, 29, 746 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 747 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 748 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), 749 F8RC:$FRB))]>, 750 Requires<[FPContractions]>; 751def FMADDS : AForm_1<59, 29, 752 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 753 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 754 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), 755 F4RC:$FRB))]>, 756 Requires<[FPContractions]>; 757def FMSUB : AForm_1<63, 28, 758 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 759 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 760 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), 761 F8RC:$FRB))]>, 762 Requires<[FPContractions]>; 763def FMSUBS : AForm_1<59, 28, 764 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 765 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 766 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), 767 F4RC:$FRB))]>, 768 Requires<[FPContractions]>; 769def FNMADD : AForm_1<63, 31, 770 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 771 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 772 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), 773 F8RC:$FRB)))]>, 774 Requires<[FPContractions]>; 775def FNMADDS : AForm_1<59, 31, 776 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 777 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 778 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), 779 F4RC:$FRB)))]>, 780 Requires<[FPContractions]>; 781def FNMSUB : AForm_1<63, 30, 782 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 783 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 784 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), 785 F8RC:$FRB)))]>, 786 Requires<[FPContractions]>; 787def FNMSUBS : AForm_1<59, 30, 788 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 789 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 790 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), 791 F4RC:$FRB)))]>, 792 Requires<[FPContractions]>; 793// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 794// having 4 of these, force the comparison to always be an 8-byte double (code 795// should use an FMRSD if the input comparison value really wants to be a float) 796// and 4/8 byte forms for the result and operand type.. 797def FSELD : AForm_1<63, 23, 798 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 799 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 800 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 801def FSELS : AForm_1<63, 23, 802 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 803 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 804 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 805def FADD : AForm_2<63, 21, 806 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 807 "fadd $FRT, $FRA, $FRB", FPGeneral, 808 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 809def FADDS : AForm_2<59, 21, 810 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 811 "fadds $FRT, $FRA, $FRB", FPGeneral, 812 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 813def FDIV : AForm_2<63, 18, 814 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 815 "fdiv $FRT, $FRA, $FRB", FPDivD, 816 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 817def FDIVS : AForm_2<59, 18, 818 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 819 "fdivs $FRT, $FRA, $FRB", FPDivS, 820 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 821def FMUL : AForm_3<63, 25, 822 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 823 "fmul $FRT, $FRA, $FRB", FPFused, 824 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 825def FMULS : AForm_3<59, 25, 826 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 827 "fmuls $FRT, $FRA, $FRB", FPGeneral, 828 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 829def FSUB : AForm_2<63, 20, 830 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 831 "fsub $FRT, $FRA, $FRB", FPGeneral, 832 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 833def FSUBS : AForm_2<59, 20, 834 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 835 "fsubs $FRT, $FRA, $FRB", FPGeneral, 836 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 837 838// M-Form instructions. rotate and mask instructions. 839// 840let isTwoAddress = 1, isCommutable = 1 in { 841// RLWIMI can be commuted if the rotate amount is zero. 842def RLWIMI : MForm_2<20, 843 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 844 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 845 []>; 846def RLDIMI : MDForm_1<30, 3, 847 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 848 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 849 []>, isPPC64; 850} 851def RLWINM : MForm_2<21, 852 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 853 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 854 []>; 855def RLWINMo : MForm_2<21, 856 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 857 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 858 []>, isDOT; 859def RLWNM : MForm_2<23, 860 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 861 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 862 []>; 863 864// MD-Form instructions. 64 bit rotate instructions. 865// 866def RLDICL : MDForm_1<30, 0, 867 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB), 868 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 869 []>, isPPC64; 870def RLDICR : MDForm_1<30, 1, 871 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME), 872 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 873 []>, isPPC64; 874 875// VA-Form instructions. 3-input AltiVec ops. 876def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), 877 "vmaddfp $vD, $vA, $vC, $vB", VecFP, 878 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC), 879 VRRC:$vB))]>, 880 Requires<[FPContractions]>; 881def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), 882 "vnmsubfp $vD, $vA, $vC, $vB", VecFP, 883 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, 884 VRRC:$vC), 885 VRRC:$vB)))]>, 886 Requires<[FPContractions]>; 887 888// VX-Form instructions. AltiVec arithmetic ops. 889def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), 890 "vaddfp $vD, $vA, $vB", VecFP, 891 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; 892def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), 893 "vadduwm $vD, $vA, $vB", VecGeneral, 894 [(set VRRC:$vD, (add VRRC:$vA, VRRC:$vB))]>; 895def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), 896 "vcfsx $vD, $vB, $UIMM", VecFP, 897 []>; 898def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), 899 "vcfux $vD, $vB, $UIMM", VecFP, 900 []>; 901def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), 902 "vctsxs $vD, $vB, $UIMM", VecFP, 903 []>; 904def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), 905 "vctuxs $vD, $vB, $UIMM", VecFP, 906 []>; 907def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB), 908 "vexptefp $vD, $vB", VecFP, 909 []>; 910def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB), 911 "vlogefp $vD, $vB", VecFP, 912 []>; 913def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), 914 "vmaxfp $vD, $vA, $vB", VecFP, 915 []>; 916def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), 917 "vminfp $vD, $vA, $vB", VecFP, 918 []>; 919def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB), 920 "vrefp $vD, $vB", VecFP, 921 []>; 922def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB), 923 "vrfim $vD, $vB", VecFP, 924 []>; 925def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB), 926 "vrfin $vD, $vB", VecFP, 927 []>; 928def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB), 929 "vrfip $vD, $vB", VecFP, 930 []>; 931def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB), 932 "vrfiz $vD, $vB", VecFP, 933 []>; 934def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB), 935 "vrsqrtefp $vD, $vB", VecFP, 936 []>; 937def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), 938 "vsubfp $vD, $vA, $vB", VecFP, 939 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; 940def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), 941 "vxor $vD, $vA, $vB", VecFP, 942 []>; 943 944// VX-Form Pseudo Instructions 945 946def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD), 947 "vxor $vD, $vD, $vD", VecFP, 948 []>; 949 950 951//===----------------------------------------------------------------------===// 952// DWARF Pseudo Instructions 953// 954 955def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file), 956 "; .loc $file, $line, $col", 957 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), 958 (i32 imm:$file))]>; 959 960def DWARF_LABEL : Pseudo<(ops i32imm:$id), 961 "\nLdebug_loc$id:", 962 [(dwarf_label (i32 imm:$id))]>; 963 964//===----------------------------------------------------------------------===// 965// PowerPC Instruction Patterns 966// 967 968// Arbitrary immediate support. Implement in terms of LIS/ORI. 969def : Pat<(i32 imm:$imm), 970 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 971 972// Implement the 'not' operation with the NOR instruction. 973def NOT : Pat<(not GPRC:$in), 974 (NOR GPRC:$in, GPRC:$in)>; 975 976// ADD an arbitrary immediate. 977def : Pat<(add GPRC:$in, imm:$imm), 978 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 979// OR an arbitrary immediate. 980def : Pat<(or GPRC:$in, imm:$imm), 981 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 982// XOR an arbitrary immediate. 983def : Pat<(xor GPRC:$in, imm:$imm), 984 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 985 986// Return void support. 987def : Pat<(ret), (BLR)>; 988 989// 64-bit support 990def : Pat<(i64 (zext GPRC:$in)), 991 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; 992def : Pat<(i64 (anyext GPRC:$in)), 993 (OR4To8 GPRC:$in, GPRC:$in)>; 994def : Pat<(i32 (trunc G8RC:$in)), 995 (OR8To4 G8RC:$in, G8RC:$in)>; 996 997// SHL 998def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 999 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1000def : Pat<(shl G8RC:$in, (i64 imm:$imm)), 1001 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 1002// SRL 1003def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1004 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1005def : Pat<(srl G8RC:$in, (i64 imm:$imm)), 1006 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 1007 1008// ROTL 1009def : Pat<(rotl GPRC:$in, GPRC:$sh), 1010 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1011def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1012 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1013 1014// Hi and Lo for Darwin Global Addresses. 1015def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1016def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1017def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1018def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1019def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1020 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1021def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1022 (ADDIS GPRC:$in, tconstpool:$g)>; 1023 1024def : Pat<(fmul VRRC:$vA, VRRC:$vB), 1025 (VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>; 1026 1027// Fused negative multiply subtract, alternate pattern 1028def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), 1029 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>, 1030 Requires<[FPContractions]>; 1031def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)), 1032 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>, 1033 Requires<[FPContractions]>; 1034 1035// Fused multiply add and multiply sub for packed float. These are represented 1036// separately from the real instructions above, for operations that must have 1037// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 1038def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C), 1039 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>; 1040def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C), 1041 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>; 1042 1043// Standard shifts. These are represented separately from the real shifts above 1044// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1045// amounts. 1046def : Pat<(sra GPRC:$rS, GPRC:$rB), 1047 (SRAW GPRC:$rS, GPRC:$rB)>; 1048def : Pat<(srl GPRC:$rS, GPRC:$rB), 1049 (SRW GPRC:$rS, GPRC:$rB)>; 1050def : Pat<(shl GPRC:$rS, GPRC:$rB), 1051 (SLW GPRC:$rS, GPRC:$rB)>; 1052 1053def : Pat<(i32 (zextload iaddr:$src, i1)), 1054 (LBZ iaddr:$src)>; 1055def : Pat<(i32 (zextload xaddr:$src, i1)), 1056 (LBZX xaddr:$src)>; 1057def : Pat<(i32 (extload iaddr:$src, i1)), 1058 (LBZ iaddr:$src)>; 1059def : Pat<(i32 (extload xaddr:$src, i1)), 1060 (LBZX xaddr:$src)>; 1061def : Pat<(i32 (extload iaddr:$src, i8)), 1062 (LBZ iaddr:$src)>; 1063def : Pat<(i32 (extload xaddr:$src, i8)), 1064 (LBZX xaddr:$src)>; 1065def : Pat<(i32 (extload iaddr:$src, i16)), 1066 (LHZ iaddr:$src)>; 1067def : Pat<(i32 (extload xaddr:$src, i16)), 1068 (LHZX xaddr:$src)>; 1069def : Pat<(f64 (extload iaddr:$src, f32)), 1070 (FMRSD (LFS iaddr:$src))>; 1071def : Pat<(f64 (extload xaddr:$src, f32)), 1072 (FMRSD (LFSX xaddr:$src))>; 1073 1074def : Pat<(v4i32 (load xoaddr:$src)), 1075 (v4i32 (LVX xoaddr:$src))>; 1076def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst), 1077 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>; 1078 1079// Same as above, but using a temporary. FIXME: implement temporaries :) 1080/* 1081def : Pattern<(xor GPRC:$in, imm:$imm), 1082 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))), 1083 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>; 1084*/ 1085 1086//===----------------------------------------------------------------------===// 1087// PowerPCInstrInfo Definition 1088// 1089def PowerPCInstrInfo : InstrInfo { 1090 let PHIInst = PHI; 1091 1092 let TSFlagsFields = [ "VMX", "PPC64" ]; 1093 let TSFlagsShifts = [ 0, 1 ]; 1094 1095 let isLittleEndianEncoding = 1; 1096} 1097 1098