PPCInstrInfo.td revision 528180ed7ba092f5767163f567fd80f0887d9e4c
1//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl 24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32> 25]>; 26def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 27def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>; 28 29//===----------------------------------------------------------------------===// 30// PowerPC specific DAG Nodes. 31// 32 33def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 34def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 35def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 36def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>; 37 38def PPCfsel : SDNode<"PPCISD::FSEL", 39 // Type constraint for fsel. 40 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 41 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 42 43def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 44def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 45def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 46def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 47 48// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 49// amounts. These nodes are generated by the multi-precision shift code. 50def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>; 51def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>; 52def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>; 53 54// These are target-independent nodes, but have target-specific formats. 55def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>; 56def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>; 57 58def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag, 59 [SDNPHasChain, SDNPOptInFlag]>; 60 61//===----------------------------------------------------------------------===// 62// PowerPC specific transformation functions and pattern fragments. 63// 64 65def SHL32 : SDNodeXForm<imm, [{ 66 // Transformation function: 31 - imm 67 return getI32Imm(31 - N->getValue()); 68}]>; 69 70def SHL64 : SDNodeXForm<imm, [{ 71 // Transformation function: 63 - imm 72 return getI32Imm(63 - N->getValue()); 73}]>; 74 75def SRL32 : SDNodeXForm<imm, [{ 76 // Transformation function: 32 - imm 77 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0); 78}]>; 79 80def SRL64 : SDNodeXForm<imm, [{ 81 // Transformation function: 64 - imm 82 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0); 83}]>; 84 85def LO16 : SDNodeXForm<imm, [{ 86 // Transformation function: get the low 16 bits. 87 return getI32Imm((unsigned short)N->getValue()); 88}]>; 89 90def HI16 : SDNodeXForm<imm, [{ 91 // Transformation function: shift the immediate value down into the low bits. 92 return getI32Imm((unsigned)N->getValue() >> 16); 93}]>; 94 95def HA16 : SDNodeXForm<imm, [{ 96 // Transformation function: shift the immediate value down into the low bits. 97 signed int Val = N->getValue(); 98 return getI32Imm((Val - (signed short)Val) >> 16); 99}]>; 100 101 102def immSExt16 : PatLeaf<(imm), [{ 103 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 104 // field. Used by instructions like 'addi'. 105 return (int)N->getValue() == (short)N->getValue(); 106}]>; 107def immZExt16 : PatLeaf<(imm), [{ 108 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 109 // field. Used by instructions like 'ori'. 110 return (unsigned)N->getValue() == (unsigned short)N->getValue(); 111}], LO16>; 112 113def imm16Shifted : PatLeaf<(imm), [{ 114 // imm16Shifted predicate - True if only bits in the top 16-bits of the 115 // immediate are set. Used by instructions like 'addis'. 116 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue(); 117}], HI16>; 118 119/* 120// Example of a legalize expander: Only for PPC64. 121def : Expander<(set i64:$dst, (fp_to_sint f64:$src)), 122 [(set f64:$tmp , (FCTIDZ f64:$src)), 123 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)), 124 (store f64:$tmp, i32:$tmpFI), 125 (set i64:$dst, (load i32:$tmpFI))], 126 Subtarget_PPC64>; 127*/ 128 129//===----------------------------------------------------------------------===// 130// PowerPC Flag Definitions. 131 132class isPPC64 { bit PPC64 = 1; } 133class isVMX { bit VMX = 1; } 134class isDOT { 135 list<Register> Defs = [CR0]; 136 bit RC = 1; 137} 138 139 140 141//===----------------------------------------------------------------------===// 142// PowerPC Operand Definitions. 143 144def u5imm : Operand<i32> { 145 let PrintMethod = "printU5ImmOperand"; 146} 147def u6imm : Operand<i32> { 148 let PrintMethod = "printU6ImmOperand"; 149} 150def s16imm : Operand<i32> { 151 let PrintMethod = "printS16ImmOperand"; 152} 153def u16imm : Operand<i32> { 154 let PrintMethod = "printU16ImmOperand"; 155} 156def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 157 let PrintMethod = "printS16X4ImmOperand"; 158} 159def target : Operand<OtherVT> { 160 let PrintMethod = "printBranchOperand"; 161} 162def calltarget : Operand<i32> { 163 let PrintMethod = "printCallOperand"; 164} 165def aaddr : Operand<i32> { 166 let PrintMethod = "printAbsAddrOperand"; 167} 168def piclabel: Operand<i32> { 169 let PrintMethod = "printPICLabel"; 170} 171def symbolHi: Operand<i32> { 172 let PrintMethod = "printSymbolHi"; 173} 174def symbolLo: Operand<i32> { 175 let PrintMethod = "printSymbolLo"; 176} 177def crbitm: Operand<i8> { 178 let PrintMethod = "printcrbitm"; 179} 180// Address operands 181def memri : Operand<i32> { 182 let PrintMethod = "printMemRegImm"; 183 let NumMIOperands = 2; 184 let MIOperandInfo = (ops i32imm, GPRC); 185} 186def memrr : Operand<i32> { 187 let PrintMethod = "printMemRegReg"; 188 let NumMIOperands = 2; 189 let MIOperandInfo = (ops GPRC, GPRC); 190} 191 192// Define PowerPC specific addressing mode. 193def iaddr : ComplexPattern<i32, 2, "SelectAddrImm", []>; 194def xaddr : ComplexPattern<i32, 2, "SelectAddrIdx", []>; 195def xoaddr : ComplexPattern<i32, 2, "SelectAddrIdxOnly",[]>; 196 197//===----------------------------------------------------------------------===// 198// PowerPC Instruction Predicate Definitions. 199def FPContractions : Predicate<"!NoExcessFPPrecision">; 200 201//===----------------------------------------------------------------------===// 202// PowerPC Instruction Definitions. 203 204// Pseudo-instructions: 205 206let hasCtrlDep = 1 in { 207def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), 208 "; ADJCALLSTACKDOWN", 209 [(callseq_start imm:$amt)]>; 210def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), 211 "; ADJCALLSTACKUP", 212 [(callseq_end imm:$amt)]>; 213 214def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS), 215 "UPDATE_VRSAVE $rD, $rS", []>; 216} 217def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC", 218 [(set GPRC:$rD, (undef))]>; 219def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8", 220 [(set F8RC:$rD, (undef))]>; 221def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4", 222 [(set F4RC:$rD, (undef))]>; 223def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC", 224 [(set VRRC:$rD, (v4f32 (undef)))]>; 225 226// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 227// scheduler into a branch sequence. 228let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler. 229 PPC970_Single = 1 in { 230 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F, 231 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>; 232 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F, 233 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>; 234 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F, 235 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>; 236} 237 238let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in { 239 let isReturn = 1 in 240 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>; 241 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>; 242} 243 244let Defs = [LR] in 245 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>, 246 PPC970_Unit_BRU; 247 248let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, 249 noResults = 1, PPC970_Unit = 7 in { 250 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$true), 251 "; COND_BRANCH", []>; 252 def B : IForm<18, 0, 0, (ops target:$dst), 253 "b $dst", BrB, 254 [(br bb:$dst)]>; 255 256 // FIXME: 4*CR# needs to be added to the BI field! 257 // This will only work for CR0 as it stands now 258 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block), 259 "blt $crS, $block", BrB>; 260 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block), 261 "ble $crS, $block", BrB>; 262 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block), 263 "beq $crS, $block", BrB>; 264 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block), 265 "bge $crS, $block", BrB>; 266 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block), 267 "bgt $crS, $block", BrB>; 268 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block), 269 "bne $crS, $block", BrB>; 270 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block), 271 "bun $crS, $block", BrB>; 272 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block), 273 "bnu $crS, $block", BrB>; 274} 275 276let isCall = 1, noResults = 1, PPC970_Unit = 7, 277 // All calls clobber the non-callee saved registers... 278 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 279 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 280 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 281 LR,CTR, 282 CR0,CR1,CR5,CR6,CR7] in { 283 // Convenient aliases for call instructions 284 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops), 285 "bl $func", BrB, []>; 286 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), 287 "bla $func", BrB, []>; 288 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB, 289 []>; 290} 291 292// D-Form instructions. Most instructions that perform an operation on a 293// register and an immediate are of this type. 294// 295let isLoad = 1, PPC970_Unit = 2 in { 296def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src), 297 "lbz $rD, $src", LdStGeneral, 298 [(set GPRC:$rD, (zextload iaddr:$src, i8))]>; 299def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src), 300 "lha $rD, $src", LdStLHA, 301 [(set GPRC:$rD, (sextload iaddr:$src, i16))]>, 302 PPC970_DGroup_Cracked; 303def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src), 304 "lhz $rD, $src", LdStGeneral, 305 [(set GPRC:$rD, (zextload iaddr:$src, i16))]>; 306def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src), 307 "lwz $rD, $src", LdStGeneral, 308 [(set GPRC:$rD, (load iaddr:$src))]>; 309def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA), 310 "lwzu $rD, $disp($rA)", LdStGeneral, 311 []>; 312} 313let PPC970_Unit = 1 in { // FXU Operations. 314def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 315 "addi $rD, $rA, $imm", IntGeneral, 316 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 317def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 318 "addic $rD, $rA, $imm", IntGeneral, 319 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 320 PPC970_DGroup_Cracked; 321def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 322 "addic. $rD, $rA, $imm", IntGeneral, 323 []>; 324def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm), 325 "addis $rD, $rA, $imm", IntGeneral, 326 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>; 327def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym), 328 "la $rD, $sym($rA)", IntGeneral, 329 [(set GPRC:$rD, (add GPRC:$rA, 330 (PPClo tglobaladdr:$sym, 0)))]>; 331def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 332 "mulli $rD, $rA, $imm", IntMulLI, 333 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 334def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 335 "subfic $rD, $rA, $imm", IntGeneral, 336 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 337def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm), 338 "li $rD, $imm", IntGeneral, 339 [(set GPRC:$rD, immSExt16:$imm)]>; 340def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm), 341 "lis $rD, $imm", IntGeneral, 342 [(set GPRC:$rD, imm16Shifted:$imm)]>; 343} 344let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 345def STB : DForm_3<38, (ops GPRC:$rS, memri:$src), 346 "stb $rS, $src", LdStGeneral, 347 [(truncstore GPRC:$rS, iaddr:$src, i8)]>; 348def STH : DForm_3<44, (ops GPRC:$rS, memri:$src), 349 "sth $rS, $src", LdStGeneral, 350 [(truncstore GPRC:$rS, iaddr:$src, i16)]>; 351def STW : DForm_3<36, (ops GPRC:$rS, memri:$src), 352 "stw $rS, $src", LdStGeneral, 353 [(store GPRC:$rS, iaddr:$src)]>; 354def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 355 "stwu $rS, $disp($rA)", LdStGeneral, 356 []>; 357} 358let PPC970_Unit = 1 in { // FXU Operations. 359def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 360 "andi. $dst, $src1, $src2", IntGeneral, 361 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 362 isDOT; 363def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 364 "andis. $dst, $src1, $src2", IntGeneral, 365 [(set GPRC:$dst, (and GPRC:$src1, imm16Shifted:$src2))]>, 366 isDOT; 367def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 368 "ori $dst, $src1, $src2", IntGeneral, 369 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 370def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 371 "oris $dst, $src1, $src2", IntGeneral, 372 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>; 373def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 374 "xori $dst, $src1, $src2", IntGeneral, 375 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 376def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 377 "xoris $dst, $src1, $src2", IntGeneral, 378 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>; 379def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral, 380 []>; 381def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm), 382 "cmpi $crD, $L, $rA, $imm", IntCompare>; 383def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 384 "cmpwi $crD, $rA, $imm", IntCompare>; 385def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 386 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 387def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2), 388 "cmpli $dst, $size, $src1, $src2", IntCompare>; 389def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 390 "cmplwi $dst, $src1, $src2", IntCompare>; 391def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 392 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 393} 394let isLoad = 1, PPC970_Unit = 2 in { 395def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src), 396 "lfs $rD, $src", LdStLFDU, 397 [(set F4RC:$rD, (load iaddr:$src))]>; 398def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src), 399 "lfd $rD, $src", LdStLFD, 400 [(set F8RC:$rD, (load iaddr:$src))]>; 401} 402let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 403def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst), 404 "stfs $rS, $dst", LdStUX, 405 [(store F4RC:$rS, iaddr:$dst)]>; 406def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst), 407 "stfd $rS, $dst", LdStUX, 408 [(store F8RC:$rS, iaddr:$dst)]>; 409} 410 411// DS-Form instructions. Load/Store instructions available in PPC-64 412// 413let isLoad = 1, PPC970_Unit = 2 in { 414def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 415 "lwa $rT, $DS($rA)", LdStLWA, 416 []>, isPPC64, PPC970_DGroup_Cracked; 417def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 418 "ld $rT, $DS($rA)", LdStLD, 419 []>, isPPC64; 420} 421let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 422def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 423 "std $rT, $DS($rA)", LdStSTD, 424 []>, isPPC64; 425def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 426 "stdu $rT, $DS($rA)", LdStSTD, 427 []>, isPPC64; 428} 429 430// X-Form instructions. Most instructions that perform an operation on a 431// register and another register are of this type. 432// 433let isLoad = 1, PPC970_Unit = 2 in { 434def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src), 435 "lbzx $rD, $src", LdStGeneral, 436 [(set GPRC:$rD, (zextload xaddr:$src, i8))]>; 437def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src), 438 "lhax $rD, $src", LdStLHA, 439 [(set GPRC:$rD, (sextload xaddr:$src, i16))]>, 440 PPC970_DGroup_Cracked; 441def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src), 442 "lhzx $rD, $src", LdStGeneral, 443 [(set GPRC:$rD, (zextload xaddr:$src, i16))]>; 444def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src), 445 "lwax $rD, $src", LdStLHA, 446 [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64, 447 PPC970_DGroup_Cracked; 448def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src), 449 "lwzx $rD, $src", LdStGeneral, 450 [(set GPRC:$rD, (load xaddr:$src))]>; 451def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src), 452 "ldx $rD, $src", LdStLD, 453 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 454def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), 455 "lvebx $vD, $base, $rA", LdStGeneral, 456 []>; 457def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), 458 "lvehx $vD, $base, $rA", LdStGeneral, 459 []>; 460def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), 461 "lvewx $vD, $base, $rA", LdStGeneral, 462 []>; 463def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src), 464 "lvx $vD, $src", LdStGeneral, 465 [(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>; 466} 467def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), 468 "lvsl $vD, $base, $rA", LdStGeneral, 469 []>, PPC970_Unit_LSU; 470def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), 471 "lvsl $vD, $base, $rA", LdStGeneral, 472 []>, PPC970_Unit_LSU; 473let PPC970_Unit = 1 in { // FXU Operations. 474def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 475 "nand $rA, $rS, $rB", IntGeneral, 476 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 477def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 478 "and $rA, $rS, $rB", IntGeneral, 479 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 480def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 481 "and. $rA, $rS, $rB", IntGeneral, 482 []>, isDOT; 483def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 484 "andc $rA, $rS, $rB", IntGeneral, 485 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 486def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 487 "or $rA, $rS, $rB", IntGeneral, 488 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 489def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 490 "or $rA, $rS, $rB", IntGeneral, 491 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 492def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB), 493 "or $rA, $rS, $rB", IntGeneral, 494 []>; 495def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB), 496 "or $rA, $rS, $rB", IntGeneral, 497 []>; 498def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 499 "nor $rA, $rS, $rB", IntGeneral, 500 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 501def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 502 "or. $rA, $rS, $rB", IntGeneral, 503 []>, isDOT; 504def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 505 "orc $rA, $rS, $rB", IntGeneral, 506 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 507def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 508 "eqv $rA, $rS, $rB", IntGeneral, 509 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 510def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 511 "xor $rA, $rS, $rB", IntGeneral, 512 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 513def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 514 "sld $rA, $rS, $rB", IntRotateD, 515 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64; 516def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 517 "slw $rA, $rS, $rB", IntGeneral, 518 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 519def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 520 "srd $rA, $rS, $rB", IntRotateD, 521 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64; 522def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 523 "srw $rA, $rS, $rB", IntGeneral, 524 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 525def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 526 "srad $rA, $rS, $rB", IntRotateD, 527 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64; 528def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 529 "sraw $rA, $rS, $rB", IntShift, 530 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 531} 532let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 533def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst), 534 "stbx $rS, $dst", LdStGeneral, 535 [(truncstore GPRC:$rS, xaddr:$dst, i8)]>, 536 PPC970_DGroup_Cracked; 537def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst), 538 "sthx $rS, $dst", LdStGeneral, 539 [(truncstore GPRC:$rS, xaddr:$dst, i16)]>, 540 PPC970_DGroup_Cracked; 541def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst), 542 "stwx $rS, $dst", LdStGeneral, 543 [(store GPRC:$rS, xaddr:$dst)]>, 544 PPC970_DGroup_Cracked; 545def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 546 "stwux $rS, $rA, $rB", LdStGeneral, 547 []>; 548def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 549 "stdx $rS, $rA, $rB", LdStSTD, 550 []>, isPPC64, PPC970_DGroup_Cracked; 551def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 552 "stdux $rS, $rA, $rB", LdStSTD, 553 []>, isPPC64; 554def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB), 555 "stvebx $rS, $rA, $rB", LdStGeneral, 556 []>; 557def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB), 558 "stvehx $rS, $rA, $rB", LdStGeneral, 559 []>; 560def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB), 561 "stvewx $rS, $rA, $rB", LdStGeneral, 562 []>; 563def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst), 564 "stvx $rS, $dst", LdStGeneral, 565 [(store (v4f32 VRRC:$rS), xoaddr:$dst)]>; 566} 567let PPC970_Unit = 1 in { // FXU Operations. 568def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), 569 "srawi $rA, $rS, $SH", IntShift, 570 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 571def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS), 572 "cntlzw $rA, $rS", IntGeneral, 573 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 574def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS), 575 "extsb $rA, $rS", IntGeneral, 576 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 577def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS), 578 "extsh $rA, $rS", IntGeneral, 579 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 580def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS), 581 "extsw $rA, $rS", IntGeneral, 582 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 583def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB), 584 "cmp $crD, $long, $rA, $rB", IntCompare>; 585def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB), 586 "cmpl $crD, $long, $rA, $rB", IntCompare>; 587def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 588 "cmpw $crD, $rA, $rB", IntCompare>; 589def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 590 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 591def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 592 "cmplw $crD, $rA, $rB", IntCompare>; 593def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 594 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 595} 596let PPC970_Unit = 3 in { // FPU Operations. 597//def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB), 598// "fcmpo $crD, $fA, $fB", FPCompare>; 599def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB), 600 "fcmpu $crD, $fA, $fB", FPCompare>; 601def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB), 602 "fcmpu $crD, $fA, $fB", FPCompare>; 603} 604let isLoad = 1, PPC970_Unit = 2 in { 605def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src), 606 "lfsx $frD, $src", LdStLFDU, 607 [(set F4RC:$frD, (load xaddr:$src))]>; 608def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src), 609 "lfdx $frD, $src", LdStLFDU, 610 [(set F8RC:$frD, (load xaddr:$src))]>; 611} 612let PPC970_Unit = 3 in { // FPU Operations. 613def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB), 614 "fcfid $frD, $frB", FPGeneral, 615 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 616def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB), 617 "fctidz $frD, $frB", FPGeneral, 618 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 619def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB), 620 "fctiwz $frD, $frB", FPGeneral, 621 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 622def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB), 623 "frsp $frD, $frB", FPGeneral, 624 [(set F4RC:$frD, (fround F8RC:$frB))]>; 625def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB), 626 "fsqrt $frD, $frB", FPSqrt, 627 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 628def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB), 629 "fsqrts $frD, $frB", FPSqrt, 630 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 631} 632 633/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending. 634/// 635/// Note that these are defined as pseudo-ops on the PPC970 because they are 636/// often coallesced away and we don't want the dispatch group builder to think 637/// that they will fill slots (which could cause the load of a LSU reject to 638/// sneak into a d-group with a store). 639def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB), 640 "fmr $frD, $frB", FPGeneral, 641 []>, // (set F4RC:$frD, F4RC:$frB) 642 PPC970_Unit_Pseudo; 643def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB), 644 "fmr $frD, $frB", FPGeneral, 645 []>, // (set F8RC:$frD, F8RC:$frB) 646 PPC970_Unit_Pseudo; 647def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB), 648 "fmr $frD, $frB", FPGeneral, 649 [(set F8RC:$frD, (fextend F4RC:$frB))]>, 650 PPC970_Unit_Pseudo; 651 652let PPC970_Unit = 3 in { // FPU Operations. 653// These are artificially split into two different forms, for 4/8 byte FP. 654def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB), 655 "fabs $frD, $frB", FPGeneral, 656 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 657def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB), 658 "fabs $frD, $frB", FPGeneral, 659 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 660def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB), 661 "fnabs $frD, $frB", FPGeneral, 662 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 663def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB), 664 "fnabs $frD, $frB", FPGeneral, 665 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 666def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB), 667 "fneg $frD, $frB", FPGeneral, 668 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 669def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB), 670 "fneg $frD, $frB", FPGeneral, 671 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 672} 673 674let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 675def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst), 676 "stfiwx $frS, $dst", LdStUX, 677 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 678def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst), 679 "stfsx $frS, $dst", LdStUX, 680 [(store F4RC:$frS, xaddr:$dst)]>; 681def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst), 682 "stfdx $frS, $dst", LdStUX, 683 [(store F8RC:$frS, xaddr:$dst)]>; 684} 685 686// XL-Form instructions. condition register logical ops. 687// 688def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA), 689 "mcrf $BF, $BFA", BrMCR>, 690 PPC970_DGroup_First, PPC970_Unit_CRU; 691 692// XFX-Form instructions. Instructions that deal with SPRs. 693// 694def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>, 695 PPC970_DGroup_First, PPC970_Unit_FXU; 696def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>, 697 PPC970_DGroup_First, PPC970_Unit_FXU; 698 699def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>, 700 PPC970_DGroup_First, PPC970_Unit_FXU; 701def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>, 702 PPC970_DGroup_First, PPC970_Unit_FXU; 703 704// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 705// a GPR on the PPC970. As such, copies in and out have the same performance 706// characteristics as an OR instruction. 707def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), 708 "mtspr 256, $rS", IntGeneral>, 709 PPC970_DGroup_Single, PPC970_Unit_FXU; 710def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), 711 "mfspr $rT, 256", IntGeneral>, 712 PPC970_DGroup_First, PPC970_Unit_FXU; 713 714def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>, 715 PPC970_MicroCode, PPC970_Unit_CRU; 716def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS), 717 "mtcrf $FXM, $rS", BrMCRX>, 718 PPC970_MicroCode, PPC970_Unit_CRU; 719def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM), 720 "mfcr $rT, $FXM", SprMFCR>, 721 PPC970_DGroup_First, PPC970_Unit_CRU; 722 723// XS-Form instructions. Just 'sradi' 724// 725let PPC970_Unit = 1 in { // FXU Operations. 726def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH), 727 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64; 728 729// XO-Form instructions. Arithmetic instructions that can set overflow bit 730// 731def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 732 "add $rT, $rA, $rB", IntGeneral, 733 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 734def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 735 "add $rT, $rA, $rB", IntGeneral, 736 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 737def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 738 "addc $rT, $rA, $rB", IntGeneral, 739 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 740 PPC970_DGroup_Cracked; 741def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 742 "adde $rT, $rA, $rB", IntGeneral, 743 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 744def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 745 "divd $rT, $rA, $rB", IntDivD, 746 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 747 PPC970_DGroup_First, PPC970_DGroup_Cracked; 748def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 749 "divdu $rT, $rA, $rB", IntDivD, 750 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 751 PPC970_DGroup_First, PPC970_DGroup_Cracked; 752def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 753 "divw $rT, $rA, $rB", IntDivW, 754 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 755 PPC970_DGroup_First, PPC970_DGroup_Cracked; 756def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 757 "divwu $rT, $rA, $rB", IntDivW, 758 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 759 PPC970_DGroup_First, PPC970_DGroup_Cracked; 760def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 761 "mulhd $rT, $rA, $rB", IntMulHW, 762 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 763def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 764 "mulhdu $rT, $rA, $rB", IntMulHWU, 765 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 766def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 767 "mulhw $rT, $rA, $rB", IntMulHW, 768 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 769def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 770 "mulhwu $rT, $rA, $rB", IntMulHWU, 771 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 772def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 773 "mulld $rT, $rA, $rB", IntMulHD, 774 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 775def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 776 "mullw $rT, $rA, $rB", IntMulHW, 777 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 778def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 779 "subf $rT, $rA, $rB", IntGeneral, 780 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 781def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 782 "subfc $rT, $rA, $rB", IntGeneral, 783 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 784 PPC970_DGroup_Cracked; 785def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 786 "subfe $rT, $rA, $rB", IntGeneral, 787 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 788def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA), 789 "addme $rT, $rA", IntGeneral, 790 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>; 791def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA), 792 "addze $rT, $rA", IntGeneral, 793 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 794def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA), 795 "neg $rT, $rA", IntGeneral, 796 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 797def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA), 798 "subfme $rT, $rA", IntGeneral, 799 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>; 800def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA), 801 "subfze $rT, $rA", IntGeneral, 802 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 803} 804 805// A-Form instructions. Most of the instructions executed in the FPU are of 806// this type. 807// 808let PPC970_Unit = 3 in { // FPU Operations. 809def FMADD : AForm_1<63, 29, 810 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 811 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 812 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), 813 F8RC:$FRB))]>, 814 Requires<[FPContractions]>; 815def FMADDS : AForm_1<59, 29, 816 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 817 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 818 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), 819 F4RC:$FRB))]>, 820 Requires<[FPContractions]>; 821def FMSUB : AForm_1<63, 28, 822 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 823 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 824 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), 825 F8RC:$FRB))]>, 826 Requires<[FPContractions]>; 827def FMSUBS : AForm_1<59, 28, 828 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 829 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 830 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), 831 F4RC:$FRB))]>, 832 Requires<[FPContractions]>; 833def FNMADD : AForm_1<63, 31, 834 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 835 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 836 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), 837 F8RC:$FRB)))]>, 838 Requires<[FPContractions]>; 839def FNMADDS : AForm_1<59, 31, 840 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 841 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 842 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), 843 F4RC:$FRB)))]>, 844 Requires<[FPContractions]>; 845def FNMSUB : AForm_1<63, 30, 846 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 847 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 848 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), 849 F8RC:$FRB)))]>, 850 Requires<[FPContractions]>; 851def FNMSUBS : AForm_1<59, 30, 852 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 853 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 854 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), 855 F4RC:$FRB)))]>, 856 Requires<[FPContractions]>; 857// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 858// having 4 of these, force the comparison to always be an 8-byte double (code 859// should use an FMRSD if the input comparison value really wants to be a float) 860// and 4/8 byte forms for the result and operand type.. 861def FSELD : AForm_1<63, 23, 862 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 863 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 864 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 865def FSELS : AForm_1<63, 23, 866 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 867 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 868 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 869def FADD : AForm_2<63, 21, 870 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 871 "fadd $FRT, $FRA, $FRB", FPGeneral, 872 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 873def FADDS : AForm_2<59, 21, 874 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 875 "fadds $FRT, $FRA, $FRB", FPGeneral, 876 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 877def FDIV : AForm_2<63, 18, 878 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 879 "fdiv $FRT, $FRA, $FRB", FPDivD, 880 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 881def FDIVS : AForm_2<59, 18, 882 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 883 "fdivs $FRT, $FRA, $FRB", FPDivS, 884 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 885def FMUL : AForm_3<63, 25, 886 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 887 "fmul $FRT, $FRA, $FRB", FPFused, 888 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 889def FMULS : AForm_3<59, 25, 890 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 891 "fmuls $FRT, $FRA, $FRB", FPGeneral, 892 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 893def FSUB : AForm_2<63, 20, 894 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 895 "fsub $FRT, $FRA, $FRB", FPGeneral, 896 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 897def FSUBS : AForm_2<59, 20, 898 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 899 "fsubs $FRT, $FRA, $FRB", FPGeneral, 900 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 901} 902 903let PPC970_Unit = 1 in { // FXU Operations. 904// M-Form instructions. rotate and mask instructions. 905// 906let isTwoAddress = 1, isCommutable = 1 in { 907// RLWIMI can be commuted if the rotate amount is zero. 908def RLWIMI : MForm_2<20, 909 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 910 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 911 []>, PPC970_DGroup_Cracked; 912def RLDIMI : MDForm_1<30, 3, 913 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 914 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 915 []>, isPPC64; 916} 917def RLWINM : MForm_2<21, 918 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 919 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 920 []>; 921def RLWINMo : MForm_2<21, 922 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 923 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 924 []>, isDOT, PPC970_DGroup_Cracked; 925def RLWNM : MForm_2<23, 926 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 927 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 928 []>; 929 930// MD-Form instructions. 64 bit rotate instructions. 931// 932def RLDICL : MDForm_1<30, 0, 933 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB), 934 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 935 []>, isPPC64; 936def RLDICR : MDForm_1<30, 1, 937 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME), 938 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 939 []>, isPPC64; 940} 941 942let PPC970_Unit = 5 in { // VALU Operations. 943// VA-Form instructions. 3-input AltiVec ops. 944def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), 945 "vmaddfp $vD, $vA, $vC, $vB", VecFP, 946 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC), 947 VRRC:$vB))]>, 948 Requires<[FPContractions]>; 949def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), 950 "vnmsubfp $vD, $vA, $vC, $vB", VecFP, 951 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, 952 VRRC:$vC), 953 VRRC:$vB)))]>, 954 Requires<[FPContractions]>; 955 956// VX-Form instructions. AltiVec arithmetic ops. 957def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), 958 "vaddfp $vD, $vA, $vB", VecFP, 959 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; 960def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), 961 "vadduwm $vD, $vA, $vB", VecGeneral, 962 [(set VRRC:$vD, (add VRRC:$vA, VRRC:$vB))]>; 963def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), 964 "vcfsx $vD, $vB, $UIMM", VecFP, 965 []>; 966def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), 967 "vcfux $vD, $vB, $UIMM", VecFP, 968 []>; 969def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), 970 "vctsxs $vD, $vB, $UIMM", VecFP, 971 []>; 972def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), 973 "vctuxs $vD, $vB, $UIMM", VecFP, 974 []>; 975def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB), 976 "vexptefp $vD, $vB", VecFP, 977 []>; 978def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB), 979 "vlogefp $vD, $vB", VecFP, 980 []>; 981def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), 982 "vmaxfp $vD, $vA, $vB", VecFP, 983 []>; 984def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), 985 "vminfp $vD, $vA, $vB", VecFP, 986 []>; 987def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB), 988 "vrefp $vD, $vB", VecFP, 989 []>; 990def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB), 991 "vrfim $vD, $vB", VecFP, 992 []>; 993def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB), 994 "vrfin $vD, $vB", VecFP, 995 []>; 996def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB), 997 "vrfip $vD, $vB", VecFP, 998 []>; 999def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB), 1000 "vrfiz $vD, $vB", VecFP, 1001 []>; 1002def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB), 1003 "vrsqrtefp $vD, $vB", VecFP, 1004 []>; 1005def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), 1006 "vsubfp $vD, $vA, $vB", VecFP, 1007 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; 1008def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), 1009 "vor $vD, $vA, $vB", VecFP, 1010 []>; 1011def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), 1012 "vxor $vD, $vA, $vB", VecFP, 1013 []>; 1014 1015// VX-Form Pseudo Instructions 1016 1017def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD), 1018 "vxor $vD, $vD, $vD", VecFP, 1019 []>; 1020} 1021 1022//===----------------------------------------------------------------------===// 1023// DWARF Pseudo Instructions 1024// 1025 1026def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file), 1027 "; .loc $file, $line, $col", 1028 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), 1029 (i32 imm:$file))]>; 1030 1031def DWARF_LABEL : Pseudo<(ops i32imm:$id), 1032 "\nLdebug_loc$id:", 1033 [(dwarf_label (i32 imm:$id))]>; 1034 1035//===----------------------------------------------------------------------===// 1036// PowerPC Instruction Patterns 1037// 1038 1039// Arbitrary immediate support. Implement in terms of LIS/ORI. 1040def : Pat<(i32 imm:$imm), 1041 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1042 1043// Implement the 'not' operation with the NOR instruction. 1044def NOT : Pat<(not GPRC:$in), 1045 (NOR GPRC:$in, GPRC:$in)>; 1046 1047// ADD an arbitrary immediate. 1048def : Pat<(add GPRC:$in, imm:$imm), 1049 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1050// OR an arbitrary immediate. 1051def : Pat<(or GPRC:$in, imm:$imm), 1052 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1053// XOR an arbitrary immediate. 1054def : Pat<(xor GPRC:$in, imm:$imm), 1055 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1056// SUBFIC 1057def : Pat<(sub immSExt16:$imm, GPRC:$in), 1058 (SUBFIC GPRC:$in, imm:$imm)>; 1059 1060// Return void support. 1061def : Pat<(ret), (BLR)>; 1062 1063// 64-bit support 1064def : Pat<(i64 (zext GPRC:$in)), 1065 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; 1066def : Pat<(i64 (anyext GPRC:$in)), 1067 (OR4To8 GPRC:$in, GPRC:$in)>; 1068def : Pat<(i32 (trunc G8RC:$in)), 1069 (OR8To4 G8RC:$in, G8RC:$in)>; 1070 1071// SHL 1072def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1073 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1074def : Pat<(shl G8RC:$in, (i64 imm:$imm)), 1075 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 1076// SRL 1077def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1078 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1079def : Pat<(srl G8RC:$in, (i64 imm:$imm)), 1080 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 1081 1082// ROTL 1083def : Pat<(rotl GPRC:$in, GPRC:$sh), 1084 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1085def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1086 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1087 1088// Hi and Lo for Darwin Global Addresses. 1089def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1090def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1091def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1092def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1093def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1094 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1095def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1096 (ADDIS GPRC:$in, tconstpool:$g)>; 1097 1098def : Pat<(fmul VRRC:$vA, VRRC:$vB), 1099 (VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>; 1100 1101// Fused negative multiply subtract, alternate pattern 1102def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), 1103 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>, 1104 Requires<[FPContractions]>; 1105def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)), 1106 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>, 1107 Requires<[FPContractions]>; 1108 1109// Fused multiply add and multiply sub for packed float. These are represented 1110// separately from the real instructions above, for operations that must have 1111// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 1112def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C), 1113 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>; 1114def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C), 1115 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>; 1116 1117// Standard shifts. These are represented separately from the real shifts above 1118// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1119// amounts. 1120def : Pat<(sra GPRC:$rS, GPRC:$rB), 1121 (SRAW GPRC:$rS, GPRC:$rB)>; 1122def : Pat<(srl GPRC:$rS, GPRC:$rB), 1123 (SRW GPRC:$rS, GPRC:$rB)>; 1124def : Pat<(shl GPRC:$rS, GPRC:$rB), 1125 (SLW GPRC:$rS, GPRC:$rB)>; 1126 1127def : Pat<(i32 (zextload iaddr:$src, i1)), 1128 (LBZ iaddr:$src)>; 1129def : Pat<(i32 (zextload xaddr:$src, i1)), 1130 (LBZX xaddr:$src)>; 1131def : Pat<(i32 (extload iaddr:$src, i1)), 1132 (LBZ iaddr:$src)>; 1133def : Pat<(i32 (extload xaddr:$src, i1)), 1134 (LBZX xaddr:$src)>; 1135def : Pat<(i32 (extload iaddr:$src, i8)), 1136 (LBZ iaddr:$src)>; 1137def : Pat<(i32 (extload xaddr:$src, i8)), 1138 (LBZX xaddr:$src)>; 1139def : Pat<(i32 (extload iaddr:$src, i16)), 1140 (LHZ iaddr:$src)>; 1141def : Pat<(i32 (extload xaddr:$src, i16)), 1142 (LHZX xaddr:$src)>; 1143def : Pat<(f64 (extload iaddr:$src, f32)), 1144 (FMRSD (LFS iaddr:$src))>; 1145def : Pat<(f64 (extload xaddr:$src, f32)), 1146 (FMRSD (LFSX xaddr:$src))>; 1147 1148def : Pat<(v4i32 (load xoaddr:$src)), 1149 (v4i32 (LVX xoaddr:$src))>; 1150def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst), 1151 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>; 1152 1153def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>; 1154 1155 1156// Same as above, but using a temporary. FIXME: implement temporaries :) 1157/* 1158def : Pattern<(xor GPRC:$in, imm:$imm), 1159 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))), 1160 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>; 1161*/ 1162 1163