PPCInstrInfo.td revision 6b4ea2cfa29be829a4003ac061f17c7942d617e2 
1
2//===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3// 
4//                     The LLVM Compiler Infrastructure
5//
6// This file was developed by the LLVM research group and is distributed under
7// the University of Illinois Open Source License. See LICENSE.TXT for details.
8// 
9//===----------------------------------------------------------------------===//
10//
11// This file describes the subset of the 32-bit PowerPC instruction set, as used
12// by the PowerPC instruction selector.
13//
14//===----------------------------------------------------------------------===//
15
16include "PowerPCInstrFormats.td"
17
18let isTerminator = 1 in {
19  let isReturn = 1 in
20    def BLR : XLForm_2_ext<19, 16, 20, 0, 0, 0, 0, (ops), "blr">;
21  def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, 0, 0, (ops), "bctr">;
22}
23
24def u5imm   : Operand<i8> {
25  let PrintMethod = "printU5ImmOperand";
26}
27def u6imm   : Operand<i8> {
28  let PrintMethod = "printU6ImmOperand";
29}
30def s16imm  : Operand<i16> {
31  let PrintMethod = "printS16ImmOperand";
32}
33def u16imm  : Operand<i16> {
34  let PrintMethod = "printU16ImmOperand";
35}
36def target : Operand<i32> {
37  let PrintMethod = "printBranchOperand";
38}
39def piclabel: Operand<i32> {
40  let PrintMethod = "printPICLabel";
41}
42def symbolHi: Operand<i32> {
43  let PrintMethod = "printSymbolHi";
44}
45def symbolLo: Operand<i32> {
46  let PrintMethod = "printSymbolLo";
47}
48
49// Pseudo-instructions:
50def PHI : Pseudo<(ops), "; PHI">;
51let isLoad = 1 in {
52def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
53def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
54}
55def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
56
57let Defs = [LR] in
58  def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
59
60let isBranch = 1, isTerminator = 1 in {
61  def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
62  def B   : IForm<18, 0, 0, 0, 0, (ops target:$func), "b $func">;
63//def BA  : IForm<18, 1, 0, 0, 0, (ops target:$func), "ba $func">;
64  def BL  : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
65//def BLA : IForm<18, 1, 1, 0, 0, (ops target:$func), "bla $func">;
66
67  // FIXME: 4*CR# needs to be added to the BI field!
68  // This will only work for CR0 as it stands now
69  def BLT : BForm_ext<16, 0, 0, 12, 0, 0, 0, (ops CRRC:$crS, target:$block),
70                      "blt $block">;
71  def BLE : BForm_ext<16, 0, 0, 4,  1, 0, 0, (ops CRRC:$crS, target:$block),
72                      "ble $block">;
73  def BEQ : BForm_ext<16, 0, 0, 12, 2, 0, 0, (ops CRRC:$crS, target:$block),
74                      "beq $block">;
75  def BGE : BForm_ext<16, 0, 0, 4,  0, 0, 0, (ops CRRC:$crS, target:$block),
76                      "bge $block">;
77  def BGT : BForm_ext<16, 0, 0, 12, 1, 0, 0, (ops CRRC:$crS, target:$block),
78                      "bgt $block">;
79  def BNE : BForm_ext<16, 0, 0, 4,  2, 0, 0, (ops CRRC:$crS, target:$block),
80                      "bne $block">;
81}
82
83let isBranch = 1, isTerminator = 1, isCall = 1, 
84  // All calls clobber the non-callee saved registers...
85  Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
86          F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
87          LR,XER,CTR,
88          CR0,CR1,CR5,CR6,CR7] in {
89  // Convenient aliases for call instructions
90  def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
91  def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, 0, 0, (ops), "bctrl">;
92}
93
94// D-Form instructions.  Most instructions that perform an operation on a
95// register and an immediate are of this type.
96//
97let isLoad = 1 in {
98def LBZ : DForm_1<34, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
99                  "lbz $rD, $disp($rA)">;
100def LHA : DForm_1<42, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
101                  "lha $rD, $disp($rA)">;
102def LHZ : DForm_1<40, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
103                  "lhz $rD, $disp($rA)">;
104def LMW : DForm_1<46, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
105                  "lmw $rD, $disp($rA)">;
106def LWZ : DForm_1<32, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
107                  "lwz $rD, $disp($rA)">;
108def LWZU : DForm_1<35, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
109                   "lwzu $rD, $disp($rA)">;
110}
111def ADDI   : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
112                     "addi $rD, $rA, $imm">;
113def ADDIC  : DForm_2<12, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
114                     "addic $rD, $rA, $imm">;
115def ADDICo : DForm_2<13, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
116                     "addic. $rD, $rA, $imm">;
117def ADDIS  : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
118                     "addis $rD, $rA, $imm">;
119def LA     : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
120                     "la $rD, $sym($rA)">;
121def LOADHiAddr : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
122                         "addis $rD, $rA, $sym">;
123def MULLI  : DForm_2< 7, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
124                     "mulli $rD, $rA, $imm">;
125def SUBFIC : DForm_2< 8, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
126                     "subfic $rD, $rA, $imm">;
127def LI  : DForm_2_r0<14, 0, 0, (ops GPRC:$rD, s16imm:$imm),
128                     "li $rD, $imm">;
129def LIS : DForm_2_r0<15, 0, 0, (ops GPRC:$rD, s16imm:$imm),
130                     "lis $rD, $imm">;
131let isStore = 1 in {
132def STMW : DForm_3<47, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
133                   "stmw $rS, $disp($rA)">;
134def STB  : DForm_3<38, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
135                   "stb $rS, $disp($rA)">;
136def STH  : DForm_3<44, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
137                   "sth $rS, $disp($rA)">;
138def STW  : DForm_3<36, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
139                   "stw $rS, $disp($rA)">;
140def STWU : DForm_3<37, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
141                   "stwu $rS, $disp($rA)">;
142}
143let Defs = [CR0] in {
144def ANDIo : DForm_4<28, 0, 0,
145                    (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
146                    "andi. $dst, $src1, $src2">;
147def ANDISo : DForm_4<29, 0, 0,
148                    (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
149                    "andis. $dst, $src1, $src2">;
150}
151def ORI   : DForm_4<24, 0, 0,
152                    (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
153                    "ori $dst, $src1, $src2">;
154def ORIS  : DForm_4<25, 0, 0,
155                    (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
156                    "oris $dst, $src1, $src2">;
157def XORI  : DForm_4<26, 0, 0,
158                    (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
159                    "xori $dst, $src1, $src2">;
160def XORIS : DForm_4<27, 0, 0,
161                    (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
162                    "xoris $dst, $src1, $src2">;
163def NOP   : DForm_4_zero<24, 0, 0, (ops), "nop">;
164def CMPI  : DForm_5<11, 0, 0, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
165                    "cmpi $crD, $L, $rA, $imm">;
166def CMPWI : DForm_5_ext<11, 0, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
167                        "cmpwi $crD, $rA, $imm">;
168def CMPDI : DForm_5_ext<11, 1, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
169                        "cmpdi $crD, $rA, $imm">;
170def CMPLI  : DForm_6<10, 0, 0,
171                     (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
172                     "cmpli $dst, $size, $src1, $src2">;
173def CMPLWI : DForm_6_ext<10, 0, 0,
174                         (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
175                         "cmplwi $dst, $src1, $src2">;
176def CMPLDI : DForm_6_ext<10, 1, 0,
177                         (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
178                         "cmpldi $dst, $src1, $src2">;
179let isLoad = 1 in {
180def LFS : DForm_8<48, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
181                  "lfs $rD, $disp($rA)">;
182def LFD : DForm_8<50, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
183                  "lfd $rD, $disp($rA)">;
184}
185let isStore = 1 in {
186def STFS : DForm_9<52, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
187                   "stfs $rS, $disp($rA)">;
188def STFD : DForm_9<54, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
189                   "stfd $rS, $disp($rA)">;
190}
191
192// DS-Form instructions.  Load/Store instructions available in PPC-64
193//
194let isLoad = 1 in {
195def LWA  : DSForm_1<58, 2, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
196                    "lwa $rT, $DS($rA)">;
197def LD   : DSForm_2<58, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
198                    "ld $rT, $DS($rA)">;
199}
200let isStore = 1 in {
201def STD  : DSForm_2<62, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
202                    "std $rT, $DS($rA)">;
203def STDU : DSForm_2<62, 1, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
204                    "stdu $rT, $DS($rA)">;
205}
206
207// X-Form instructions.  Most instructions that perform an operation on a
208// register and another register are of this type.
209//
210let isLoad = 1 in {
211def LBZX : XForm_1<31,  87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
212                   "lbzx $dst, $base, $index">;
213def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
214                   "lhax $dst, $base, $index">;
215def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
216                   "lhzx $dst, $base, $index">;
217def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
218                   "lwax $dst, $base, $index">;
219def LWZX : XForm_1<31,  23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
220                   "lwzx $dst, $base, $index">;
221def LDX  : XForm_1<31,  21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
222                   "ldx $dst, $base, $index">;
223}
224def MFCR : XForm_5<31,  19, 0, 0, (ops GPRC:$dst), "mfcr $dst">;
225def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
226                   "and $rA, $rS, $rB">;
227let Defs = [CR0] in
228def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
229                   "and. $rA, $rS, $rB">;
230def ANDC : XForm_6<31,  60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
231                   "andc $rA, $rS, $rB">;
232def EQV  : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
233                   "eqv $rA, $rS, $rB">;
234def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
235                   "nand $rA, $rS, $rB">;
236def NOR  : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
237                   "nor $rA, $rS, $rB">;
238def OR   : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
239                   "or $rA, $rS, $rB">;
240def ORo  : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
241                   "or. $rA, $rS, $rB">;
242def ORC  : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
243                   "orc $rA, $rS, $rB">;
244def SLD  : XForm_6<31,  27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
245                   "sld $rA, $rS, $rB">;
246def SLW  : XForm_6<31,  24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
247                   "slw $rA, $rS, $rB">;
248def SRD  : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
249                   "srd $rA, $rS, $rB">;
250def SRW  : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
251                   "srw $rA, $rS, $rB">;
252def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
253                   "srad $rA, $rS, $rB">;
254def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
255                   "sraw $rA, $rS, $rB">;
256def XOR  : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
257                   "xor $rA, $rS, $rB">;
258let isStore = 1 in {
259def STBX  : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
260                   "stbx $rS, $rA, $rB">;
261def STHX  : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
262                   "sthx $rS, $rA, $rB">;
263def STWX  : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
264                   "stwx $rS, $rA, $rB">;
265def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
266                   "stwux $rS, $rA, $rB">;
267def STDX  : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
268                   "stdx $rS, $rA, $rB">;
269def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
270                   "stdux $rS, $rA, $rB">;
271}
272def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), 
273                     "srawi $rA, $rS, $SH">;
274def CNTLZW : XForm_11<31,  26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
275                      "cntlzw $rA, $rS">;
276def EXTSB  : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
277                      "extsb $rA, $rS">;
278def EXTSH  : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
279                      "extsh $rA, $rS">;
280def EXTSW  : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
281                      "extsw $rA, $rS">;
282def CMP    : XForm_16<31, 0, 0, 0,
283                      (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
284                      "cmp $crD, $long, $rA, $rB">;
285def CMPL   : XForm_16<31, 32, 0, 0,
286                      (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
287                      "cmpl $crD, $long, $rA, $rB">;
288def CMPW   : XForm_16_ext<31, 0, 0, 0,
289                          (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
290                          "cmpw $crD, $rA, $rB">;
291def CMPD   : XForm_16_ext<31, 0, 1, 0,
292                          (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
293                          "cmpd $crD, $rA, $rB">;
294def CMPLW  : XForm_16_ext<31, 32, 0, 0,
295                          (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
296                          "cmplw $crD, $rA, $rB">;
297def CMPLD  : XForm_16_ext<31, 32, 1, 0,
298                          (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
299                          "cmpld $crD, $rA, $rB">;
300def FCMPO  : XForm_17<63, 32, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
301                      "fcmpo $crD, $fA, $fB">;
302def FCMPU  : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
303                      "fcmpu $crD, $fA, $fB">;
304let isLoad = 1 in {
305def LFSX   : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
306                      "lfsx $dst, $base, $index">;
307def LFDX   : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
308                      "lfdx $dst, $base, $index">;
309}
310def FCFID  : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
311                      "fcfid $frD, $frB">;
312def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
313                      "fctidz $frD, $frB">;
314def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
315                      "fctiwz $frD, $frB">;
316def FABS   : XForm_26<63, 264, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
317                      "fabs $frD, $frB">;
318def FMR    : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
319                      "fmr $frD, $frB">;
320def FNABS  : XForm_26<63, 136, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
321                      "fnabs $frD, $frB">;
322def FNEG   : XForm_26<63, 40, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
323                      "fneg $frD, $frB">;
324def FRSP   : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
325                      "frsp $frD, $frB">;
326let isStore = 1 in {
327def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
328                     "stfsx $frS, $rA, $rB">;
329def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
330                     "stfdx $frS, $rA, $rB">;
331}
332
333// XL-Form instructions.  condition register logical ops.
334//
335def CRAND  : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
336                      "crand $D, $A, $B">;
337def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
338                      "crandc $D, $A, $B">;
339def CRNOR  : XLForm_1<19,  33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
340                      "crnor $D, $A, $B">;
341def CROR   : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
342                      "cror $D, $A, $B">;
343
344// XFX-Form instructions.  Instructions that deal with SPRs
345//
346// Note that although LR should be listed as `8' and CTR as `9' in the SPR
347// field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
348// which means the SPR value needs to be multiplied by a factor of 32.
349def MFCTR : XFXForm_1_ext<31, 339, 288, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
350def MFLR  : XFXForm_1_ext<31, 339, 256, 0, 0, (ops GPRC:$rT), "mflr $rT">;
351def MTCTR : XFXForm_7_ext<31, 467, 288, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
352def MTLR  : XFXForm_7_ext<31, 467, 256, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
353
354
355// XS-Form instructions.  Just 'sradi'
356//
357def SRADI  : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
358                      "sradi $rA, $rS, $SH">;
359
360// XO-Form instructions.  Arithmetic instructions that can set overflow bit
361//
362def ADD   : XOForm_1<31, 266, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
363                     "add $rT, $rA, $rB">;
364def ADDC  : XOForm_1<31, 10, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
365                     "addc $rT, $rA, $rB">;
366def ADDE  : XOForm_1<31, 138, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
367                     "adde $rT, $rA, $rB">;
368def DIVD  : XOForm_1<31, 489, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
369                     "divd $rT, $rA, $rB">;
370def DIVDU : XOForm_1<31, 457, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
371                     "divdu $rT, $rA, $rB">;
372def DIVW  : XOForm_1<31, 491, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
373                     "divw $rT, $rA, $rB">;
374def DIVWU : XOForm_1<31, 459, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
375                     "divwu $rT, $rA, $rB">;
376def MULHW : XOForm_1<31, 75, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
377                     "mulhw $rT, $rA, $rB">;
378def MULHWU : XOForm_1<31, 11, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
379                     "mulhwu $rT, $rA, $rB">;
380def MULLD : XOForm_1<31, 233, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
381                     "mulld $rT, $rA, $rB">;
382def MULLW : XOForm_1<31, 235, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
383                     "mullw $rT, $rA, $rB">;
384def SUBF  : XOForm_1<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
385                     "subf $rT, $rA, $rB">;
386def SUBFC : XOForm_1<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
387                     "subfc $rT, $rA, $rB">;
388def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
389                     "subfe $rT, $rA, $rB">;
390def SUB  : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
391                     "sub $rT, $rA, $rB">;
392def ADDME  : XOForm_3<31, 234, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
393                      "addme $rT, $rA">;
394def ADDZE  : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
395                      "addze $rT, $rA">;
396def NEG    : XOForm_3<31, 104, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
397                      "neg $rT, $rA">;
398def SUBFZE : XOForm_3<31, 200, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
399                      "subfze $rT, $rA">;
400
401// A-Form instructions.  Most of the instructions executed in the FPU are of
402// this type.
403//
404def FMADD : AForm_1<63, 29, 0, 0, 0,
405                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
406                    "fmadd $FRT, $FRA, $FRC, $FRB">;
407def FMADDS : AForm_1<59, 29, 0, 0, 0,
408                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
409                    "fmadds $FRT, $FRA, $FRC, $FRB">;
410def FMSUB : AForm_1<63, 28, 0, 0, 0,
411                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
412                    "fmsub $FRT, $FRA, $FRC, $FRB">;
413def FMSUBS : AForm_1<59, 28, 0, 0, 0,
414                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
415                    "fmsubs $FRT, $FRA, $FRC, $FRB">;
416def FNMADD : AForm_1<63, 31, 0, 0, 0,
417                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
418                    "fnmadd $FRT, $FRA, $FRC, $FRB">;
419def FNMADDS : AForm_1<59, 31, 0, 0, 0,
420                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
421                    "fnmadds $FRT, $FRA, $FRC, $FRB">;
422def FNMSUB : AForm_1<63, 30, 0, 0, 0,
423                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
424                    "fnmsub $FRT, $FRA, $FRC, $FRB">;
425def FNMSUBS : AForm_1<59, 30, 0, 0, 0,
426                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
427                    "fnmsubs $FRT, $FRA, $FRC, $FRB">;
428def FSEL  : AForm_1<63, 23, 0, 0, 0,
429                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
430                    "fsel $FRT, $FRA, $FRC, $FRB">;
431def FADD  : AForm_2<63, 21, 0, 0, 0,
432                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
433                    "fadd $FRT, $FRA, $FRB">;
434def FADDS : AForm_2<59, 21, 0, 0, 0,
435                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
436                    "fadds $FRT, $FRA, $FRB">;
437def FDIV  : AForm_2<63, 18, 0, 0, 0,
438                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
439                    "fdiv $FRT, $FRA, $FRB">;
440def FDIVS : AForm_2<59, 18, 0, 0, 0,
441                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
442                    "fdivs $FRT, $FRA, $FRB">;
443def FMUL  : AForm_3<63, 25, 0, 0, 0,
444                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
445                    "fmul $FRT, $FRA, $FRB">;
446def FMULS : AForm_3<59, 25, 0, 0, 0,
447                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
448                    "fmuls $FRT, $FRA, $FRB">;
449def FSUB  : AForm_2<63, 20, 0, 0, 0,
450                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
451                    "fsub $FRT, $FRA, $FRB">;
452def FSUBS : AForm_2<59, 20, 0, 0, 0,
453                    (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
454                    "fsubs $FRT, $FRA, $FRB">;
455
456// M-Form instructions.  rotate and mask instructions.
457//
458let isTwoAddress = 1 in {
459def RLWIMI : MForm_2<20, 0, 0, 0,
460                     (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 
461                      u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
462}
463def RLWINM : MForm_2<21, 0, 0, 0,
464                     (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
465                     "rlwinm $rA, $rS, $SH, $MB, $ME">;
466def RLWNM  : MForm_2<23, 0, 0, 0,
467                     (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
468                     "rlwnm $rA, $rS, $rB, $MB, $ME">;
469
470// MD-Form instructions.  64 bit rotate instructions.
471//
472def RLDICL : MDForm_1<30, 0, 0, 1, 0, 
473                      (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
474                      "rldicl $rA, $rS, $SH, $MB">;
475def RLDICR : MDForm_1<30, 1, 0, 1, 0, 
476                      (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
477                      "rldicr $rA, $rS, $SH, $ME">;
478
479def PowerPCInstrInfo : InstrInfo {
480  let PHIInst  = PHI;
481
482  let TSFlagsFields = [ "VMX", "PPC64" ];
483  let TSFlagsShifts = [ 0, 1 ];
484
485  let isLittleEndianEncoding = 1;
486}
487
488