PPCInstrInfo.td revision 7049540de55741611545829ad47572432a187771
1//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl 24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32> 25]>; 26def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 27 28def SDT_PPCvperm : SDTypeProfile<1, 3, [ 29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 30]>; 31 32def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 34]>; 35 36def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 37 SDTCisVT<1, i32>, SDTCisVT<2, OtherVT> 38]>; 39 40def SDT_PPClbrx : SDTypeProfile<1, 3, [ 41 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> 42]>; 43def SDT_PPCstbrx : SDTypeProfile<0, 4, [ 44 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> 45]>; 46 47//===----------------------------------------------------------------------===// 48// PowerPC specific DAG Nodes. 49// 50 51def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 52def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 53def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 54def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>; 55 56def PPCfsel : SDNode<"PPCISD::FSEL", 57 // Type constraint for fsel. 58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 59 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 60 61def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 62def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 63def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 64def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 65 66def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 67 68// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 69// amounts. These nodes are generated by the multi-precision shift code. 70def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>; 71def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>; 72def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>; 73 74def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 75def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq, 79 [SDNPHasChain, SDNPOutFlag]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq, 81 [SDNPHasChain, SDNPOutFlag]>; 82 83def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 84def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 85 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 86def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 87 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 88def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet, 89 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 90 91def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet, 92 [SDNPHasChain, SDNPOptInFlag]>; 93 94def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 95def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>; 96 97def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 98 [SDNPHasChain, SDNPOptInFlag]>; 99 100def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>; 101def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>; 102 103//===----------------------------------------------------------------------===// 104// PowerPC specific transformation functions and pattern fragments. 105// 106 107def SHL32 : SDNodeXForm<imm, [{ 108 // Transformation function: 31 - imm 109 return getI32Imm(31 - N->getValue()); 110}]>; 111 112def SRL32 : SDNodeXForm<imm, [{ 113 // Transformation function: 32 - imm 114 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0); 115}]>; 116 117def LO16 : SDNodeXForm<imm, [{ 118 // Transformation function: get the low 16 bits. 119 return getI32Imm((unsigned short)N->getValue()); 120}]>; 121 122def HI16 : SDNodeXForm<imm, [{ 123 // Transformation function: shift the immediate value down into the low bits. 124 return getI32Imm((unsigned)N->getValue() >> 16); 125}]>; 126 127def HA16 : SDNodeXForm<imm, [{ 128 // Transformation function: shift the immediate value down into the low bits. 129 signed int Val = N->getValue(); 130 return getI32Imm((Val - (signed short)Val) >> 16); 131}]>; 132def MB : SDNodeXForm<imm, [{ 133 // Transformation function: get the start bit of a mask 134 unsigned mb, me; 135 (void)isRunOfOnes((unsigned)N->getValue(), mb, me); 136 return getI32Imm(mb); 137}]>; 138 139def ME : SDNodeXForm<imm, [{ 140 // Transformation function: get the end bit of a mask 141 unsigned mb, me; 142 (void)isRunOfOnes((unsigned)N->getValue(), mb, me); 143 return getI32Imm(me); 144}]>; 145def maskimm32 : PatLeaf<(imm), [{ 146 // maskImm predicate - True if immediate is a run of ones. 147 unsigned mb, me; 148 if (N->getValueType(0) == MVT::i32) 149 return isRunOfOnes((unsigned)N->getValue(), mb, me); 150 else 151 return false; 152}]>; 153 154def immSExt16 : PatLeaf<(imm), [{ 155 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 156 // field. Used by instructions like 'addi'. 157 if (N->getValueType(0) == MVT::i32) 158 return (int32_t)N->getValue() == (short)N->getValue(); 159 else 160 return (int64_t)N->getValue() == (short)N->getValue(); 161}]>; 162def immZExt16 : PatLeaf<(imm), [{ 163 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 164 // field. Used by instructions like 'ori'. 165 return (uint64_t)N->getValue() == (unsigned short)N->getValue(); 166}], LO16>; 167 168// imm16Shifted* - These match immediates where the low 16-bits are zero. There 169// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 170// identical in 32-bit mode, but in 64-bit mode, they return true if the 171// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 172// clear). 173def imm16ShiftedZExt : PatLeaf<(imm), [{ 174 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 175 // immediate are set. Used by instructions like 'xoris'. 176 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0; 177}], HI16>; 178 179def imm16ShiftedSExt : PatLeaf<(imm), [{ 180 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 181 // immediate are set. Used by instructions like 'addis'. Identical to 182 // imm16ShiftedZExt in 32-bit mode. 183 if (N->getValue() & 0xFFFF) return false; 184 if (N->getValueType(0) == MVT::i32) 185 return true; 186 // For 64-bit, make sure it is sext right. 187 return N->getValue() == (uint64_t)(int)N->getValue(); 188}], HI16>; 189 190 191//===----------------------------------------------------------------------===// 192// PowerPC Flag Definitions. 193 194class isPPC64 { bit PPC64 = 1; } 195class isDOT { 196 list<Register> Defs = [CR0]; 197 bit RC = 1; 198} 199 200 201 202//===----------------------------------------------------------------------===// 203// PowerPC Operand Definitions. 204 205def s5imm : Operand<i32> { 206 let PrintMethod = "printS5ImmOperand"; 207} 208def u5imm : Operand<i32> { 209 let PrintMethod = "printU5ImmOperand"; 210} 211def u6imm : Operand<i32> { 212 let PrintMethod = "printU6ImmOperand"; 213} 214def s16imm : Operand<i32> { 215 let PrintMethod = "printS16ImmOperand"; 216} 217def u16imm : Operand<i32> { 218 let PrintMethod = "printU16ImmOperand"; 219} 220def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 221 let PrintMethod = "printS16X4ImmOperand"; 222} 223def target : Operand<OtherVT> { 224 let PrintMethod = "printBranchOperand"; 225} 226def calltarget : Operand<iPTR> { 227 let PrintMethod = "printCallOperand"; 228} 229def aaddr : Operand<iPTR> { 230 let PrintMethod = "printAbsAddrOperand"; 231} 232def piclabel: Operand<iPTR> { 233 let PrintMethod = "printPICLabel"; 234} 235def symbolHi: Operand<i32> { 236 let PrintMethod = "printSymbolHi"; 237} 238def symbolLo: Operand<i32> { 239 let PrintMethod = "printSymbolLo"; 240} 241def crbitm: Operand<i8> { 242 let PrintMethod = "printcrbitm"; 243} 244// Address operands 245def memri : Operand<iPTR> { 246 let PrintMethod = "printMemRegImm"; 247 let MIOperandInfo = (ops i32imm, ptr_rc); 248} 249def memrr : Operand<iPTR> { 250 let PrintMethod = "printMemRegReg"; 251 let MIOperandInfo = (ops ptr_rc, ptr_rc); 252} 253def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 254 let PrintMethod = "printMemRegImmShifted"; 255 let MIOperandInfo = (ops i32imm, ptr_rc); 256} 257 258// Define PowerPC specific addressing mode. 259def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 260def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 261def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 262def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 263 264//===----------------------------------------------------------------------===// 265// PowerPC Instruction Predicate Definitions. 266def FPContractions : Predicate<"!NoExcessFPPrecision">; 267 268//===----------------------------------------------------------------------===// 269// PowerPC Instruction Definitions. 270 271// Pseudo-instructions: 272 273let hasCtrlDep = 1 in { 274def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), 275 "${:comment} ADJCALLSTACKDOWN", 276 [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>; 277def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), 278 "${:comment} ADJCALLSTACKUP", 279 [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>; 280 281def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS), 282 "UPDATE_VRSAVE $rD, $rS", []>; 283} 284def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD),"${:comment}IMPLICIT_DEF_GPRC $rD", 285 [(set GPRC:$rD, (undef))]>; 286def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "${:comment} IMPLICIT_DEF_F8 $rD", 287 [(set F8RC:$rD, (undef))]>; 288def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "${:comment} IMPLICIT_DEF_F4 $rD", 289 [(set F4RC:$rD, (undef))]>; 290 291// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 292// scheduler into a branch sequence. 293let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler. 294 PPC970_Single = 1 in { 295 def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F, 296 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 297 []>; 298 def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F, 299 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 300 []>; 301 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F, 302 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 303 []>; 304 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F, 305 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 306 []>; 307 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F, 308 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 309 []>; 310} 311 312let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in { 313 let isReturn = 1 in 314 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>; 315 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>; 316} 317 318let Defs = [LR] in 319 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>, 320 PPC970_Unit_BRU; 321 322let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, 323 noResults = 1, PPC970_Unit = 7 in { 324 // COND_BRANCH is formed before branch selection, it is turned into Bcc below. 325 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst), 326 "${:comment} COND_BRANCH $crS, $opc, $dst", 327 [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>; 328 let isBarrier = 1 in { 329 def B : IForm<18, 0, 0, (ops target:$dst), 330 "b $dst", BrB, 331 [(br bb:$dst)]>; 332 } 333 334 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block), 335 "blt $crS, $block", BrB>; 336 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block), 337 "ble $crS, $block", BrB>; 338 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block), 339 "beq $crS, $block", BrB>; 340 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block), 341 "bge $crS, $block", BrB>; 342 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block), 343 "bgt $crS, $block", BrB>; 344 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block), 345 "bne $crS, $block", BrB>; 346 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block), 347 "bun $crS, $block", BrB>; 348 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block), 349 "bnu $crS, $block", BrB>; 350} 351 352let isCall = 1, noResults = 1, PPC970_Unit = 7, 353 // All calls clobber the non-callee saved registers... 354 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 355 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 356 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 357 LR,CTR, 358 CR0,CR1,CR5,CR6,CR7] in { 359 // Convenient aliases for call instructions 360 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops), 361 "bl $func", BrB, []>; // See Pat patterns below. 362 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), 363 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>; 364 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB, 365 [(PPCbctrl)]>; 366} 367 368// DCB* instructions. 369def DCBA : DCB_Form<758, 0, (ops memrr:$dst), 370 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 371 PPC970_DGroup_Single; 372def DCBF : DCB_Form<86, 0, (ops memrr:$dst), 373 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 374 PPC970_DGroup_Single; 375def DCBI : DCB_Form<470, 0, (ops memrr:$dst), 376 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 377 PPC970_DGroup_Single; 378def DCBST : DCB_Form<54, 0, (ops memrr:$dst), 379 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 380 PPC970_DGroup_Single; 381def DCBT : DCB_Form<278, 0, (ops memrr:$dst), 382 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 383 PPC970_DGroup_Single; 384def DCBTST : DCB_Form<246, 0, (ops memrr:$dst), 385 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 386 PPC970_DGroup_Single; 387def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst), 388 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 389 PPC970_DGroup_Single; 390def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst), 391 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 392 PPC970_DGroup_Single; 393 394// D-Form instructions. Most instructions that perform an operation on a 395// register and an immediate are of this type. 396// 397let isLoad = 1, PPC970_Unit = 2 in { 398def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src), 399 "lbz $rD, $src", LdStGeneral, 400 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 401def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src), 402 "lha $rD, $src", LdStLHA, 403 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, 404 PPC970_DGroup_Cracked; 405def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src), 406 "lhz $rD, $src", LdStGeneral, 407 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; 408def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src), 409 "lwz $rD, $src", LdStGeneral, 410 [(set GPRC:$rD, (load iaddr:$src))]>; 411def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA), 412 "lwzu $rD, $disp($rA)", LdStGeneral, 413 []>; 414} 415let PPC970_Unit = 1 in { // FXU Operations. 416def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 417 "addi $rD, $rA, $imm", IntGeneral, 418 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 419def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 420 "addic $rD, $rA, $imm", IntGeneral, 421 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 422 PPC970_DGroup_Cracked; 423def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 424 "addic. $rD, $rA, $imm", IntGeneral, 425 []>; 426def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm), 427 "addis $rD, $rA, $imm", IntGeneral, 428 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; 429def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym), 430 "la $rD, $sym($rA)", IntGeneral, 431 [(set GPRC:$rD, (add GPRC:$rA, 432 (PPClo tglobaladdr:$sym, 0)))]>; 433def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 434 "mulli $rD, $rA, $imm", IntMulLI, 435 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 436def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 437 "subfic $rD, $rA, $imm", IntGeneral, 438 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 439def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm), 440 "li $rD, $imm", IntGeneral, 441 [(set GPRC:$rD, immSExt16:$imm)]>; 442def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm), 443 "lis $rD, $imm", IntGeneral, 444 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; 445} 446let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 447def STB : DForm_3<38, (ops GPRC:$rS, memri:$src), 448 "stb $rS, $src", LdStGeneral, 449 [(truncstorei8 GPRC:$rS, iaddr:$src)]>; 450def STH : DForm_3<44, (ops GPRC:$rS, memri:$src), 451 "sth $rS, $src", LdStGeneral, 452 [(truncstorei16 GPRC:$rS, iaddr:$src)]>; 453def STW : DForm_3<36, (ops GPRC:$rS, memri:$src), 454 "stw $rS, $src", LdStGeneral, 455 [(store GPRC:$rS, iaddr:$src)]>; 456def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 457 "stwu $rS, $disp($rA)", LdStGeneral, 458 []>; 459} 460let PPC970_Unit = 1 in { // FXU Operations. 461def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 462 "andi. $dst, $src1, $src2", IntGeneral, 463 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 464 isDOT; 465def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 466 "andis. $dst, $src1, $src2", IntGeneral, 467 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, 468 isDOT; 469def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 470 "ori $dst, $src1, $src2", IntGeneral, 471 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 472def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 473 "oris $dst, $src1, $src2", IntGeneral, 474 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; 475def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 476 "xori $dst, $src1, $src2", IntGeneral, 477 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 478def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 479 "xoris $dst, $src1, $src2", IntGeneral, 480 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; 481def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral, 482 []>; 483def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 484 "cmpwi $crD, $rA, $imm", IntCompare>; 485def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 486 "cmplwi $dst, $src1, $src2", IntCompare>; 487} 488let isLoad = 1, PPC970_Unit = 2 in { 489def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src), 490 "lfs $rD, $src", LdStLFDU, 491 [(set F4RC:$rD, (load iaddr:$src))]>; 492def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src), 493 "lfd $rD, $src", LdStLFD, 494 [(set F8RC:$rD, (load iaddr:$src))]>; 495} 496let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 497def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst), 498 "stfs $rS, $dst", LdStUX, 499 [(store F4RC:$rS, iaddr:$dst)]>; 500def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst), 501 "stfd $rS, $dst", LdStUX, 502 [(store F8RC:$rS, iaddr:$dst)]>; 503} 504 505// X-Form instructions. Most instructions that perform an operation on a 506// register and another register are of this type. 507// 508let isLoad = 1, PPC970_Unit = 2 in { 509def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src), 510 "lbzx $rD, $src", LdStGeneral, 511 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; 512def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src), 513 "lhax $rD, $src", LdStLHA, 514 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, 515 PPC970_DGroup_Cracked; 516def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src), 517 "lhzx $rD, $src", LdStGeneral, 518 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; 519def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src), 520 "lwzx $rD, $src", LdStGeneral, 521 [(set GPRC:$rD, (load xaddr:$src))]>; 522 523 524def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src), 525 "lhbrx $rD, $src", LdStGeneral, 526 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>; 527def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src), 528 "lwbrx $rD, $src", LdStGeneral, 529 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>; 530 531} 532 533let PPC970_Unit = 1 in { // FXU Operations. 534def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 535 "nand $rA, $rS, $rB", IntGeneral, 536 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 537def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 538 "and $rA, $rS, $rB", IntGeneral, 539 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 540def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 541 "andc $rA, $rS, $rB", IntGeneral, 542 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 543def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 544 "or $rA, $rS, $rB", IntGeneral, 545 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 546def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 547 "nor $rA, $rS, $rB", IntGeneral, 548 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 549def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 550 "orc $rA, $rS, $rB", IntGeneral, 551 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 552def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 553 "eqv $rA, $rS, $rB", IntGeneral, 554 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 555def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 556 "xor $rA, $rS, $rB", IntGeneral, 557 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 558def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 559 "slw $rA, $rS, $rB", IntGeneral, 560 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 561def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 562 "srw $rA, $rS, $rB", IntGeneral, 563 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 564def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 565 "sraw $rA, $rS, $rB", IntShift, 566 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 567} 568let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 569def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst), 570 "stbx $rS, $dst", LdStGeneral, 571 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, 572 PPC970_DGroup_Cracked; 573def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst), 574 "sthx $rS, $dst", LdStGeneral, 575 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, 576 PPC970_DGroup_Cracked; 577def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst), 578 "stwx $rS, $dst", LdStGeneral, 579 [(store GPRC:$rS, xaddr:$dst)]>, 580 PPC970_DGroup_Cracked; 581def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 582 "stwux $rS, $rA, $rB", LdStGeneral, 583 []>; 584def STHBRX: XForm_8<31, 918, (ops GPRC:$rS, memrr:$dst), 585 "sthbrx $rS, $dst", LdStGeneral, 586 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>, 587 PPC970_DGroup_Cracked; 588def STWBRX: XForm_8<31, 662, (ops GPRC:$rS, memrr:$dst), 589 "stwbrx $rS, $dst", LdStGeneral, 590 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>, 591 PPC970_DGroup_Cracked; 592} 593let PPC970_Unit = 1 in { // FXU Operations. 594def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), 595 "srawi $rA, $rS, $SH", IntShift, 596 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 597def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS), 598 "cntlzw $rA, $rS", IntGeneral, 599 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 600def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS), 601 "extsb $rA, $rS", IntGeneral, 602 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 603def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS), 604 "extsh $rA, $rS", IntGeneral, 605 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 606 607def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 608 "cmpw $crD, $rA, $rB", IntCompare>; 609def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 610 "cmplw $crD, $rA, $rB", IntCompare>; 611} 612let PPC970_Unit = 3 in { // FPU Operations. 613//def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB), 614// "fcmpo $crD, $fA, $fB", FPCompare>; 615def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB), 616 "fcmpu $crD, $fA, $fB", FPCompare>; 617def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB), 618 "fcmpu $crD, $fA, $fB", FPCompare>; 619} 620let isLoad = 1, PPC970_Unit = 2 in { 621def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src), 622 "lfsx $frD, $src", LdStLFDU, 623 [(set F4RC:$frD, (load xaddr:$src))]>; 624def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src), 625 "lfdx $frD, $src", LdStLFDU, 626 [(set F8RC:$frD, (load xaddr:$src))]>; 627} 628let PPC970_Unit = 3 in { // FPU Operations. 629def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB), 630 "fctiwz $frD, $frB", FPGeneral, 631 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 632def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB), 633 "frsp $frD, $frB", FPGeneral, 634 [(set F4RC:$frD, (fround F8RC:$frB))]>; 635def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB), 636 "fsqrt $frD, $frB", FPSqrt, 637 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 638def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB), 639 "fsqrts $frD, $frB", FPSqrt, 640 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 641} 642 643/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending. 644/// 645/// Note that these are defined as pseudo-ops on the PPC970 because they are 646/// often coalesced away and we don't want the dispatch group builder to think 647/// that they will fill slots (which could cause the load of a LSU reject to 648/// sneak into a d-group with a store). 649def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB), 650 "fmr $frD, $frB", FPGeneral, 651 []>, // (set F4RC:$frD, F4RC:$frB) 652 PPC970_Unit_Pseudo; 653def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB), 654 "fmr $frD, $frB", FPGeneral, 655 []>, // (set F8RC:$frD, F8RC:$frB) 656 PPC970_Unit_Pseudo; 657def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB), 658 "fmr $frD, $frB", FPGeneral, 659 [(set F8RC:$frD, (fextend F4RC:$frB))]>, 660 PPC970_Unit_Pseudo; 661 662let PPC970_Unit = 3 in { // FPU Operations. 663// These are artificially split into two different forms, for 4/8 byte FP. 664def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB), 665 "fabs $frD, $frB", FPGeneral, 666 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 667def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB), 668 "fabs $frD, $frB", FPGeneral, 669 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 670def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB), 671 "fnabs $frD, $frB", FPGeneral, 672 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 673def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB), 674 "fnabs $frD, $frB", FPGeneral, 675 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 676def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB), 677 "fneg $frD, $frB", FPGeneral, 678 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 679def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB), 680 "fneg $frD, $frB", FPGeneral, 681 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 682} 683 684let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 685def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst), 686 "stfiwx $frS, $dst", LdStUX, 687 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 688def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst), 689 "stfsx $frS, $dst", LdStUX, 690 [(store F4RC:$frS, xaddr:$dst)]>; 691def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst), 692 "stfdx $frS, $dst", LdStUX, 693 [(store F8RC:$frS, xaddr:$dst)]>; 694} 695 696// XL-Form instructions. condition register logical ops. 697// 698def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA), 699 "mcrf $BF, $BFA", BrMCR>, 700 PPC970_DGroup_First, PPC970_Unit_CRU; 701 702// XFX-Form instructions. Instructions that deal with SPRs. 703// 704def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>, 705 PPC970_DGroup_First, PPC970_Unit_FXU; 706let Pattern = [(PPCmtctr GPRC:$rS)] in { 707def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>, 708 PPC970_DGroup_First, PPC970_Unit_FXU; 709} 710 711def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>, 712 PPC970_DGroup_First, PPC970_Unit_FXU; 713def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>, 714 PPC970_DGroup_First, PPC970_Unit_FXU; 715 716// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 717// a GPR on the PPC970. As such, copies in and out have the same performance 718// characteristics as an OR instruction. 719def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), 720 "mtspr 256, $rS", IntGeneral>, 721 PPC970_DGroup_Single, PPC970_Unit_FXU; 722def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), 723 "mfspr $rT, 256", IntGeneral>, 724 PPC970_DGroup_First, PPC970_Unit_FXU; 725 726def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS), 727 "mtcrf $FXM, $rS", BrMCRX>, 728 PPC970_MicroCode, PPC970_Unit_CRU; 729def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>, 730 PPC970_MicroCode, PPC970_Unit_CRU; 731def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM), 732 "mfcr $rT, $FXM", SprMFCR>, 733 PPC970_DGroup_First, PPC970_Unit_CRU; 734 735let PPC970_Unit = 1 in { // FXU Operations. 736 737// XO-Form instructions. Arithmetic instructions that can set overflow bit 738// 739def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 740 "add $rT, $rA, $rB", IntGeneral, 741 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 742def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 743 "addc $rT, $rA, $rB", IntGeneral, 744 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 745 PPC970_DGroup_Cracked; 746def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 747 "adde $rT, $rA, $rB", IntGeneral, 748 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 749def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 750 "divw $rT, $rA, $rB", IntDivW, 751 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 752 PPC970_DGroup_First, PPC970_DGroup_Cracked; 753def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 754 "divwu $rT, $rA, $rB", IntDivW, 755 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 756 PPC970_DGroup_First, PPC970_DGroup_Cracked; 757def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 758 "mulhw $rT, $rA, $rB", IntMulHW, 759 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 760def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 761 "mulhwu $rT, $rA, $rB", IntMulHWU, 762 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 763def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 764 "mullw $rT, $rA, $rB", IntMulHW, 765 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 766def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 767 "subf $rT, $rA, $rB", IntGeneral, 768 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 769def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 770 "subfc $rT, $rA, $rB", IntGeneral, 771 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 772 PPC970_DGroup_Cracked; 773def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 774 "subfe $rT, $rA, $rB", IntGeneral, 775 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 776def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA), 777 "addme $rT, $rA", IntGeneral, 778 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>; 779def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA), 780 "addze $rT, $rA", IntGeneral, 781 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 782def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA), 783 "neg $rT, $rA", IntGeneral, 784 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 785def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA), 786 "subfme $rT, $rA", IntGeneral, 787 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>; 788def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA), 789 "subfze $rT, $rA", IntGeneral, 790 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 791} 792 793// A-Form instructions. Most of the instructions executed in the FPU are of 794// this type. 795// 796let PPC970_Unit = 3 in { // FPU Operations. 797def FMADD : AForm_1<63, 29, 798 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 799 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 800 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), 801 F8RC:$FRB))]>, 802 Requires<[FPContractions]>; 803def FMADDS : AForm_1<59, 29, 804 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 805 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 806 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), 807 F4RC:$FRB))]>, 808 Requires<[FPContractions]>; 809def FMSUB : AForm_1<63, 28, 810 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 811 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 812 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), 813 F8RC:$FRB))]>, 814 Requires<[FPContractions]>; 815def FMSUBS : AForm_1<59, 28, 816 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 817 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 818 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), 819 F4RC:$FRB))]>, 820 Requires<[FPContractions]>; 821def FNMADD : AForm_1<63, 31, 822 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 823 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 824 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), 825 F8RC:$FRB)))]>, 826 Requires<[FPContractions]>; 827def FNMADDS : AForm_1<59, 31, 828 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 829 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 830 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), 831 F4RC:$FRB)))]>, 832 Requires<[FPContractions]>; 833def FNMSUB : AForm_1<63, 30, 834 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 835 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 836 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), 837 F8RC:$FRB)))]>, 838 Requires<[FPContractions]>; 839def FNMSUBS : AForm_1<59, 30, 840 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 841 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 842 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), 843 F4RC:$FRB)))]>, 844 Requires<[FPContractions]>; 845// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 846// having 4 of these, force the comparison to always be an 8-byte double (code 847// should use an FMRSD if the input comparison value really wants to be a float) 848// and 4/8 byte forms for the result and operand type.. 849def FSELD : AForm_1<63, 23, 850 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 851 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 852 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 853def FSELS : AForm_1<63, 23, 854 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 855 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 856 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 857def FADD : AForm_2<63, 21, 858 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 859 "fadd $FRT, $FRA, $FRB", FPGeneral, 860 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 861def FADDS : AForm_2<59, 21, 862 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 863 "fadds $FRT, $FRA, $FRB", FPGeneral, 864 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 865def FDIV : AForm_2<63, 18, 866 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 867 "fdiv $FRT, $FRA, $FRB", FPDivD, 868 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 869def FDIVS : AForm_2<59, 18, 870 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 871 "fdivs $FRT, $FRA, $FRB", FPDivS, 872 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 873def FMUL : AForm_3<63, 25, 874 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 875 "fmul $FRT, $FRA, $FRB", FPFused, 876 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 877def FMULS : AForm_3<59, 25, 878 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 879 "fmuls $FRT, $FRA, $FRB", FPGeneral, 880 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 881def FSUB : AForm_2<63, 20, 882 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 883 "fsub $FRT, $FRA, $FRB", FPGeneral, 884 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 885def FSUBS : AForm_2<59, 20, 886 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 887 "fsubs $FRT, $FRA, $FRB", FPGeneral, 888 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 889} 890 891let PPC970_Unit = 1 in { // FXU Operations. 892// M-Form instructions. rotate and mask instructions. 893// 894let isTwoAddress = 1, isCommutable = 1 in { 895// RLWIMI can be commuted if the rotate amount is zero. 896def RLWIMI : MForm_2<20, 897 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 898 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 899 []>, PPC970_DGroup_Cracked; 900} 901def RLWINM : MForm_2<21, 902 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 903 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 904 []>; 905def RLWINMo : MForm_2<21, 906 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 907 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 908 []>, isDOT, PPC970_DGroup_Cracked; 909def RLWNM : MForm_2<23, 910 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 911 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 912 []>; 913} 914 915 916//===----------------------------------------------------------------------===// 917// DWARF Pseudo Instructions 918// 919 920def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file), 921 "${:comment} .loc $file, $line, $col", 922 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), 923 (i32 imm:$file))]>; 924 925def DWARF_LABEL : Pseudo<(ops i32imm:$id), 926 "\n${:private}debug_loc$id:", 927 [(dwarf_label (i32 imm:$id))]>; 928 929//===----------------------------------------------------------------------===// 930// PowerPC Instruction Patterns 931// 932 933// Arbitrary immediate support. Implement in terms of LIS/ORI. 934def : Pat<(i32 imm:$imm), 935 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 936 937// Implement the 'not' operation with the NOR instruction. 938def NOT : Pat<(not GPRC:$in), 939 (NOR GPRC:$in, GPRC:$in)>; 940 941// ADD an arbitrary immediate. 942def : Pat<(add GPRC:$in, imm:$imm), 943 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 944// OR an arbitrary immediate. 945def : Pat<(or GPRC:$in, imm:$imm), 946 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 947// XOR an arbitrary immediate. 948def : Pat<(xor GPRC:$in, imm:$imm), 949 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 950// SUBFIC 951def : Pat<(sub immSExt16:$imm, GPRC:$in), 952 (SUBFIC GPRC:$in, imm:$imm)>; 953 954// Return void support. 955def : Pat<(ret), (BLR)>; 956 957// SHL/SRL 958def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 959 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 960def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 961 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 962 963// ROTL 964def : Pat<(rotl GPRC:$in, GPRC:$sh), 965 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 966def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 967 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 968 969// RLWNM 970def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm), 971 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 972 973// Calls 974def : Pat<(PPCcall tglobaladdr:$dst), 975 (BL tglobaladdr:$dst)>; 976def : Pat<(PPCcall texternalsym:$dst), 977 (BL texternalsym:$dst)>; 978 979// Hi and Lo for Darwin Global Addresses. 980def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 981def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 982def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 983def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 984def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 985def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 986def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 987 (ADDIS GPRC:$in, tglobaladdr:$g)>; 988def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 989 (ADDIS GPRC:$in, tconstpool:$g)>; 990def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 991 (ADDIS GPRC:$in, tjumptable:$g)>; 992 993// Fused negative multiply subtract, alternate pattern 994def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), 995 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>, 996 Requires<[FPContractions]>; 997def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)), 998 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>, 999 Requires<[FPContractions]>; 1000 1001// Standard shifts. These are represented separately from the real shifts above 1002// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1003// amounts. 1004def : Pat<(sra GPRC:$rS, GPRC:$rB), 1005 (SRAW GPRC:$rS, GPRC:$rB)>; 1006def : Pat<(srl GPRC:$rS, GPRC:$rB), 1007 (SRW GPRC:$rS, GPRC:$rB)>; 1008def : Pat<(shl GPRC:$rS, GPRC:$rB), 1009 (SLW GPRC:$rS, GPRC:$rB)>; 1010 1011def : Pat<(zextloadi1 iaddr:$src), 1012 (LBZ iaddr:$src)>; 1013def : Pat<(zextloadi1 xaddr:$src), 1014 (LBZX xaddr:$src)>; 1015def : Pat<(extloadi1 iaddr:$src), 1016 (LBZ iaddr:$src)>; 1017def : Pat<(extloadi1 xaddr:$src), 1018 (LBZX xaddr:$src)>; 1019def : Pat<(extloadi8 iaddr:$src), 1020 (LBZ iaddr:$src)>; 1021def : Pat<(extloadi8 xaddr:$src), 1022 (LBZX xaddr:$src)>; 1023def : Pat<(extloadi16 iaddr:$src), 1024 (LHZ iaddr:$src)>; 1025def : Pat<(extloadi16 xaddr:$src), 1026 (LHZX xaddr:$src)>; 1027def : Pat<(extloadf32 iaddr:$src), 1028 (FMRSD (LFS iaddr:$src))>; 1029def : Pat<(extloadf32 xaddr:$src), 1030 (FMRSD (LFSX xaddr:$src))>; 1031 1032include "PPCInstrAltivec.td" 1033include "PPCInstr64Bit.td" 1034