PPCInstrInfo.td revision c703a8fbf8653ac8302ae368391a4954c307ca2c
1//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl 24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32> 25]>; 26def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 27 28def SDT_PPCvperm : SDTypeProfile<1, 3, [ 29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 30]>; 31 32def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 34]>; 35 36def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 37 SDTCisVT<1, i32>, SDTCisVT<2, OtherVT> 38]>; 39 40//===----------------------------------------------------------------------===// 41// PowerPC specific DAG Nodes. 42// 43 44def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 45def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 46def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 47def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>; 48 49def PPCfsel : SDNode<"PPCISD::FSEL", 50 // Type constraint for fsel. 51 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 52 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 53 54def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 55def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 56def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 57def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 58 59def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 60 61// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 62// amounts. These nodes are generated by the multi-precision shift code. 63def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>; 64def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>; 65def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>; 66 67def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 68def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>; 69 70// These are target-independent nodes, but have target-specific formats. 71def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>; 72def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>; 73 74def SDT_PPCCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 75def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 76 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 77def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 78 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 79def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet, 80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 81 82def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet, 83 [SDNPHasChain, SDNPOptInFlag]>; 84 85def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 86def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>; 87 88def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 89 [SDNPHasChain, SDNPOptInFlag]>; 90 91//===----------------------------------------------------------------------===// 92// PowerPC specific transformation functions and pattern fragments. 93// 94 95def SHL32 : SDNodeXForm<imm, [{ 96 // Transformation function: 31 - imm 97 return getI32Imm(31 - N->getValue()); 98}]>; 99 100def SHL64 : SDNodeXForm<imm, [{ 101 // Transformation function: 63 - imm 102 return getI32Imm(63 - N->getValue()); 103}]>; 104 105def SRL32 : SDNodeXForm<imm, [{ 106 // Transformation function: 32 - imm 107 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0); 108}]>; 109 110def SRL64 : SDNodeXForm<imm, [{ 111 // Transformation function: 64 - imm 112 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0); 113}]>; 114 115def LO16 : SDNodeXForm<imm, [{ 116 // Transformation function: get the low 16 bits. 117 return getI32Imm((unsigned short)N->getValue()); 118}]>; 119 120def HI16 : SDNodeXForm<imm, [{ 121 // Transformation function: shift the immediate value down into the low bits. 122 return getI32Imm((unsigned)N->getValue() >> 16); 123}]>; 124 125def HA16 : SDNodeXForm<imm, [{ 126 // Transformation function: shift the immediate value down into the low bits. 127 signed int Val = N->getValue(); 128 return getI32Imm((Val - (signed short)Val) >> 16); 129}]>; 130 131 132def immSExt16 : PatLeaf<(imm), [{ 133 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 134 // field. Used by instructions like 'addi'. 135 return (int)N->getValue() == (short)N->getValue(); 136}]>; 137def immZExt16 : PatLeaf<(imm), [{ 138 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 139 // field. Used by instructions like 'ori'. 140 return (unsigned)N->getValue() == (unsigned short)N->getValue(); 141}], LO16>; 142 143def imm16Shifted : PatLeaf<(imm), [{ 144 // imm16Shifted predicate - True if only bits in the top 16-bits of the 145 // immediate are set. Used by instructions like 'addis'. 146 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue(); 147}], HI16>; 148 149 150//===----------------------------------------------------------------------===// 151// PowerPC Flag Definitions. 152 153class isPPC64 { bit PPC64 = 1; } 154class isVMX { bit VMX = 1; } 155class isDOT { 156 list<Register> Defs = [CR0]; 157 bit RC = 1; 158} 159 160 161 162//===----------------------------------------------------------------------===// 163// PowerPC Operand Definitions. 164 165def s5imm : Operand<i32> { 166 let PrintMethod = "printS5ImmOperand"; 167} 168def u5imm : Operand<i32> { 169 let PrintMethod = "printU5ImmOperand"; 170} 171def u6imm : Operand<i32> { 172 let PrintMethod = "printU6ImmOperand"; 173} 174def s16imm : Operand<i32> { 175 let PrintMethod = "printS16ImmOperand"; 176} 177def u16imm : Operand<i32> { 178 let PrintMethod = "printU16ImmOperand"; 179} 180def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 181 let PrintMethod = "printS16X4ImmOperand"; 182} 183def target : Operand<OtherVT> { 184 let PrintMethod = "printBranchOperand"; 185} 186def calltarget : Operand<i32> { 187 let PrintMethod = "printCallOperand"; 188} 189def aaddr : Operand<i32> { 190 let PrintMethod = "printAbsAddrOperand"; 191} 192def piclabel: Operand<i32> { 193 let PrintMethod = "printPICLabel"; 194} 195def symbolHi: Operand<i32> { 196 let PrintMethod = "printSymbolHi"; 197} 198def symbolLo: Operand<i32> { 199 let PrintMethod = "printSymbolLo"; 200} 201def crbitm: Operand<i8> { 202 let PrintMethod = "printcrbitm"; 203} 204// Address operands 205def memri : Operand<i32> { 206 let PrintMethod = "printMemRegImm"; 207 let NumMIOperands = 2; 208 let MIOperandInfo = (ops i32imm, GPRC); 209} 210def memrr : Operand<i32> { 211 let PrintMethod = "printMemRegReg"; 212 let NumMIOperands = 2; 213 let MIOperandInfo = (ops GPRC, GPRC); 214} 215def memrix : Operand<i32> { // memri where the imm is shifted 2 bits. 216 let PrintMethod = "printMemRegImmShifted"; 217 let NumMIOperands = 2; 218 let MIOperandInfo = (ops i32imm, GPRC); 219} 220 221// Define PowerPC specific addressing mode. 222def iaddr : ComplexPattern<i32, 2, "SelectAddrImm", []>; 223def xaddr : ComplexPattern<i32, 2, "SelectAddrIdx", []>; 224def xoaddr : ComplexPattern<i32, 2, "SelectAddrIdxOnly",[]>; 225def ixaddr : ComplexPattern<i32, 2, "SelectAddrImmShift", []>; // "std" 226 227//===----------------------------------------------------------------------===// 228// PowerPC Instruction Predicate Definitions. 229def FPContractions : Predicate<"!NoExcessFPPrecision">; 230 231//===----------------------------------------------------------------------===// 232// PowerPC Instruction Definitions. 233 234// Pseudo-instructions: 235 236let hasCtrlDep = 1 in { 237def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), 238 "; ADJCALLSTACKDOWN", 239 [(callseq_start imm:$amt)]>; 240def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), 241 "; ADJCALLSTACKUP", 242 [(callseq_end imm:$amt)]>; 243 244def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS), 245 "UPDATE_VRSAVE $rD, $rS", []>; 246} 247def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC", 248 [(set GPRC:$rD, (undef))]>; 249def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8", 250 [(set F8RC:$rD, (undef))]>; 251def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4", 252 [(set F4RC:$rD, (undef))]>; 253 254// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 255// scheduler into a branch sequence. 256let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler. 257 PPC970_Single = 1 in { 258 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F, 259 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>; 260 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F, 261 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>; 262 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F, 263 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>; 264 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F, 265 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>; 266} 267 268let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in { 269 let isReturn = 1 in 270 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>; 271 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>; 272} 273 274let Defs = [LR] in 275 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>, 276 PPC970_Unit_BRU; 277 278let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, 279 noResults = 1, PPC970_Unit = 7 in { 280 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst), 281 "; COND_BRANCH $crS, $opc, $dst", 282 [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>; 283 def B : IForm<18, 0, 0, (ops target:$dst), 284 "b $dst", BrB, 285 [(br bb:$dst)]>; 286 287 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block), 288 "blt $crS, $block", BrB>; 289 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block), 290 "ble $crS, $block", BrB>; 291 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block), 292 "beq $crS, $block", BrB>; 293 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block), 294 "bge $crS, $block", BrB>; 295 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block), 296 "bgt $crS, $block", BrB>; 297 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block), 298 "bne $crS, $block", BrB>; 299 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block), 300 "bun $crS, $block", BrB>; 301 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block), 302 "bnu $crS, $block", BrB>; 303} 304 305let isCall = 1, noResults = 1, PPC970_Unit = 7, 306 // All calls clobber the non-callee saved registers... 307 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 308 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 309 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 310 LR,CTR, 311 CR0,CR1,CR5,CR6,CR7] in { 312 // Convenient aliases for call instructions 313 def BL : IForm<18, 0, 1, (ops calltarget:$func), 314 "bl $func", BrB, []>; // See Pat patterns below. 315 def BLA : IForm<18, 1, 1, (ops aaddr:$func), 316 "bla $func", BrB, [(PPCcall imm:$func)]>; 317 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops), "bctrl", BrB, 318 [(PPCbctrl)]>; 319} 320 321// D-Form instructions. Most instructions that perform an operation on a 322// register and an immediate are of this type. 323// 324let isLoad = 1, PPC970_Unit = 2 in { 325def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src), 326 "lbz $rD, $src", LdStGeneral, 327 [(set GPRC:$rD, (zextload iaddr:$src, i8))]>; 328def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src), 329 "lha $rD, $src", LdStLHA, 330 [(set GPRC:$rD, (sextload iaddr:$src, i16))]>, 331 PPC970_DGroup_Cracked; 332def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src), 333 "lhz $rD, $src", LdStGeneral, 334 [(set GPRC:$rD, (zextload iaddr:$src, i16))]>; 335def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src), 336 "lwz $rD, $src", LdStGeneral, 337 [(set GPRC:$rD, (load iaddr:$src))]>; 338def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA), 339 "lwzu $rD, $disp($rA)", LdStGeneral, 340 []>; 341} 342let PPC970_Unit = 1 in { // FXU Operations. 343def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 344 "addi $rD, $rA, $imm", IntGeneral, 345 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 346def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 347 "addic $rD, $rA, $imm", IntGeneral, 348 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 349 PPC970_DGroup_Cracked; 350def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 351 "addic. $rD, $rA, $imm", IntGeneral, 352 []>; 353def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm), 354 "addis $rD, $rA, $imm", IntGeneral, 355 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>; 356def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym), 357 "la $rD, $sym($rA)", IntGeneral, 358 [(set GPRC:$rD, (add GPRC:$rA, 359 (PPClo tglobaladdr:$sym, 0)))]>; 360def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 361 "mulli $rD, $rA, $imm", IntMulLI, 362 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 363def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 364 "subfic $rD, $rA, $imm", IntGeneral, 365 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 366def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm), 367 "li $rD, $imm", IntGeneral, 368 [(set GPRC:$rD, immSExt16:$imm)]>; 369def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm), 370 "lis $rD, $imm", IntGeneral, 371 [(set GPRC:$rD, imm16Shifted:$imm)]>; 372} 373let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 374def STB : DForm_3<38, (ops GPRC:$rS, memri:$src), 375 "stb $rS, $src", LdStGeneral, 376 [(truncstore GPRC:$rS, iaddr:$src, i8)]>; 377def STH : DForm_3<44, (ops GPRC:$rS, memri:$src), 378 "sth $rS, $src", LdStGeneral, 379 [(truncstore GPRC:$rS, iaddr:$src, i16)]>; 380def STW : DForm_3<36, (ops GPRC:$rS, memri:$src), 381 "stw $rS, $src", LdStGeneral, 382 [(store GPRC:$rS, iaddr:$src)]>; 383def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 384 "stwu $rS, $disp($rA)", LdStGeneral, 385 []>; 386} 387let PPC970_Unit = 1 in { // FXU Operations. 388def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 389 "andi. $dst, $src1, $src2", IntGeneral, 390 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 391 isDOT; 392def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 393 "andis. $dst, $src1, $src2", IntGeneral, 394 [(set GPRC:$dst, (and GPRC:$src1, imm16Shifted:$src2))]>, 395 isDOT; 396def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 397 "ori $dst, $src1, $src2", IntGeneral, 398 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 399def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 400 "oris $dst, $src1, $src2", IntGeneral, 401 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>; 402def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 403 "xori $dst, $src1, $src2", IntGeneral, 404 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 405def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 406 "xoris $dst, $src1, $src2", IntGeneral, 407 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>; 408def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral, 409 []>; 410def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm), 411 "cmpi $crD, $L, $rA, $imm", IntCompare>; 412def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 413 "cmpwi $crD, $rA, $imm", IntCompare>; 414def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 415 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 416def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2), 417 "cmpli $dst, $size, $src1, $src2", IntCompare>; 418def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 419 "cmplwi $dst, $src1, $src2", IntCompare>; 420def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 421 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 422} 423let isLoad = 1, PPC970_Unit = 2 in { 424def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src), 425 "lfs $rD, $src", LdStLFDU, 426 [(set F4RC:$rD, (load iaddr:$src))]>; 427def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src), 428 "lfd $rD, $src", LdStLFD, 429 [(set F8RC:$rD, (load iaddr:$src))]>; 430} 431let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 432def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst), 433 "stfs $rS, $dst", LdStUX, 434 [(store F4RC:$rS, iaddr:$dst)]>; 435def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst), 436 "stfd $rS, $dst", LdStUX, 437 [(store F8RC:$rS, iaddr:$dst)]>; 438} 439 440// DS-Form instructions. Load/Store instructions available in PPC-64 441// 442let isLoad = 1, PPC970_Unit = 2 in { 443def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 444 "lwa $rT, $DS($rA)", LdStLWA, 445 []>, isPPC64, PPC970_DGroup_Cracked; 446def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 447 "ld $rT, $DS($rA)", LdStLD, 448 []>, isPPC64; 449} 450let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 451def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 452 "std $rT, $DS($rA)", LdStSTD, 453 []>, isPPC64; 454 455// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 456def STD_32 : DSForm_2<62, 0, (ops GPRC:$rT, memrix:$dst), 457 "std $rT, $dst", LdStSTD, 458 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 459def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst), 460 "stdx $rT, $dst", LdStSTD, 461 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 462 PPC970_DGroup_Cracked; 463} 464 465// X-Form instructions. Most instructions that perform an operation on a 466// register and another register are of this type. 467// 468let isLoad = 1, PPC970_Unit = 2 in { 469def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src), 470 "lbzx $rD, $src", LdStGeneral, 471 [(set GPRC:$rD, (zextload xaddr:$src, i8))]>; 472def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src), 473 "lhax $rD, $src", LdStLHA, 474 [(set GPRC:$rD, (sextload xaddr:$src, i16))]>, 475 PPC970_DGroup_Cracked; 476def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src), 477 "lhzx $rD, $src", LdStGeneral, 478 [(set GPRC:$rD, (zextload xaddr:$src, i16))]>; 479def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src), 480 "lwax $rD, $src", LdStLHA, 481 [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64, 482 PPC970_DGroup_Cracked; 483def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src), 484 "lwzx $rD, $src", LdStGeneral, 485 [(set GPRC:$rD, (load xaddr:$src))]>; 486def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src), 487 "ldx $rD, $src", LdStLD, 488 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 489} 490 491let PPC970_Unit = 1 in { // FXU Operations. 492def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 493 "nand $rA, $rS, $rB", IntGeneral, 494 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 495def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 496 "and $rA, $rS, $rB", IntGeneral, 497 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 498def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 499 "and. $rA, $rS, $rB", IntGeneral, 500 []>, isDOT; 501def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 502 "andc $rA, $rS, $rB", IntGeneral, 503 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 504def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 505 "or $rA, $rS, $rB", IntGeneral, 506 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 507def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 508 "or $rA, $rS, $rB", IntGeneral, 509 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 510def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB), 511 "or $rA, $rS, $rB", IntGeneral, 512 []>; 513def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB), 514 "or $rA, $rS, $rB", IntGeneral, 515 []>; 516def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 517 "nor $rA, $rS, $rB", IntGeneral, 518 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 519def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 520 "or. $rA, $rS, $rB", IntGeneral, 521 []>, isDOT; 522def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 523 "orc $rA, $rS, $rB", IntGeneral, 524 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 525def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 526 "eqv $rA, $rS, $rB", IntGeneral, 527 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 528def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 529 "xor $rA, $rS, $rB", IntGeneral, 530 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 531def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 532 "sld $rA, $rS, $rB", IntRotateD, 533 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64; 534def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 535 "slw $rA, $rS, $rB", IntGeneral, 536 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 537def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 538 "srd $rA, $rS, $rB", IntRotateD, 539 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64; 540def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 541 "srw $rA, $rS, $rB", IntGeneral, 542 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 543def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 544 "srad $rA, $rS, $rB", IntRotateD, 545 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64; 546def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 547 "sraw $rA, $rS, $rB", IntShift, 548 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 549} 550let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 551def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst), 552 "stbx $rS, $dst", LdStGeneral, 553 [(truncstore GPRC:$rS, xaddr:$dst, i8)]>, 554 PPC970_DGroup_Cracked; 555def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst), 556 "sthx $rS, $dst", LdStGeneral, 557 [(truncstore GPRC:$rS, xaddr:$dst, i16)]>, 558 PPC970_DGroup_Cracked; 559def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst), 560 "stwx $rS, $dst", LdStGeneral, 561 [(store GPRC:$rS, xaddr:$dst)]>, 562 PPC970_DGroup_Cracked; 563def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 564 "stwux $rS, $rA, $rB", LdStGeneral, 565 []>; 566def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 567 "stdx $rS, $rA, $rB", LdStSTD, 568 []>, isPPC64, PPC970_DGroup_Cracked; 569def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 570 "stdux $rS, $rA, $rB", LdStSTD, 571 []>, isPPC64; 572} 573let PPC970_Unit = 1 in { // FXU Operations. 574def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), 575 "srawi $rA, $rS, $SH", IntShift, 576 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 577def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS), 578 "cntlzw $rA, $rS", IntGeneral, 579 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 580def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS), 581 "extsb $rA, $rS", IntGeneral, 582 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 583def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS), 584 "extsh $rA, $rS", IntGeneral, 585 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 586def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS), 587 "extsw $rA, $rS", IntGeneral, 588 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 589/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 590def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS), 591 "extsw $rA, $rS", IntGeneral, 592 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 593 594def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB), 595 "cmp $crD, $long, $rA, $rB", IntCompare>; 596def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB), 597 "cmpl $crD, $long, $rA, $rB", IntCompare>; 598def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 599 "cmpw $crD, $rA, $rB", IntCompare>; 600def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 601 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 602def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 603 "cmplw $crD, $rA, $rB", IntCompare>; 604def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 605 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 606} 607let PPC970_Unit = 3 in { // FPU Operations. 608//def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB), 609// "fcmpo $crD, $fA, $fB", FPCompare>; 610def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB), 611 "fcmpu $crD, $fA, $fB", FPCompare>; 612def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB), 613 "fcmpu $crD, $fA, $fB", FPCompare>; 614} 615let isLoad = 1, PPC970_Unit = 2 in { 616def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src), 617 "lfsx $frD, $src", LdStLFDU, 618 [(set F4RC:$frD, (load xaddr:$src))]>; 619def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src), 620 "lfdx $frD, $src", LdStLFDU, 621 [(set F8RC:$frD, (load xaddr:$src))]>; 622} 623let PPC970_Unit = 3 in { // FPU Operations. 624def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB), 625 "fcfid $frD, $frB", FPGeneral, 626 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 627def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB), 628 "fctidz $frD, $frB", FPGeneral, 629 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 630def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB), 631 "fctiwz $frD, $frB", FPGeneral, 632 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 633def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB), 634 "frsp $frD, $frB", FPGeneral, 635 [(set F4RC:$frD, (fround F8RC:$frB))]>; 636def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB), 637 "fsqrt $frD, $frB", FPSqrt, 638 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 639def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB), 640 "fsqrts $frD, $frB", FPSqrt, 641 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 642} 643 644/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending. 645/// 646/// Note that these are defined as pseudo-ops on the PPC970 because they are 647/// often coalesced away and we don't want the dispatch group builder to think 648/// that they will fill slots (which could cause the load of a LSU reject to 649/// sneak into a d-group with a store). 650def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB), 651 "fmr $frD, $frB", FPGeneral, 652 []>, // (set F4RC:$frD, F4RC:$frB) 653 PPC970_Unit_Pseudo; 654def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB), 655 "fmr $frD, $frB", FPGeneral, 656 []>, // (set F8RC:$frD, F8RC:$frB) 657 PPC970_Unit_Pseudo; 658def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB), 659 "fmr $frD, $frB", FPGeneral, 660 [(set F8RC:$frD, (fextend F4RC:$frB))]>, 661 PPC970_Unit_Pseudo; 662 663let PPC970_Unit = 3 in { // FPU Operations. 664// These are artificially split into two different forms, for 4/8 byte FP. 665def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB), 666 "fabs $frD, $frB", FPGeneral, 667 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 668def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB), 669 "fabs $frD, $frB", FPGeneral, 670 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 671def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB), 672 "fnabs $frD, $frB", FPGeneral, 673 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 674def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB), 675 "fnabs $frD, $frB", FPGeneral, 676 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 677def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB), 678 "fneg $frD, $frB", FPGeneral, 679 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 680def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB), 681 "fneg $frD, $frB", FPGeneral, 682 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 683} 684 685let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 686def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst), 687 "stfiwx $frS, $dst", LdStUX, 688 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 689def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst), 690 "stfsx $frS, $dst", LdStUX, 691 [(store F4RC:$frS, xaddr:$dst)]>; 692def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst), 693 "stfdx $frS, $dst", LdStUX, 694 [(store F8RC:$frS, xaddr:$dst)]>; 695} 696 697// XL-Form instructions. condition register logical ops. 698// 699def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA), 700 "mcrf $BF, $BFA", BrMCR>, 701 PPC970_DGroup_First, PPC970_Unit_CRU; 702 703// XFX-Form instructions. Instructions that deal with SPRs. 704// 705def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>, 706 PPC970_DGroup_First, PPC970_Unit_FXU; 707let Pattern = [(PPCmtctr GPRC:$rS)] in { 708def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>, 709 PPC970_DGroup_First, PPC970_Unit_FXU; 710} 711 712def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>, 713 PPC970_DGroup_First, PPC970_Unit_FXU; 714def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>, 715 PPC970_DGroup_First, PPC970_Unit_FXU; 716 717// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 718// a GPR on the PPC970. As such, copies in and out have the same performance 719// characteristics as an OR instruction. 720def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), 721 "mtspr 256, $rS", IntGeneral>, 722 PPC970_DGroup_Single, PPC970_Unit_FXU; 723def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), 724 "mfspr $rT, 256", IntGeneral>, 725 PPC970_DGroup_First, PPC970_Unit_FXU; 726 727def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS), 728 "mtcrf $FXM, $rS", BrMCRX>, 729 PPC970_MicroCode, PPC970_Unit_CRU; 730def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>, 731 PPC970_MicroCode, PPC970_Unit_CRU; 732def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM), 733 "mfcr $rT, $FXM", SprMFCR>, 734 PPC970_DGroup_First, PPC970_Unit_CRU; 735 736// XS-Form instructions. Just 'sradi' 737// 738let PPC970_Unit = 1 in { // FXU Operations. 739def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH), 740 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64; 741 742// XO-Form instructions. Arithmetic instructions that can set overflow bit 743// 744def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 745 "add $rT, $rA, $rB", IntGeneral, 746 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 747def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 748 "add $rT, $rA, $rB", IntGeneral, 749 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 750def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 751 "addc $rT, $rA, $rB", IntGeneral, 752 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 753 PPC970_DGroup_Cracked; 754def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 755 "adde $rT, $rA, $rB", IntGeneral, 756 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 757def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 758 "divd $rT, $rA, $rB", IntDivD, 759 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 760 PPC970_DGroup_First, PPC970_DGroup_Cracked; 761def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 762 "divdu $rT, $rA, $rB", IntDivD, 763 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 764 PPC970_DGroup_First, PPC970_DGroup_Cracked; 765def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 766 "divw $rT, $rA, $rB", IntDivW, 767 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 768 PPC970_DGroup_First, PPC970_DGroup_Cracked; 769def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 770 "divwu $rT, $rA, $rB", IntDivW, 771 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 772 PPC970_DGroup_First, PPC970_DGroup_Cracked; 773def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 774 "mulhd $rT, $rA, $rB", IntMulHW, 775 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 776def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 777 "mulhdu $rT, $rA, $rB", IntMulHWU, 778 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 779def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 780 "mulhw $rT, $rA, $rB", IntMulHW, 781 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 782def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 783 "mulhwu $rT, $rA, $rB", IntMulHWU, 784 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 785def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 786 "mulld $rT, $rA, $rB", IntMulHD, 787 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 788def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 789 "mullw $rT, $rA, $rB", IntMulHW, 790 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 791def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 792 "subf $rT, $rA, $rB", IntGeneral, 793 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 794def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 795 "subfc $rT, $rA, $rB", IntGeneral, 796 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 797 PPC970_DGroup_Cracked; 798def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 799 "subfe $rT, $rA, $rB", IntGeneral, 800 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 801def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA), 802 "addme $rT, $rA", IntGeneral, 803 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>; 804def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA), 805 "addze $rT, $rA", IntGeneral, 806 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 807def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA), 808 "neg $rT, $rA", IntGeneral, 809 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 810def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA), 811 "subfme $rT, $rA", IntGeneral, 812 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>; 813def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA), 814 "subfze $rT, $rA", IntGeneral, 815 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 816} 817 818// A-Form instructions. Most of the instructions executed in the FPU are of 819// this type. 820// 821let PPC970_Unit = 3 in { // FPU Operations. 822def FMADD : AForm_1<63, 29, 823 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 824 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 825 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), 826 F8RC:$FRB))]>, 827 Requires<[FPContractions]>; 828def FMADDS : AForm_1<59, 29, 829 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 830 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 831 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), 832 F4RC:$FRB))]>, 833 Requires<[FPContractions]>; 834def FMSUB : AForm_1<63, 28, 835 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 836 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 837 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), 838 F8RC:$FRB))]>, 839 Requires<[FPContractions]>; 840def FMSUBS : AForm_1<59, 28, 841 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 842 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 843 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), 844 F4RC:$FRB))]>, 845 Requires<[FPContractions]>; 846def FNMADD : AForm_1<63, 31, 847 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 848 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 849 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), 850 F8RC:$FRB)))]>, 851 Requires<[FPContractions]>; 852def FNMADDS : AForm_1<59, 31, 853 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 854 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 855 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), 856 F4RC:$FRB)))]>, 857 Requires<[FPContractions]>; 858def FNMSUB : AForm_1<63, 30, 859 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 860 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 861 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), 862 F8RC:$FRB)))]>, 863 Requires<[FPContractions]>; 864def FNMSUBS : AForm_1<59, 30, 865 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 866 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 867 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), 868 F4RC:$FRB)))]>, 869 Requires<[FPContractions]>; 870// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 871// having 4 of these, force the comparison to always be an 8-byte double (code 872// should use an FMRSD if the input comparison value really wants to be a float) 873// and 4/8 byte forms for the result and operand type.. 874def FSELD : AForm_1<63, 23, 875 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 876 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 877 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 878def FSELS : AForm_1<63, 23, 879 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 880 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 881 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 882def FADD : AForm_2<63, 21, 883 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 884 "fadd $FRT, $FRA, $FRB", FPGeneral, 885 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 886def FADDS : AForm_2<59, 21, 887 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 888 "fadds $FRT, $FRA, $FRB", FPGeneral, 889 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 890def FDIV : AForm_2<63, 18, 891 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 892 "fdiv $FRT, $FRA, $FRB", FPDivD, 893 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 894def FDIVS : AForm_2<59, 18, 895 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 896 "fdivs $FRT, $FRA, $FRB", FPDivS, 897 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 898def FMUL : AForm_3<63, 25, 899 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 900 "fmul $FRT, $FRA, $FRB", FPFused, 901 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 902def FMULS : AForm_3<59, 25, 903 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 904 "fmuls $FRT, $FRA, $FRB", FPGeneral, 905 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 906def FSUB : AForm_2<63, 20, 907 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 908 "fsub $FRT, $FRA, $FRB", FPGeneral, 909 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 910def FSUBS : AForm_2<59, 20, 911 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 912 "fsubs $FRT, $FRA, $FRB", FPGeneral, 913 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 914} 915 916let PPC970_Unit = 1 in { // FXU Operations. 917// M-Form instructions. rotate and mask instructions. 918// 919let isTwoAddress = 1, isCommutable = 1 in { 920// RLWIMI can be commuted if the rotate amount is zero. 921def RLWIMI : MForm_2<20, 922 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 923 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 924 []>, PPC970_DGroup_Cracked; 925def RLDIMI : MDForm_1<30, 3, 926 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 927 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 928 []>, isPPC64; 929} 930def RLWINM : MForm_2<21, 931 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 932 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 933 []>; 934def RLWINMo : MForm_2<21, 935 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 936 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 937 []>, isDOT, PPC970_DGroup_Cracked; 938def RLWNM : MForm_2<23, 939 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 940 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 941 []>; 942 943// MD-Form instructions. 64 bit rotate instructions. 944// 945def RLDICL : MDForm_1<30, 0, 946 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB), 947 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 948 []>, isPPC64; 949def RLDICR : MDForm_1<30, 1, 950 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME), 951 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 952 []>, isPPC64; 953} 954 955 956//===----------------------------------------------------------------------===// 957// DWARF Pseudo Instructions 958// 959 960def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file), 961 "; .loc $file, $line, $col", 962 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), 963 (i32 imm:$file))]>; 964 965def DWARF_LABEL : Pseudo<(ops i32imm:$id), 966 "\nLdebug_loc$id:", 967 [(dwarf_label (i32 imm:$id))]>; 968 969//===----------------------------------------------------------------------===// 970// PowerPC Instruction Patterns 971// 972 973// Arbitrary immediate support. Implement in terms of LIS/ORI. 974def : Pat<(i32 imm:$imm), 975 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 976 977// Implement the 'not' operation with the NOR instruction. 978def NOT : Pat<(not GPRC:$in), 979 (NOR GPRC:$in, GPRC:$in)>; 980 981// ADD an arbitrary immediate. 982def : Pat<(add GPRC:$in, imm:$imm), 983 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 984// OR an arbitrary immediate. 985def : Pat<(or GPRC:$in, imm:$imm), 986 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 987// XOR an arbitrary immediate. 988def : Pat<(xor GPRC:$in, imm:$imm), 989 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 990// SUBFIC 991def : Pat<(sub immSExt16:$imm, GPRC:$in), 992 (SUBFIC GPRC:$in, imm:$imm)>; 993 994// Return void support. 995def : Pat<(ret), (BLR)>; 996 997// 64-bit support 998def : Pat<(i64 (zext GPRC:$in)), 999 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; 1000def : Pat<(i64 (anyext GPRC:$in)), 1001 (OR4To8 GPRC:$in, GPRC:$in)>; 1002def : Pat<(i32 (trunc G8RC:$in)), 1003 (OR8To4 G8RC:$in, G8RC:$in)>; 1004 1005// SHL 1006def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1007 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1008def : Pat<(shl G8RC:$in, (i64 imm:$imm)), 1009 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 1010// SRL 1011def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1012 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1013def : Pat<(srl G8RC:$in, (i64 imm:$imm)), 1014 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 1015 1016// ROTL 1017def : Pat<(rotl GPRC:$in, GPRC:$sh), 1018 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1019def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1020 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1021 1022// Calls 1023def : Pat<(PPCcall tglobaladdr:$dst), 1024 (BL tglobaladdr:$dst)>; 1025def : Pat<(PPCcall texternalsym:$dst), 1026 (BL texternalsym:$dst)>; 1027 1028// Hi and Lo for Darwin Global Addresses. 1029def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1030def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1031def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1032def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1033def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1034def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1035def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1036 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1037def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1038 (ADDIS GPRC:$in, tconstpool:$g)>; 1039def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 1040 (ADDIS GPRC:$in, tjumptable:$g)>; 1041 1042// Fused negative multiply subtract, alternate pattern 1043def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), 1044 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>, 1045 Requires<[FPContractions]>; 1046def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)), 1047 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>, 1048 Requires<[FPContractions]>; 1049 1050// Standard shifts. These are represented separately from the real shifts above 1051// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1052// amounts. 1053def : Pat<(sra GPRC:$rS, GPRC:$rB), 1054 (SRAW GPRC:$rS, GPRC:$rB)>; 1055def : Pat<(srl GPRC:$rS, GPRC:$rB), 1056 (SRW GPRC:$rS, GPRC:$rB)>; 1057def : Pat<(shl GPRC:$rS, GPRC:$rB), 1058 (SLW GPRC:$rS, GPRC:$rB)>; 1059 1060def : Pat<(i32 (zextload iaddr:$src, i1)), 1061 (LBZ iaddr:$src)>; 1062def : Pat<(i32 (zextload xaddr:$src, i1)), 1063 (LBZX xaddr:$src)>; 1064def : Pat<(i32 (extload iaddr:$src, i1)), 1065 (LBZ iaddr:$src)>; 1066def : Pat<(i32 (extload xaddr:$src, i1)), 1067 (LBZX xaddr:$src)>; 1068def : Pat<(i32 (extload iaddr:$src, i8)), 1069 (LBZ iaddr:$src)>; 1070def : Pat<(i32 (extload xaddr:$src, i8)), 1071 (LBZX xaddr:$src)>; 1072def : Pat<(i32 (extload iaddr:$src, i16)), 1073 (LHZ iaddr:$src)>; 1074def : Pat<(i32 (extload xaddr:$src, i16)), 1075 (LHZX xaddr:$src)>; 1076def : Pat<(f64 (extload iaddr:$src, f32)), 1077 (FMRSD (LFS iaddr:$src))>; 1078def : Pat<(f64 (extload xaddr:$src, f32)), 1079 (FMRSD (LFSX xaddr:$src))>; 1080 1081 1082include "PPCInstrAltivec.td" 1083