PPCInstrInfo.td revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb
1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 24 SDTCisVT<0, f64>, SDTCisPtrTy<1> 25]>; 26 27def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 28def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 29 SDTCisVT<1, i32> ]>; 30def SDT_PPCvperm : SDTypeProfile<1, 3, [ 31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 32]>; 33 34def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 36]>; 37 38def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 40]>; 41 42def SDT_PPClbrx : SDTypeProfile<1, 2, [ 43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 44]>; 45def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 47]>; 48 49def SDT_PPClarx : SDTypeProfile<1, 1, [ 50 SDTCisInt<0>, SDTCisPtrTy<1> 51]>; 52def SDT_PPCstcx : SDTypeProfile<0, 2, [ 53 SDTCisInt<0>, SDTCisPtrTy<1> 54]>; 55 56def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 57 SDTCisPtrTy<0>, SDTCisVT<1, i32> 58]>; 59 60 61//===----------------------------------------------------------------------===// 62// PowerPC specific DAG Nodes. 63// 64 65def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 66def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 67 68def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 69def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 70def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 71def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 72def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 73def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 74def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 75def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 76def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 77 [SDNPHasChain, SDNPMayStore]>; 78def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 79 [SDNPHasChain, SDNPMayLoad]>; 80def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 81 [SDNPHasChain, SDNPMayLoad]>; 82 83// Extract FPSCR (not modeled at the DAG level). 84def PPCmffs : SDNode<"PPCISD::MFFS", 85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>; 86 87// Perform FADD in round-to-zero mode. 88def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 89 90 91def PPCfsel : SDNode<"PPCISD::FSEL", 92 // Type constraint for fsel. 93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 95 96def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 97def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 98def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>; 99def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 100def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 101 102def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 103 104def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 105def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 106 [SDNPMayLoad]>; 107def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 108def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 109def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 110def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 111def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 112def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 113def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 114def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp, 115 [SDNPHasChain]>; 116def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 117 118def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 119 120// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 121// amounts. These nodes are generated by the multi-precision shift code. 122def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 123def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 124def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 125 126// These are target-independent nodes, but have target-specific formats. 127def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 128 [SDNPHasChain, SDNPOutGlue]>; 129def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 131 132def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 133def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 135 SDNPVariadic]>; 136def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 138 SDNPVariadic]>; 139def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>, 140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 141def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>, 142 [SDNPHasChain, SDNPSideEffect, 143 SDNPInGlue, SDNPOutGlue]>; 144def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 145 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 146def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 147 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 148 SDNPVariadic]>; 149 150def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 151 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 152 153def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 154 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 155 156def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 157 SDTypeProfile<1, 1, [SDTCisInt<0>, 158 SDTCisPtrTy<1>]>, 159 [SDNPHasChain, SDNPSideEffect]>; 160def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 161 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 162 [SDNPHasChain, SDNPSideEffect]>; 163 164def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 165def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 166 [SDNPHasChain, SDNPSideEffect]>; 167 168def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 169def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 170 171def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 172 [SDNPHasChain, SDNPOptInGlue]>; 173 174def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 175 [SDNPHasChain, SDNPMayLoad]>; 176def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 177 [SDNPHasChain, SDNPMayStore]>; 178 179// Instructions to set/unset CR bit 6 for SVR4 vararg calls 180def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 181 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 182def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 183 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 184 185// Instructions to support atomic operations 186def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, 187 [SDNPHasChain, SDNPMayLoad]>; 188def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, 189 [SDNPHasChain, SDNPMayStore]>; 190 191// Instructions to support medium and large code model 192def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>; 193def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>; 194def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>; 195 196 197// Instructions to support dynamic alloca. 198def SDTDynOp : SDTypeProfile<1, 2, []>; 199def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 200 201//===----------------------------------------------------------------------===// 202// PowerPC specific transformation functions and pattern fragments. 203// 204 205def SHL32 : SDNodeXForm<imm, [{ 206 // Transformation function: 31 - imm 207 return getI32Imm(31 - N->getZExtValue()); 208}]>; 209 210def SRL32 : SDNodeXForm<imm, [{ 211 // Transformation function: 32 - imm 212 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0); 213}]>; 214 215def LO16 : SDNodeXForm<imm, [{ 216 // Transformation function: get the low 16 bits. 217 return getI32Imm((unsigned short)N->getZExtValue()); 218}]>; 219 220def HI16 : SDNodeXForm<imm, [{ 221 // Transformation function: shift the immediate value down into the low bits. 222 return getI32Imm((unsigned)N->getZExtValue() >> 16); 223}]>; 224 225def HA16 : SDNodeXForm<imm, [{ 226 // Transformation function: shift the immediate value down into the low bits. 227 signed int Val = N->getZExtValue(); 228 return getI32Imm((Val - (signed short)Val) >> 16); 229}]>; 230def MB : SDNodeXForm<imm, [{ 231 // Transformation function: get the start bit of a mask 232 unsigned mb = 0, me; 233 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 234 return getI32Imm(mb); 235}]>; 236 237def ME : SDNodeXForm<imm, [{ 238 // Transformation function: get the end bit of a mask 239 unsigned mb, me = 0; 240 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 241 return getI32Imm(me); 242}]>; 243def maskimm32 : PatLeaf<(imm), [{ 244 // maskImm predicate - True if immediate is a run of ones. 245 unsigned mb, me; 246 if (N->getValueType(0) == MVT::i32) 247 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 248 else 249 return false; 250}]>; 251 252def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 253 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 254 // sign extended field. Used by instructions like 'addi'. 255 return (int32_t)Imm == (short)Imm; 256}]>; 257def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 258 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 259 // sign extended field. Used by instructions like 'addi'. 260 return (int64_t)Imm == (short)Imm; 261}]>; 262def immZExt16 : PatLeaf<(imm), [{ 263 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 264 // field. Used by instructions like 'ori'. 265 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 266}], LO16>; 267 268// imm16Shifted* - These match immediates where the low 16-bits are zero. There 269// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 270// identical in 32-bit mode, but in 64-bit mode, they return true if the 271// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 272// clear). 273def imm16ShiftedZExt : PatLeaf<(imm), [{ 274 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 275 // immediate are set. Used by instructions like 'xoris'. 276 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 277}], HI16>; 278 279def imm16ShiftedSExt : PatLeaf<(imm), [{ 280 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 281 // immediate are set. Used by instructions like 'addis'. Identical to 282 // imm16ShiftedZExt in 32-bit mode. 283 if (N->getZExtValue() & 0xFFFF) return false; 284 if (N->getValueType(0) == MVT::i32) 285 return true; 286 // For 64-bit, make sure it is sext right. 287 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 288}], HI16>; 289 290def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 291 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 292 // zero extended field. 293 return isUInt<32>(Imm); 294}]>; 295 296// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 297// restricted memrix (4-aligned) constants are alignment sensitive. If these 298// offsets are hidden behind TOC entries than the values of the lower-order 299// bits cannot be checked directly. As a result, we need to also incorporate 300// an alignment check into the relevant patterns. 301 302def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 303 return cast<LoadSDNode>(N)->getAlignment() >= 4; 304}]>; 305def aligned4store : PatFrag<(ops node:$val, node:$ptr), 306 (store node:$val, node:$ptr), [{ 307 return cast<StoreSDNode>(N)->getAlignment() >= 4; 308}]>; 309def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 310 return cast<LoadSDNode>(N)->getAlignment() >= 4; 311}]>; 312def aligned4pre_store : PatFrag< 313 (ops node:$val, node:$base, node:$offset), 314 (pre_store node:$val, node:$base, node:$offset), [{ 315 return cast<StoreSDNode>(N)->getAlignment() >= 4; 316}]>; 317 318def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 319 return cast<LoadSDNode>(N)->getAlignment() < 4; 320}]>; 321def unaligned4store : PatFrag<(ops node:$val, node:$ptr), 322 (store node:$val, node:$ptr), [{ 323 return cast<StoreSDNode>(N)->getAlignment() < 4; 324}]>; 325def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 326 return cast<LoadSDNode>(N)->getAlignment() < 4; 327}]>; 328 329//===----------------------------------------------------------------------===// 330// PowerPC Flag Definitions. 331 332class isPPC64 { bit PPC64 = 1; } 333class isDOT { bit RC = 1; } 334 335class RegConstraint<string C> { 336 string Constraints = C; 337} 338class NoEncode<string E> { 339 string DisableEncoding = E; 340} 341 342 343//===----------------------------------------------------------------------===// 344// PowerPC Operand Definitions. 345 346// In the default PowerPC assembler syntax, registers are specified simply 347// by number, so they cannot be distinguished from immediate values (without 348// looking at the opcode). This means that the default operand matching logic 349// for the asm parser does not work, and we need to specify custom matchers. 350// Since those can only be specified with RegisterOperand classes and not 351// directly on the RegisterClass, all instructions patterns used by the asm 352// parser need to use a RegisterOperand (instead of a RegisterClass) for 353// all their register operands. 354// For this purpose, we define one RegisterOperand for each RegisterClass, 355// using the same name as the class, just in lower case. 356 357def PPCRegGPRCAsmOperand : AsmOperandClass { 358 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber"; 359} 360def gprc : RegisterOperand<GPRC> { 361 let ParserMatchClass = PPCRegGPRCAsmOperand; 362} 363def PPCRegG8RCAsmOperand : AsmOperandClass { 364 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber"; 365} 366def g8rc : RegisterOperand<G8RC> { 367 let ParserMatchClass = PPCRegG8RCAsmOperand; 368} 369def PPCRegGPRCNoR0AsmOperand : AsmOperandClass { 370 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber"; 371} 372def gprc_nor0 : RegisterOperand<GPRC_NOR0> { 373 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand; 374} 375def PPCRegG8RCNoX0AsmOperand : AsmOperandClass { 376 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber"; 377} 378def g8rc_nox0 : RegisterOperand<G8RC_NOX0> { 379 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand; 380} 381def PPCRegF8RCAsmOperand : AsmOperandClass { 382 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber"; 383} 384def f8rc : RegisterOperand<F8RC> { 385 let ParserMatchClass = PPCRegF8RCAsmOperand; 386} 387def PPCRegF4RCAsmOperand : AsmOperandClass { 388 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber"; 389} 390def f4rc : RegisterOperand<F4RC> { 391 let ParserMatchClass = PPCRegF4RCAsmOperand; 392} 393def PPCRegVRRCAsmOperand : AsmOperandClass { 394 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber"; 395} 396def vrrc : RegisterOperand<VRRC> { 397 let ParserMatchClass = PPCRegVRRCAsmOperand; 398} 399def PPCRegCRBITRCAsmOperand : AsmOperandClass { 400 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; 401} 402def crbitrc : RegisterOperand<CRBITRC> { 403 let ParserMatchClass = PPCRegCRBITRCAsmOperand; 404} 405def PPCRegCRRCAsmOperand : AsmOperandClass { 406 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber"; 407} 408def crrc : RegisterOperand<CRRC> { 409 let ParserMatchClass = PPCRegCRRCAsmOperand; 410} 411 412def PPCU2ImmAsmOperand : AsmOperandClass { 413 let Name = "U2Imm"; let PredicateMethod = "isU2Imm"; 414 let RenderMethod = "addImmOperands"; 415} 416def u2imm : Operand<i32> { 417 let PrintMethod = "printU2ImmOperand"; 418 let ParserMatchClass = PPCU2ImmAsmOperand; 419} 420def PPCS5ImmAsmOperand : AsmOperandClass { 421 let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; 422 let RenderMethod = "addImmOperands"; 423} 424def s5imm : Operand<i32> { 425 let PrintMethod = "printS5ImmOperand"; 426 let ParserMatchClass = PPCS5ImmAsmOperand; 427 let DecoderMethod = "decodeSImmOperand<5>"; 428} 429def PPCU5ImmAsmOperand : AsmOperandClass { 430 let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; 431 let RenderMethod = "addImmOperands"; 432} 433def u5imm : Operand<i32> { 434 let PrintMethod = "printU5ImmOperand"; 435 let ParserMatchClass = PPCU5ImmAsmOperand; 436 let DecoderMethod = "decodeUImmOperand<5>"; 437} 438def PPCU6ImmAsmOperand : AsmOperandClass { 439 let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; 440 let RenderMethod = "addImmOperands"; 441} 442def u6imm : Operand<i32> { 443 let PrintMethod = "printU6ImmOperand"; 444 let ParserMatchClass = PPCU6ImmAsmOperand; 445 let DecoderMethod = "decodeUImmOperand<6>"; 446} 447def PPCS16ImmAsmOperand : AsmOperandClass { 448 let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; 449 let RenderMethod = "addImmOperands"; 450} 451def s16imm : Operand<i32> { 452 let PrintMethod = "printS16ImmOperand"; 453 let EncoderMethod = "getImm16Encoding"; 454 let ParserMatchClass = PPCS16ImmAsmOperand; 455 let DecoderMethod = "decodeSImmOperand<16>"; 456} 457def PPCU16ImmAsmOperand : AsmOperandClass { 458 let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; 459 let RenderMethod = "addImmOperands"; 460} 461def u16imm : Operand<i32> { 462 let PrintMethod = "printU16ImmOperand"; 463 let EncoderMethod = "getImm16Encoding"; 464 let ParserMatchClass = PPCU16ImmAsmOperand; 465 let DecoderMethod = "decodeUImmOperand<16>"; 466} 467def PPCS17ImmAsmOperand : AsmOperandClass { 468 let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; 469 let RenderMethod = "addImmOperands"; 470} 471def s17imm : Operand<i32> { 472 // This operand type is used for addis/lis to allow the assembler parser 473 // to accept immediates in the range -65536..65535 for compatibility with 474 // the GNU assembler. The operand is treated as 16-bit otherwise. 475 let PrintMethod = "printS16ImmOperand"; 476 let EncoderMethod = "getImm16Encoding"; 477 let ParserMatchClass = PPCS17ImmAsmOperand; 478 let DecoderMethod = "decodeSImmOperand<16>"; 479} 480def PPCDirectBrAsmOperand : AsmOperandClass { 481 let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; 482 let RenderMethod = "addBranchTargetOperands"; 483} 484def directbrtarget : Operand<OtherVT> { 485 let PrintMethod = "printBranchOperand"; 486 let EncoderMethod = "getDirectBrEncoding"; 487 let ParserMatchClass = PPCDirectBrAsmOperand; 488} 489def absdirectbrtarget : Operand<OtherVT> { 490 let PrintMethod = "printAbsBranchOperand"; 491 let EncoderMethod = "getAbsDirectBrEncoding"; 492 let ParserMatchClass = PPCDirectBrAsmOperand; 493} 494def PPCCondBrAsmOperand : AsmOperandClass { 495 let Name = "CondBr"; let PredicateMethod = "isCondBr"; 496 let RenderMethod = "addBranchTargetOperands"; 497} 498def condbrtarget : Operand<OtherVT> { 499 let PrintMethod = "printBranchOperand"; 500 let EncoderMethod = "getCondBrEncoding"; 501 let ParserMatchClass = PPCCondBrAsmOperand; 502} 503def abscondbrtarget : Operand<OtherVT> { 504 let PrintMethod = "printAbsBranchOperand"; 505 let EncoderMethod = "getAbsCondBrEncoding"; 506 let ParserMatchClass = PPCCondBrAsmOperand; 507} 508def calltarget : Operand<iPTR> { 509 let PrintMethod = "printBranchOperand"; 510 let EncoderMethod = "getDirectBrEncoding"; 511 let ParserMatchClass = PPCDirectBrAsmOperand; 512} 513def abscalltarget : Operand<iPTR> { 514 let PrintMethod = "printAbsBranchOperand"; 515 let EncoderMethod = "getAbsDirectBrEncoding"; 516 let ParserMatchClass = PPCDirectBrAsmOperand; 517} 518def PPCCRBitMaskOperand : AsmOperandClass { 519 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask"; 520} 521def crbitm: Operand<i8> { 522 let PrintMethod = "printcrbitm"; 523 let EncoderMethod = "get_crbitm_encoding"; 524 let DecoderMethod = "decodeCRBitMOperand"; 525 let ParserMatchClass = PPCCRBitMaskOperand; 526} 527// Address operands 528// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 529def PPCRegGxRCNoR0Operand : AsmOperandClass { 530 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; 531} 532def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { 533 let ParserMatchClass = PPCRegGxRCNoR0Operand; 534} 535// A version of ptr_rc usable with the asm parser. 536def PPCRegGxRCOperand : AsmOperandClass { 537 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; 538} 539def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { 540 let ParserMatchClass = PPCRegGxRCOperand; 541} 542 543def PPCDispRIOperand : AsmOperandClass { 544 let Name = "DispRI"; let PredicateMethod = "isS16Imm"; 545 let RenderMethod = "addImmOperands"; 546} 547def dispRI : Operand<iPTR> { 548 let ParserMatchClass = PPCDispRIOperand; 549} 550def PPCDispRIXOperand : AsmOperandClass { 551 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; 552 let RenderMethod = "addImmOperands"; 553} 554def dispRIX : Operand<iPTR> { 555 let ParserMatchClass = PPCDispRIXOperand; 556} 557 558def memri : Operand<iPTR> { 559 let PrintMethod = "printMemRegImm"; 560 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 561 let EncoderMethod = "getMemRIEncoding"; 562 let DecoderMethod = "decodeMemRIOperands"; 563} 564def memrr : Operand<iPTR> { 565 let PrintMethod = "printMemRegReg"; 566 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); 567} 568def memrix : Operand<iPTR> { // memri where the imm is 4-aligned. 569 let PrintMethod = "printMemRegImm"; 570 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 571 let EncoderMethod = "getMemRIXEncoding"; 572 let DecoderMethod = "decodeMemRIXOperands"; 573} 574 575// A single-register address. This is used with the SjLj 576// pseudo-instructions. 577def memr : Operand<iPTR> { 578 let MIOperandInfo = (ops ptr_rc:$ptrreg); 579} 580def PPCTLSRegOperand : AsmOperandClass { 581 let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; 582 let RenderMethod = "addTLSRegOperands"; 583} 584def tlsreg32 : Operand<i32> { 585 let EncoderMethod = "getTLSRegEncoding"; 586 let ParserMatchClass = PPCTLSRegOperand; 587} 588 589// PowerPC Predicate operand. 590def pred : Operand<OtherVT> { 591 let PrintMethod = "printPredicateOperand"; 592 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg); 593} 594 595// Define PowerPC specific addressing mode. 596def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 597def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 598def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 599def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 600 601// The address in a single register. This is used with the SjLj 602// pseudo-instructions. 603def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 604 605/// This is just the offset part of iaddr, used for preinc. 606def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 607 608//===----------------------------------------------------------------------===// 609// PowerPC Instruction Predicate Definitions. 610def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">; 611def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">; 612def IsBookE : Predicate<"PPCSubTarget->isBookE()">; 613def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">; 614 615//===----------------------------------------------------------------------===// 616// PowerPC Multiclass Definitions. 617 618multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 619 string asmbase, string asmstr, InstrItinClass itin, 620 list<dag> pattern> { 621 let BaseName = asmbase in { 622 def NAME : XForm_6<opcode, xo, OOL, IOL, 623 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 624 pattern>, RecFormRel; 625 let Defs = [CR0] in 626 def o : XForm_6<opcode, xo, OOL, IOL, 627 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 628 []>, isDOT, RecFormRel; 629 } 630} 631 632multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 633 string asmbase, string asmstr, InstrItinClass itin, 634 list<dag> pattern> { 635 let BaseName = asmbase in { 636 let Defs = [CARRY] in 637 def NAME : XForm_6<opcode, xo, OOL, IOL, 638 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 639 pattern>, RecFormRel; 640 let Defs = [CARRY, CR0] in 641 def o : XForm_6<opcode, xo, OOL, IOL, 642 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 643 []>, isDOT, RecFormRel; 644 } 645} 646 647multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 648 string asmbase, string asmstr, InstrItinClass itin, 649 list<dag> pattern> { 650 let BaseName = asmbase in { 651 let Defs = [CARRY] in 652 def NAME : XForm_10<opcode, xo, OOL, IOL, 653 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 654 pattern>, RecFormRel; 655 let Defs = [CARRY, CR0] in 656 def o : XForm_10<opcode, xo, OOL, IOL, 657 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 658 []>, isDOT, RecFormRel; 659 } 660} 661 662multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 663 string asmbase, string asmstr, InstrItinClass itin, 664 list<dag> pattern> { 665 let BaseName = asmbase in { 666 def NAME : XForm_11<opcode, xo, OOL, IOL, 667 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 668 pattern>, RecFormRel; 669 let Defs = [CR0] in 670 def o : XForm_11<opcode, xo, OOL, IOL, 671 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 672 []>, isDOT, RecFormRel; 673 } 674} 675 676multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 677 string asmbase, string asmstr, InstrItinClass itin, 678 list<dag> pattern> { 679 let BaseName = asmbase in { 680 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 681 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 682 pattern>, RecFormRel; 683 let Defs = [CR0] in 684 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 685 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 686 []>, isDOT, RecFormRel; 687 } 688} 689 690multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 691 string asmbase, string asmstr, InstrItinClass itin, 692 list<dag> pattern> { 693 let BaseName = asmbase in { 694 let Defs = [CARRY] in 695 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 696 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 697 pattern>, RecFormRel; 698 let Defs = [CARRY, CR0] in 699 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 700 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 701 []>, isDOT, RecFormRel; 702 } 703} 704 705multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 706 string asmbase, string asmstr, InstrItinClass itin, 707 list<dag> pattern> { 708 let BaseName = asmbase in { 709 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 710 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 711 pattern>, RecFormRel; 712 let Defs = [CR0] in 713 def o : XOForm_3<opcode, xo, oe, OOL, IOL, 714 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 715 []>, isDOT, RecFormRel; 716 } 717} 718 719multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 720 string asmbase, string asmstr, InstrItinClass itin, 721 list<dag> pattern> { 722 let BaseName = asmbase in { 723 let Defs = [CARRY] in 724 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 725 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 726 pattern>, RecFormRel; 727 let Defs = [CARRY, CR0] in 728 def o : XOForm_3<opcode, xo, oe, OOL, IOL, 729 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 730 []>, isDOT, RecFormRel; 731 } 732} 733 734multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 735 string asmbase, string asmstr, InstrItinClass itin, 736 list<dag> pattern> { 737 let BaseName = asmbase in { 738 def NAME : MForm_2<opcode, OOL, IOL, 739 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 740 pattern>, RecFormRel; 741 let Defs = [CR0] in 742 def o : MForm_2<opcode, OOL, IOL, 743 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 744 []>, isDOT, RecFormRel; 745 } 746} 747 748multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 749 string asmbase, string asmstr, InstrItinClass itin, 750 list<dag> pattern> { 751 let BaseName = asmbase in { 752 def NAME : MDForm_1<opcode, xo, OOL, IOL, 753 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 754 pattern>, RecFormRel; 755 let Defs = [CR0] in 756 def o : MDForm_1<opcode, xo, OOL, IOL, 757 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 758 []>, isDOT, RecFormRel; 759 } 760} 761 762multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 763 string asmbase, string asmstr, InstrItinClass itin, 764 list<dag> pattern> { 765 let BaseName = asmbase in { 766 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 767 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 768 pattern>, RecFormRel; 769 let Defs = [CR0] in 770 def o : MDSForm_1<opcode, xo, OOL, IOL, 771 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 772 []>, isDOT, RecFormRel; 773 } 774} 775 776multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 777 string asmbase, string asmstr, InstrItinClass itin, 778 list<dag> pattern> { 779 let BaseName = asmbase in { 780 let Defs = [CARRY] in 781 def NAME : XSForm_1<opcode, xo, OOL, IOL, 782 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 783 pattern>, RecFormRel; 784 let Defs = [CARRY, CR0] in 785 def o : XSForm_1<opcode, xo, OOL, IOL, 786 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 787 []>, isDOT, RecFormRel; 788 } 789} 790 791multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 792 string asmbase, string asmstr, InstrItinClass itin, 793 list<dag> pattern> { 794 let BaseName = asmbase in { 795 def NAME : XForm_26<opcode, xo, OOL, IOL, 796 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 797 pattern>, RecFormRel; 798 let Defs = [CR1] in 799 def o : XForm_26<opcode, xo, OOL, IOL, 800 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 801 []>, isDOT, RecFormRel; 802 } 803} 804 805multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 806 string asmbase, string asmstr, InstrItinClass itin, 807 list<dag> pattern> { 808 let BaseName = asmbase in { 809 def NAME : XForm_28<opcode, xo, OOL, IOL, 810 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 811 pattern>, RecFormRel; 812 let Defs = [CR1] in 813 def o : XForm_28<opcode, xo, OOL, IOL, 814 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 815 []>, isDOT, RecFormRel; 816 } 817} 818 819multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 820 string asmbase, string asmstr, InstrItinClass itin, 821 list<dag> pattern> { 822 let BaseName = asmbase in { 823 def NAME : AForm_1<opcode, xo, OOL, IOL, 824 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 825 pattern>, RecFormRel; 826 let Defs = [CR1] in 827 def o : AForm_1<opcode, xo, OOL, IOL, 828 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 829 []>, isDOT, RecFormRel; 830 } 831} 832 833multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 834 string asmbase, string asmstr, InstrItinClass itin, 835 list<dag> pattern> { 836 let BaseName = asmbase in { 837 def NAME : AForm_2<opcode, xo, OOL, IOL, 838 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 839 pattern>, RecFormRel; 840 let Defs = [CR1] in 841 def o : AForm_2<opcode, xo, OOL, IOL, 842 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 843 []>, isDOT, RecFormRel; 844 } 845} 846 847multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 848 string asmbase, string asmstr, InstrItinClass itin, 849 list<dag> pattern> { 850 let BaseName = asmbase in { 851 def NAME : AForm_3<opcode, xo, OOL, IOL, 852 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 853 pattern>, RecFormRel; 854 let Defs = [CR1] in 855 def o : AForm_3<opcode, xo, OOL, IOL, 856 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 857 []>, isDOT, RecFormRel; 858 } 859} 860 861//===----------------------------------------------------------------------===// 862// PowerPC Instruction Definitions. 863 864// Pseudo-instructions: 865 866let hasCtrlDep = 1 in { 867let Defs = [R1], Uses = [R1] in { 868def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt", 869 [(callseq_start timm:$amt)]>; 870def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2", 871 [(callseq_end timm:$amt1, timm:$amt2)]>; 872} 873 874def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS), 875 "UPDATE_VRSAVE $rD, $rS", []>; 876} 877 878let Defs = [R1], Uses = [R1] in 879def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 880 [(set i32:$result, 881 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 882 883// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 884// instruction selection into a branch sequence. 885let usesCustomInserter = 1, // Expanded after instruction selection. 886 PPC970_Single = 1 in { 887 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 888 // because either operand might become the first operand in an isel, and 889 // that operand cannot be r0. 890 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond, 891 gprc_nor0:$T, gprc_nor0:$F, 892 i32imm:$BROPC), "#SELECT_CC_I4", 893 []>; 894 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond, 895 g8rc_nox0:$T, g8rc_nox0:$F, 896 i32imm:$BROPC), "#SELECT_CC_I8", 897 []>; 898 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 899 i32imm:$BROPC), "#SELECT_CC_F4", 900 []>; 901 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 902 i32imm:$BROPC), "#SELECT_CC_F8", 903 []>; 904 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 905 i32imm:$BROPC), "#SELECT_CC_VRRC", 906 []>; 907 908 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 909 // register bit directly. 910 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond, 911 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 912 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 913 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 914 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 915 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 916 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 917 f4rc:$T, f4rc:$F), "#SELECT_F4", 918 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 919 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 920 f8rc:$T, f8rc:$F), "#SELECT_F8", 921 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 922 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 923 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 924 [(set v4i32:$dst, 925 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 926} 927 928// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 929// scavenge a register for it. 930let mayStore = 1 in { 931def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F), 932 "#SPILL_CR", []>; 933def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F), 934 "#SPILL_CRBIT", []>; 935} 936 937// RESTORE_CR - Indicate that we're restoring the CR register (previously 938// spilled), so we'll need to scavenge a register for it. 939let mayLoad = 1 in { 940def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F), 941 "#RESTORE_CR", []>; 942def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F), 943 "#RESTORE_CRBIT", []>; 944} 945 946let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 947 let isReturn = 1, Uses = [LR, RM] in 948 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 949 [(retflag)]>; 950 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 951 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 952 []>; 953 954 let isCodeGenOnly = 1 in { 955 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 956 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 957 []>; 958 959 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 960 "bcctr 12, $bi, 0", IIC_BrB, []>; 961 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 962 "bcctr 4, $bi, 0", IIC_BrB, []>; 963 } 964 } 965} 966 967let Defs = [LR] in 968 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>, 969 PPC970_Unit_BRU; 970 971let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 972 let isBarrier = 1 in { 973 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 974 "b $dst", IIC_BrB, 975 [(br bb:$dst)]>; 976 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), 977 "ba $dst", IIC_BrB, []>; 978 } 979 980 // BCC represents an arbitrary conditional branch on a predicate. 981 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 982 // a two-value operand where a dag node expects two operands. :( 983 let isCodeGenOnly = 1 in { 984 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 985 "b${cond:cc}${cond:pm} ${cond:reg}, $dst" 986 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; 987 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), 988 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; 989 990 let isReturn = 1, Uses = [LR, RM] in 991 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), 992 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 993 } 994 995 let isCodeGenOnly = 1 in { 996 let Pattern = [(brcond i1:$bi, bb:$dst)] in 997 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 998 "bc 12, $bi, $dst">; 999 1000 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in 1001 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1002 "bc 4, $bi, $dst">; 1003 1004 let isReturn = 1, Uses = [LR, RM] in 1005 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), 1006 "bclr 12, $bi, 0", IIC_BrB, []>; 1007 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), 1008 "bclr 4, $bi, 0", IIC_BrB, []>; 1009 } 1010 1011 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1012 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1013 "bdzlr", IIC_BrB, []>; 1014 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1015 "bdnzlr", IIC_BrB, []>; 1016 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1017 "bdzlr+", IIC_BrB, []>; 1018 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1019 "bdnzlr+", IIC_BrB, []>; 1020 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1021 "bdzlr-", IIC_BrB, []>; 1022 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1023 "bdnzlr-", IIC_BrB, []>; 1024 } 1025 1026 let Defs = [CTR], Uses = [CTR] in { 1027 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 1028 "bdz $dst">; 1029 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 1030 "bdnz $dst">; 1031 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), 1032 "bdza $dst">; 1033 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), 1034 "bdnza $dst">; 1035 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), 1036 "bdz+ $dst">; 1037 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), 1038 "bdnz+ $dst">; 1039 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), 1040 "bdza+ $dst">; 1041 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), 1042 "bdnza+ $dst">; 1043 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), 1044 "bdz- $dst">; 1045 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), 1046 "bdnz- $dst">; 1047 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), 1048 "bdza- $dst">; 1049 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), 1050 "bdnza- $dst">; 1051 } 1052} 1053 1054// The unconditional BCL used by the SjLj setjmp code. 1055let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in { 1056 let Defs = [LR], Uses = [RM] in { 1057 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), 1058 "bcl 20, 31, $dst">; 1059 } 1060} 1061 1062let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1063 // Convenient aliases for call instructions 1064 let Uses = [RM] in { 1065 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1066 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1067 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1068 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; 1069 1070 let isCodeGenOnly = 1 in { 1071 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), 1072 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; 1073 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1074 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; 1075 1076 def BCL : BForm_4<16, 12, 0, 1, (outs), 1077 (ins crbitrc:$bi, condbrtarget:$dst), 1078 "bcl 12, $bi, $dst">; 1079 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1080 (ins crbitrc:$bi, condbrtarget:$dst), 1081 "bcl 4, $bi, $dst">; 1082 } 1083 } 1084 let Uses = [CTR, RM] in { 1085 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1086 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1087 Requires<[In32BitMode]>; 1088 1089 let isCodeGenOnly = 1 in { 1090 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 1091 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1092 []>; 1093 1094 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 1095 "bcctrl 12, $bi, 0", IIC_BrB, []>; 1096 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 1097 "bcctrl 4, $bi, 0", IIC_BrB, []>; 1098 } 1099 } 1100 let Uses = [LR, RM] in { 1101 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1102 "blrl", IIC_BrB, []>; 1103 1104 let isCodeGenOnly = 1 in { 1105 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), 1106 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1107 []>; 1108 1109 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), 1110 "bclrl 12, $bi, 0", IIC_BrB, []>; 1111 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), 1112 "bclrl 4, $bi, 0", IIC_BrB, []>; 1113 } 1114 } 1115 let Defs = [CTR], Uses = [CTR, RM] in { 1116 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), 1117 "bdzl $dst">; 1118 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), 1119 "bdnzl $dst">; 1120 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), 1121 "bdzla $dst">; 1122 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), 1123 "bdnzla $dst">; 1124 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), 1125 "bdzl+ $dst">; 1126 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), 1127 "bdnzl+ $dst">; 1128 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), 1129 "bdzla+ $dst">; 1130 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), 1131 "bdnzla+ $dst">; 1132 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), 1133 "bdzl- $dst">; 1134 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), 1135 "bdnzl- $dst">; 1136 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), 1137 "bdzla- $dst">; 1138 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), 1139 "bdnzla- $dst">; 1140 } 1141 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1142 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1143 "bdzlrl", IIC_BrB, []>; 1144 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1145 "bdnzlrl", IIC_BrB, []>; 1146 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1147 "bdzlrl+", IIC_BrB, []>; 1148 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1149 "bdnzlrl+", IIC_BrB, []>; 1150 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1151 "bdzlrl-", IIC_BrB, []>; 1152 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1153 "bdnzlrl-", IIC_BrB, []>; 1154 } 1155} 1156 1157let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1158def TCRETURNdi :Pseudo< (outs), 1159 (ins calltarget:$dst, i32imm:$offset), 1160 "#TC_RETURNd $dst $offset", 1161 []>; 1162 1163 1164let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1165def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1166 "#TC_RETURNa $func $offset", 1167 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1168 1169let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1170def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1171 "#TC_RETURNr $dst $offset", 1172 []>; 1173 1174 1175let isCodeGenOnly = 1 in { 1176 1177let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1178 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1179def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1180 []>, Requires<[In32BitMode]>; 1181 1182let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1183 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1184def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 1185 "b $dst", IIC_BrB, 1186 []>; 1187 1188let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1189 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1190def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 1191 "ba $dst", IIC_BrB, 1192 []>; 1193 1194} 1195 1196let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 1197 let Defs = [CTR] in 1198 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 1199 "#EH_SJLJ_SETJMP32", 1200 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1201 Requires<[In32BitMode]>; 1202 let isTerminator = 1 in 1203 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf), 1204 "#EH_SJLJ_LONGJMP32", 1205 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1206 Requires<[In32BitMode]>; 1207} 1208 1209let isBranch = 1, isTerminator = 1 in { 1210 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst), 1211 "#EH_SjLj_Setup\t$dst", []>; 1212} 1213 1214// System call. 1215let PPC970_Unit = 7 in { 1216 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), 1217 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; 1218} 1219 1220// DCB* instructions. 1221def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", 1222 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 1223 PPC970_DGroup_Single; 1224def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst", 1225 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 1226 PPC970_DGroup_Single; 1227def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", 1228 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 1229 PPC970_DGroup_Single; 1230def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", 1231 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 1232 PPC970_DGroup_Single; 1233def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst", 1234 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 1235 PPC970_DGroup_Single; 1236def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst", 1237 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 1238 PPC970_DGroup_Single; 1239def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", 1240 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 1241 PPC970_DGroup_Single; 1242def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", 1243 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 1244 PPC970_DGroup_Single; 1245 1246def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 1247 (DCBT xoaddr:$dst)>; 1248 1249// Atomic operations 1250let usesCustomInserter = 1 in { 1251 let Defs = [CR0] in { 1252 def ATOMIC_LOAD_ADD_I8 : Pseudo< 1253 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1254 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>; 1255 def ATOMIC_LOAD_SUB_I8 : Pseudo< 1256 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1257 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>; 1258 def ATOMIC_LOAD_AND_I8 : Pseudo< 1259 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1260 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>; 1261 def ATOMIC_LOAD_OR_I8 : Pseudo< 1262 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1263 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>; 1264 def ATOMIC_LOAD_XOR_I8 : Pseudo< 1265 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1266 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>; 1267 def ATOMIC_LOAD_NAND_I8 : Pseudo< 1268 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1269 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>; 1270 def ATOMIC_LOAD_ADD_I16 : Pseudo< 1271 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1272 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>; 1273 def ATOMIC_LOAD_SUB_I16 : Pseudo< 1274 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1275 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>; 1276 def ATOMIC_LOAD_AND_I16 : Pseudo< 1277 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1278 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>; 1279 def ATOMIC_LOAD_OR_I16 : Pseudo< 1280 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1281 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>; 1282 def ATOMIC_LOAD_XOR_I16 : Pseudo< 1283 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1284 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>; 1285 def ATOMIC_LOAD_NAND_I16 : Pseudo< 1286 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1287 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>; 1288 def ATOMIC_LOAD_ADD_I32 : Pseudo< 1289 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1290 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>; 1291 def ATOMIC_LOAD_SUB_I32 : Pseudo< 1292 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1293 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>; 1294 def ATOMIC_LOAD_AND_I32 : Pseudo< 1295 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1296 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>; 1297 def ATOMIC_LOAD_OR_I32 : Pseudo< 1298 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1299 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>; 1300 def ATOMIC_LOAD_XOR_I32 : Pseudo< 1301 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1302 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>; 1303 def ATOMIC_LOAD_NAND_I32 : Pseudo< 1304 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1305 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>; 1306 1307 def ATOMIC_CMP_SWAP_I8 : Pseudo< 1308 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1309 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>; 1310 def ATOMIC_CMP_SWAP_I16 : Pseudo< 1311 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1312 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>; 1313 def ATOMIC_CMP_SWAP_I32 : Pseudo< 1314 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1315 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>; 1316 1317 def ATOMIC_SWAP_I8 : Pseudo< 1318 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1319 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>; 1320 def ATOMIC_SWAP_I16 : Pseudo< 1321 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1322 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>; 1323 def ATOMIC_SWAP_I32 : Pseudo< 1324 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1325 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>; 1326 } 1327} 1328 1329// Instructions to support atomic operations 1330def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src), 1331 "lwarx $rD, $src", IIC_LdStLWARX, 1332 [(set i32:$rD, (PPClarx xoaddr:$src))]>; 1333 1334let Defs = [CR0] in 1335def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst), 1336 "stwcx. $rS, $dst", IIC_LdStSTWCX, 1337 [(PPCstcx i32:$rS, xoaddr:$dst)]>, 1338 isDOT; 1339 1340let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 1341def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 1342 1343def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm), 1344 "twi $to, $rA, $imm", IIC_IntTrapW, []>; 1345def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB), 1346 "tw $to, $rA, $rB", IIC_IntTrapW, []>; 1347def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm), 1348 "tdi $to, $rA, $imm", IIC_IntTrapD, []>; 1349def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB), 1350 "td $to, $rA, $rB", IIC_IntTrapD, []>; 1351 1352//===----------------------------------------------------------------------===// 1353// PPC32 Load Instructions. 1354// 1355 1356// Unindexed (r+i) Loads. 1357let canFoldAsLoad = 1, PPC970_Unit = 2 in { 1358def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), 1359 "lbz $rD, $src", IIC_LdStLoad, 1360 [(set i32:$rD, (zextloadi8 iaddr:$src))]>; 1361def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), 1362 "lha $rD, $src", IIC_LdStLHA, 1363 [(set i32:$rD, (sextloadi16 iaddr:$src))]>, 1364 PPC970_DGroup_Cracked; 1365def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), 1366 "lhz $rD, $src", IIC_LdStLoad, 1367 [(set i32:$rD, (zextloadi16 iaddr:$src))]>; 1368def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), 1369 "lwz $rD, $src", IIC_LdStLoad, 1370 [(set i32:$rD, (load iaddr:$src))]>; 1371 1372def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), 1373 "lfs $rD, $src", IIC_LdStLFD, 1374 [(set f32:$rD, (load iaddr:$src))]>; 1375def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), 1376 "lfd $rD, $src", IIC_LdStLFD, 1377 [(set f64:$rD, (load iaddr:$src))]>; 1378 1379 1380// Unindexed (r+i) Loads with Update (preinc). 1381let mayLoad = 1, neverHasSideEffects = 1 in { 1382def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1383 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1384 []>, RegConstraint<"$addr.reg = $ea_result">, 1385 NoEncode<"$ea_result">; 1386 1387def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1388 "lhau $rD, $addr", IIC_LdStLHAU, 1389 []>, RegConstraint<"$addr.reg = $ea_result">, 1390 NoEncode<"$ea_result">; 1391 1392def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1393 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1394 []>, RegConstraint<"$addr.reg = $ea_result">, 1395 NoEncode<"$ea_result">; 1396 1397def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1398 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1399 []>, RegConstraint<"$addr.reg = $ea_result">, 1400 NoEncode<"$ea_result">; 1401 1402def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1403 "lfsu $rD, $addr", IIC_LdStLFDU, 1404 []>, RegConstraint<"$addr.reg = $ea_result">, 1405 NoEncode<"$ea_result">; 1406 1407def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1408 "lfdu $rD, $addr", IIC_LdStLFDU, 1409 []>, RegConstraint<"$addr.reg = $ea_result">, 1410 NoEncode<"$ea_result">; 1411 1412 1413// Indexed (r+r) Loads with Update (preinc). 1414def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1415 (ins memrr:$addr), 1416 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1417 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1418 NoEncode<"$ea_result">; 1419 1420def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1421 (ins memrr:$addr), 1422 "lhaux $rD, $addr", IIC_LdStLHAUX, 1423 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1424 NoEncode<"$ea_result">; 1425 1426def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1427 (ins memrr:$addr), 1428 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1429 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1430 NoEncode<"$ea_result">; 1431 1432def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1433 (ins memrr:$addr), 1434 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1435 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1436 NoEncode<"$ea_result">; 1437 1438def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), 1439 (ins memrr:$addr), 1440 "lfsux $rD, $addr", IIC_LdStLFDUX, 1441 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1442 NoEncode<"$ea_result">; 1443 1444def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), 1445 (ins memrr:$addr), 1446 "lfdux $rD, $addr", IIC_LdStLFDUX, 1447 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1448 NoEncode<"$ea_result">; 1449} 1450} 1451 1452// Indexed (r+r) Loads. 1453// 1454let canFoldAsLoad = 1, PPC970_Unit = 2 in { 1455def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src), 1456 "lbzx $rD, $src", IIC_LdStLoad, 1457 [(set i32:$rD, (zextloadi8 xaddr:$src))]>; 1458def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src), 1459 "lhax $rD, $src", IIC_LdStLHA, 1460 [(set i32:$rD, (sextloadi16 xaddr:$src))]>, 1461 PPC970_DGroup_Cracked; 1462def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src), 1463 "lhzx $rD, $src", IIC_LdStLoad, 1464 [(set i32:$rD, (zextloadi16 xaddr:$src))]>; 1465def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src), 1466 "lwzx $rD, $src", IIC_LdStLoad, 1467 [(set i32:$rD, (load xaddr:$src))]>; 1468 1469 1470def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src), 1471 "lhbrx $rD, $src", IIC_LdStLoad, 1472 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>; 1473def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src), 1474 "lwbrx $rD, $src", IIC_LdStLoad, 1475 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>; 1476 1477def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src), 1478 "lfsx $frD, $src", IIC_LdStLFD, 1479 [(set f32:$frD, (load xaddr:$src))]>; 1480def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src), 1481 "lfdx $frD, $src", IIC_LdStLFD, 1482 [(set f64:$frD, (load xaddr:$src))]>; 1483 1484def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src), 1485 "lfiwax $frD, $src", IIC_LdStLFD, 1486 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>; 1487def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src), 1488 "lfiwzx $frD, $src", IIC_LdStLFD, 1489 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>; 1490} 1491 1492// Load Multiple 1493def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), 1494 "lmw $rD, $src", IIC_LdStLMW, []>; 1495 1496//===----------------------------------------------------------------------===// 1497// PPC32 Store Instructions. 1498// 1499 1500// Unindexed (r+i) Stores. 1501let PPC970_Unit = 2 in { 1502def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src), 1503 "stb $rS, $src", IIC_LdStStore, 1504 [(truncstorei8 i32:$rS, iaddr:$src)]>; 1505def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src), 1506 "sth $rS, $src", IIC_LdStStore, 1507 [(truncstorei16 i32:$rS, iaddr:$src)]>; 1508def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src), 1509 "stw $rS, $src", IIC_LdStStore, 1510 [(store i32:$rS, iaddr:$src)]>; 1511def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), 1512 "stfs $rS, $dst", IIC_LdStSTFD, 1513 [(store f32:$rS, iaddr:$dst)]>; 1514def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), 1515 "stfd $rS, $dst", IIC_LdStSTFD, 1516 [(store f64:$rS, iaddr:$dst)]>; 1517} 1518 1519// Unindexed (r+i) Stores with Update (preinc). 1520let PPC970_Unit = 2, mayStore = 1 in { 1521def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1522 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 1523 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1524def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1525 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 1526 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1527def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1528 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 1529 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1530def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), 1531 "stfsu $rS, $dst", IIC_LdStSTFDU, []>, 1532 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1533def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), 1534 "stfdu $rS, $dst", IIC_LdStSTFDU, []>, 1535 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1536} 1537 1538// Patterns to match the pre-inc stores. We can't put the patterns on 1539// the instruction definitions directly as ISel wants the address base 1540// and offset to be separate operands, not a single complex operand. 1541def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1542 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 1543def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1544 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 1545def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1546 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 1547def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1548 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 1549def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1550 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 1551 1552// Indexed (r+r) Stores. 1553let PPC970_Unit = 2 in { 1554def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst), 1555 "stbx $rS, $dst", IIC_LdStStore, 1556 [(truncstorei8 i32:$rS, xaddr:$dst)]>, 1557 PPC970_DGroup_Cracked; 1558def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst), 1559 "sthx $rS, $dst", IIC_LdStStore, 1560 [(truncstorei16 i32:$rS, xaddr:$dst)]>, 1561 PPC970_DGroup_Cracked; 1562def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst), 1563 "stwx $rS, $dst", IIC_LdStStore, 1564 [(store i32:$rS, xaddr:$dst)]>, 1565 PPC970_DGroup_Cracked; 1566 1567def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst), 1568 "sthbrx $rS, $dst", IIC_LdStStore, 1569 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>, 1570 PPC970_DGroup_Cracked; 1571def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst), 1572 "stwbrx $rS, $dst", IIC_LdStStore, 1573 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>, 1574 PPC970_DGroup_Cracked; 1575 1576def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), 1577 "stfiwx $frS, $dst", IIC_LdStSTFD, 1578 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>; 1579 1580def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), 1581 "stfsx $frS, $dst", IIC_LdStSTFD, 1582 [(store f32:$frS, xaddr:$dst)]>; 1583def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), 1584 "stfdx $frS, $dst", IIC_LdStSTFD, 1585 [(store f64:$frS, xaddr:$dst)]>; 1586} 1587 1588// Indexed (r+r) Stores with Update (preinc). 1589let PPC970_Unit = 2, mayStore = 1 in { 1590def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1591 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 1592 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1593 PPC970_DGroup_Cracked; 1594def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1595 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 1596 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1597 PPC970_DGroup_Cracked; 1598def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1599 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 1600 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1601 PPC970_DGroup_Cracked; 1602def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst), 1603 "stfsux $rS, $dst", IIC_LdStSTFDU, []>, 1604 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1605 PPC970_DGroup_Cracked; 1606def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst), 1607 "stfdux $rS, $dst", IIC_LdStSTFDU, []>, 1608 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1609 PPC970_DGroup_Cracked; 1610} 1611 1612// Patterns to match the pre-inc stores. We can't put the patterns on 1613// the instruction definitions directly as ISel wants the address base 1614// and offset to be separate operands, not a single complex operand. 1615def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1616 (STBUX $rS, $ptrreg, $ptroff)>; 1617def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1618 (STHUX $rS, $ptrreg, $ptroff)>; 1619def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1620 (STWUX $rS, $ptrreg, $ptroff)>; 1621def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1622 (STFSUX $rS, $ptrreg, $ptroff)>; 1623def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1624 (STFDUX $rS, $ptrreg, $ptroff)>; 1625 1626// Store Multiple 1627def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), 1628 "stmw $rS, $dst", IIC_LdStLMW, []>; 1629 1630def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L), 1631 "sync $L", IIC_LdStSync, []>, Requires<[IsNotBookE]>; 1632 1633let isCodeGenOnly = 1 in { 1634 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 1635 "msync", IIC_LdStSync, []>, Requires<[IsBookE]> { 1636 let L = 0; 1637 } 1638} 1639 1640def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>; 1641def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>; 1642 1643//===----------------------------------------------------------------------===// 1644// PPC32 Arithmetic Instructions. 1645// 1646 1647let PPC970_Unit = 1 in { // FXU Operations. 1648def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), 1649 "addi $rD, $rA, $imm", IIC_IntSimple, 1650 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; 1651let BaseName = "addic" in { 1652let Defs = [CARRY] in 1653def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1654 "addic $rD, $rA, $imm", IIC_IntGeneral, 1655 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, 1656 RecFormRel, PPC970_DGroup_Cracked; 1657let Defs = [CARRY, CR0] in 1658def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1659 "addic. $rD, $rA, $imm", IIC_IntGeneral, 1660 []>, isDOT, RecFormRel; 1661} 1662def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), 1663 "addis $rD, $rA, $imm", IIC_IntSimple, 1664 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; 1665let isCodeGenOnly = 1 in 1666def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), 1667 "la $rD, $sym($rA)", IIC_IntGeneral, 1668 [(set i32:$rD, (add i32:$rA, 1669 (PPClo tglobaladdr:$sym, 0)))]>; 1670def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1671 "mulli $rD, $rA, $imm", IIC_IntMulLI, 1672 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; 1673let Defs = [CARRY] in 1674def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1675 "subfic $rD, $rA, $imm", IIC_IntGeneral, 1676 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; 1677 1678let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 1679 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), 1680 "li $rD, $imm", IIC_IntSimple, 1681 [(set i32:$rD, imm32SExt16:$imm)]>; 1682 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), 1683 "lis $rD, $imm", IIC_IntSimple, 1684 [(set i32:$rD, imm16ShiftedSExt:$imm)]>; 1685} 1686} 1687 1688let PPC970_Unit = 1 in { // FXU Operations. 1689let Defs = [CR0] in { 1690def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1691 "andi. $dst, $src1, $src2", IIC_IntGeneral, 1692 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, 1693 isDOT; 1694def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1695 "andis. $dst, $src1, $src2", IIC_IntGeneral, 1696 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, 1697 isDOT; 1698} 1699def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1700 "ori $dst, $src1, $src2", IIC_IntSimple, 1701 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; 1702def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1703 "oris $dst, $src1, $src2", IIC_IntSimple, 1704 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; 1705def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1706 "xori $dst, $src1, $src2", IIC_IntSimple, 1707 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; 1708def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1709 "xoris $dst, $src1, $src2", IIC_IntSimple, 1710 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; 1711 1712def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 1713 []>; 1714let isCodeGenOnly = 1 in { 1715// The POWER6 and POWER7 have special group-terminating nops. 1716def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 1717 "ori 1, 1, 0", IIC_IntSimple, []>; 1718def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 1719 "ori 2, 2, 0", IIC_IntSimple, []>; 1720} 1721 1722let isCompare = 1, neverHasSideEffects = 1 in { 1723 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), 1724 "cmpwi $crD, $rA, $imm", IIC_IntCompare>; 1725 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), 1726 "cmplwi $dst, $src1, $src2", IIC_IntCompare>; 1727} 1728} 1729 1730let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations. 1731let isCommutable = 1 in { 1732defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1733 "nand", "$rA, $rS, $rB", IIC_IntSimple, 1734 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; 1735defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1736 "and", "$rA, $rS, $rB", IIC_IntSimple, 1737 [(set i32:$rA, (and i32:$rS, i32:$rB))]>; 1738} // isCommutable 1739defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1740 "andc", "$rA, $rS, $rB", IIC_IntSimple, 1741 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; 1742let isCommutable = 1 in { 1743defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1744 "or", "$rA, $rS, $rB", IIC_IntSimple, 1745 [(set i32:$rA, (or i32:$rS, i32:$rB))]>; 1746defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1747 "nor", "$rA, $rS, $rB", IIC_IntSimple, 1748 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; 1749} // isCommutable 1750defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1751 "orc", "$rA, $rS, $rB", IIC_IntSimple, 1752 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; 1753let isCommutable = 1 in { 1754defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1755 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 1756 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; 1757defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1758 "xor", "$rA, $rS, $rB", IIC_IntSimple, 1759 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; 1760} // isCommutable 1761defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1762 "slw", "$rA, $rS, $rB", IIC_IntGeneral, 1763 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>; 1764defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1765 "srw", "$rA, $rS, $rB", IIC_IntGeneral, 1766 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>; 1767defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1768 "sraw", "$rA, $rS, $rB", IIC_IntShift, 1769 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>; 1770} 1771 1772let PPC970_Unit = 1 in { // FXU Operations. 1773let neverHasSideEffects = 1 in { 1774defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), 1775 "srawi", "$rA, $rS, $SH", IIC_IntShift, 1776 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>; 1777defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), 1778 "cntlzw", "$rA, $rS", IIC_IntGeneral, 1779 [(set i32:$rA, (ctlz i32:$rS))]>; 1780defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), 1781 "extsb", "$rA, $rS", IIC_IntSimple, 1782 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>; 1783defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), 1784 "extsh", "$rA, $rS", IIC_IntSimple, 1785 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>; 1786} 1787let isCompare = 1, neverHasSideEffects = 1 in { 1788 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 1789 "cmpw $crD, $rA, $rB", IIC_IntCompare>; 1790 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 1791 "cmplw $crD, $rA, $rB", IIC_IntCompare>; 1792} 1793} 1794let PPC970_Unit = 3 in { // FPU Operations. 1795//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 1796// "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 1797let isCompare = 1, neverHasSideEffects = 1 in { 1798 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 1799 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 1800 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1801 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 1802 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 1803} 1804 1805let Uses = [RM] in { 1806 let neverHasSideEffects = 1 in { 1807 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), 1808 "fctiw", "$frD, $frB", IIC_FPGeneral, 1809 []>; 1810 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), 1811 "fctiwz", "$frD, $frB", IIC_FPGeneral, 1812 [(set f64:$frD, (PPCfctiwz f64:$frB))]>; 1813 1814 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), 1815 "frsp", "$frD, $frB", IIC_FPGeneral, 1816 [(set f32:$frD, (fround f64:$frB))]>; 1817 1818 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1819 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), 1820 "frin", "$frD, $frB", IIC_FPGeneral, 1821 [(set f64:$frD, (frnd f64:$frB))]>; 1822 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), 1823 "frin", "$frD, $frB", IIC_FPGeneral, 1824 [(set f32:$frD, (frnd f32:$frB))]>; 1825 } 1826 1827 let neverHasSideEffects = 1 in { 1828 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1829 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), 1830 "frip", "$frD, $frB", IIC_FPGeneral, 1831 [(set f64:$frD, (fceil f64:$frB))]>; 1832 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), 1833 "frip", "$frD, $frB", IIC_FPGeneral, 1834 [(set f32:$frD, (fceil f32:$frB))]>; 1835 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1836 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), 1837 "friz", "$frD, $frB", IIC_FPGeneral, 1838 [(set f64:$frD, (ftrunc f64:$frB))]>; 1839 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), 1840 "friz", "$frD, $frB", IIC_FPGeneral, 1841 [(set f32:$frD, (ftrunc f32:$frB))]>; 1842 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1843 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), 1844 "frim", "$frD, $frB", IIC_FPGeneral, 1845 [(set f64:$frD, (ffloor f64:$frB))]>; 1846 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), 1847 "frim", "$frD, $frB", IIC_FPGeneral, 1848 [(set f32:$frD, (ffloor f32:$frB))]>; 1849 1850 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), 1851 "fsqrt", "$frD, $frB", IIC_FPSqrtD, 1852 [(set f64:$frD, (fsqrt f64:$frB))]>; 1853 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), 1854 "fsqrts", "$frD, $frB", IIC_FPSqrtS, 1855 [(set f32:$frD, (fsqrt f32:$frB))]>; 1856 } 1857 } 1858} 1859 1860/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 1861/// often coalesced away and we don't want the dispatch group builder to think 1862/// that they will fill slots (which could cause the load of a LSU reject to 1863/// sneak into a d-group with a store). 1864let neverHasSideEffects = 1 in 1865defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), 1866 "fmr", "$frD, $frB", IIC_FPGeneral, 1867 []>, // (set f32:$frD, f32:$frB) 1868 PPC970_Unit_Pseudo; 1869 1870let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations. 1871// These are artificially split into two different forms, for 4/8 byte FP. 1872defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), 1873 "fabs", "$frD, $frB", IIC_FPGeneral, 1874 [(set f32:$frD, (fabs f32:$frB))]>; 1875let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1876defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), 1877 "fabs", "$frD, $frB", IIC_FPGeneral, 1878 [(set f64:$frD, (fabs f64:$frB))]>; 1879defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), 1880 "fnabs", "$frD, $frB", IIC_FPGeneral, 1881 [(set f32:$frD, (fneg (fabs f32:$frB)))]>; 1882let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1883defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), 1884 "fnabs", "$frD, $frB", IIC_FPGeneral, 1885 [(set f64:$frD, (fneg (fabs f64:$frB)))]>; 1886defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), 1887 "fneg", "$frD, $frB", IIC_FPGeneral, 1888 [(set f32:$frD, (fneg f32:$frB))]>; 1889let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1890defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), 1891 "fneg", "$frD, $frB", IIC_FPGeneral, 1892 [(set f64:$frD, (fneg f64:$frB))]>; 1893 1894defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB), 1895 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 1896 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>; 1897let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1898defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB), 1899 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 1900 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>; 1901 1902// Reciprocal estimates. 1903defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), 1904 "fre", "$frD, $frB", IIC_FPGeneral, 1905 [(set f64:$frD, (PPCfre f64:$frB))]>; 1906defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), 1907 "fres", "$frD, $frB", IIC_FPGeneral, 1908 [(set f32:$frD, (PPCfre f32:$frB))]>; 1909defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), 1910 "frsqrte", "$frD, $frB", IIC_FPGeneral, 1911 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; 1912defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), 1913 "frsqrtes", "$frD, $frB", IIC_FPGeneral, 1914 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; 1915} 1916 1917// XL-Form instructions. condition register logical ops. 1918// 1919let neverHasSideEffects = 1 in 1920def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 1921 "mcrf $BF, $BFA", IIC_BrMCR>, 1922 PPC970_DGroup_First, PPC970_Unit_CRU; 1923 1924let isCommutable = 1 in { 1925def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 1926 (ins crbitrc:$CRA, crbitrc:$CRB), 1927 "crand $CRD, $CRA, $CRB", IIC_BrCR, 1928 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 1929 1930def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 1931 (ins crbitrc:$CRA, crbitrc:$CRB), 1932 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 1933 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 1934 1935def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 1936 (ins crbitrc:$CRA, crbitrc:$CRB), 1937 "cror $CRD, $CRA, $CRB", IIC_BrCR, 1938 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 1939 1940def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 1941 (ins crbitrc:$CRA, crbitrc:$CRB), 1942 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 1943 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 1944 1945def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 1946 (ins crbitrc:$CRA, crbitrc:$CRB), 1947 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 1948 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 1949 1950def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 1951 (ins crbitrc:$CRA, crbitrc:$CRB), 1952 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 1953 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 1954} // isCommutable 1955 1956def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 1957 (ins crbitrc:$CRA, crbitrc:$CRB), 1958 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 1959 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 1960 1961def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 1962 (ins crbitrc:$CRA, crbitrc:$CRB), 1963 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 1964 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 1965 1966let isCodeGenOnly = 1 in { 1967def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), 1968 "creqv $dst, $dst, $dst", IIC_BrCR, 1969 [(set i1:$dst, 1)]>; 1970 1971def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), 1972 "crxor $dst, $dst, $dst", IIC_BrCR, 1973 [(set i1:$dst, 0)]>; 1974 1975let Defs = [CR1EQ], CRD = 6 in { 1976def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 1977 "creqv 6, 6, 6", IIC_BrCR, 1978 [(PPCcr6set)]>; 1979 1980def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 1981 "crxor 6, 6, 6", IIC_BrCR, 1982 [(PPCcr6unset)]>; 1983} 1984} 1985 1986// XFX-Form instructions. Instructions that deal with SPRs. 1987// 1988 1989def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 1990 "mfspr $RT, $SPR", IIC_SprMFSPR>; 1991def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 1992 "mtspr $SPR, $RT", IIC_SprMTSPR>; 1993 1994def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 1995 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>; 1996 1997let Uses = [CTR] in { 1998def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), 1999 "mfctr $rT", IIC_SprMFSPR>, 2000 PPC970_DGroup_First, PPC970_Unit_FXU; 2001} 2002let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { 2003def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2004 "mtctr $rS", IIC_SprMTSPR>, 2005 PPC970_DGroup_First, PPC970_Unit_FXU; 2006} 2007let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { 2008let Pattern = [(int_ppc_mtctr i32:$rS)] in 2009def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2010 "mtctr $rS", IIC_SprMTSPR>, 2011 PPC970_DGroup_First, PPC970_Unit_FXU; 2012} 2013 2014let Defs = [LR] in { 2015def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), 2016 "mtlr $rS", IIC_SprMTSPR>, 2017 PPC970_DGroup_First, PPC970_Unit_FXU; 2018} 2019let Uses = [LR] in { 2020def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), 2021 "mflr $rT", IIC_SprMFSPR>, 2022 PPC970_DGroup_First, PPC970_Unit_FXU; 2023} 2024 2025let isCodeGenOnly = 1 in { 2026 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2027 // like a GPR on the PPC970. As such, copies in and out have the same 2028 // performance characteristics as an OR instruction. 2029 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), 2030 "mtspr 256, $rS", IIC_IntGeneral>, 2031 PPC970_DGroup_Single, PPC970_Unit_FXU; 2032 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), 2033 "mfspr $rT, 256", IIC_IntGeneral>, 2034 PPC970_DGroup_First, PPC970_Unit_FXU; 2035 2036 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, 2037 (outs VRSAVERC:$reg), (ins gprc:$rS), 2038 "mtspr 256, $rS", IIC_IntGeneral>, 2039 PPC970_DGroup_Single, PPC970_Unit_FXU; 2040 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), 2041 (ins VRSAVERC:$reg), 2042 "mfspr $rT, 256", IIC_IntGeneral>, 2043 PPC970_DGroup_First, PPC970_Unit_FXU; 2044} 2045 2046// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register, 2047// so we'll need to scavenge a register for it. 2048let mayStore = 1 in 2049def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F), 2050 "#SPILL_VRSAVE", []>; 2051 2052// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously 2053// spilled), so we'll need to scavenge a register for it. 2054let mayLoad = 1 in 2055def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F), 2056 "#RESTORE_VRSAVE", []>; 2057 2058let neverHasSideEffects = 1 in { 2059def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), 2060 "mtocrf $FXM, $ST", IIC_BrMCRX>, 2061 PPC970_DGroup_First, PPC970_Unit_CRU; 2062 2063def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), 2064 "mtcrf $FXM, $rS", IIC_BrMCRX>, 2065 PPC970_MicroCode, PPC970_Unit_CRU; 2066 2067let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking. 2068def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), 2069 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 2070 PPC970_DGroup_First, PPC970_Unit_CRU; 2071 2072def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), 2073 "mfcr $rT", IIC_SprMFCR>, 2074 PPC970_MicroCode, PPC970_Unit_CRU; 2075} // neverHasSideEffects = 1 2076 2077// Pseudo instruction to perform FADD in round-to-zero mode. 2078let usesCustomInserter = 1, Uses = [RM] in { 2079 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2080 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>; 2081} 2082 2083// The above pseudo gets expanded to make use of the following instructions 2084// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2085let Uses = [RM], Defs = [RM] in { 2086 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2087 "mtfsb0 $FM", IIC_IntMTFSB0, []>, 2088 PPC970_DGroup_Single, PPC970_Unit_FPU; 2089 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2090 "mtfsb1 $FM", IIC_IntMTFSB0, []>, 2091 PPC970_DGroup_Single, PPC970_Unit_FPU; 2092 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), 2093 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>, 2094 PPC970_DGroup_Single, PPC970_Unit_FPU; 2095} 2096let Uses = [RM] in { 2097 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2098 "mffs $rT", IIC_IntMFFS, 2099 [(set f64:$rT, (PPCmffs))]>, 2100 PPC970_DGroup_Single, PPC970_Unit_FPU; 2101} 2102 2103 2104let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations. 2105// XO-Form instructions. Arithmetic instructions that can set overflow bit 2106let isCommutable = 1 in 2107defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2108 "add", "$rT, $rA, $rB", IIC_IntSimple, 2109 [(set i32:$rT, (add i32:$rA, i32:$rB))]>; 2110let isCodeGenOnly = 1 in 2111def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB), 2112 "add $rT, $rA, $rB", IIC_IntSimple, 2113 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>; 2114let isCommutable = 1 in 2115defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2116 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 2117 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, 2118 PPC970_DGroup_Cracked; 2119 2120defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2121 "divw", "$rT, $rA, $rB", IIC_IntDivW, 2122 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>, 2123 PPC970_DGroup_First, PPC970_DGroup_Cracked; 2124defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2125 "divwu", "$rT, $rA, $rB", IIC_IntDivW, 2126 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>, 2127 PPC970_DGroup_First, PPC970_DGroup_Cracked; 2128let isCommutable = 1 in { 2129defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2130 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW, 2131 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; 2132defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2133 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, 2134 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; 2135defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2136 "mullw", "$rT, $rA, $rB", IIC_IntMulHW, 2137 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; 2138} // isCommutable 2139defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2140 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 2141 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; 2142defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2143 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 2144 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, 2145 PPC970_DGroup_Cracked; 2146defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), 2147 "neg", "$rT, $rA", IIC_IntSimple, 2148 [(set i32:$rT, (ineg i32:$rA))]>; 2149let Uses = [CARRY] in { 2150let isCommutable = 1 in 2151defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2152 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 2153 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; 2154defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), 2155 "addme", "$rT, $rA", IIC_IntGeneral, 2156 [(set i32:$rT, (adde i32:$rA, -1))]>; 2157defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), 2158 "addze", "$rT, $rA", IIC_IntGeneral, 2159 [(set i32:$rT, (adde i32:$rA, 0))]>; 2160defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2161 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 2162 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; 2163defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), 2164 "subfme", "$rT, $rA", IIC_IntGeneral, 2165 [(set i32:$rT, (sube -1, i32:$rA))]>; 2166defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), 2167 "subfze", "$rT, $rA", IIC_IntGeneral, 2168 [(set i32:$rT, (sube 0, i32:$rA))]>; 2169} 2170} 2171 2172// A-Form instructions. Most of the instructions executed in the FPU are of 2173// this type. 2174// 2175let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations. 2176let Uses = [RM] in { 2177let isCommutable = 1 in { 2178 defm FMADD : AForm_1r<63, 29, 2179 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2180 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2181 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 2182 defm FMADDS : AForm_1r<59, 29, 2183 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2184 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2185 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 2186 defm FMSUB : AForm_1r<63, 28, 2187 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2188 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2189 [(set f64:$FRT, 2190 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 2191 defm FMSUBS : AForm_1r<59, 28, 2192 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2193 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2194 [(set f32:$FRT, 2195 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 2196 defm FNMADD : AForm_1r<63, 31, 2197 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2198 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2199 [(set f64:$FRT, 2200 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 2201 defm FNMADDS : AForm_1r<59, 31, 2202 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2203 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2204 [(set f32:$FRT, 2205 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 2206 defm FNMSUB : AForm_1r<63, 30, 2207 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2208 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2209 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC, 2210 (fneg f64:$FRB))))]>; 2211 defm FNMSUBS : AForm_1r<59, 30, 2212 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2213 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2214 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC, 2215 (fneg f32:$FRB))))]>; 2216} // isCommutable 2217} 2218// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 2219// having 4 of these, force the comparison to always be an 8-byte double (code 2220// should use an FMRSD if the input comparison value really wants to be a float) 2221// and 4/8 byte forms for the result and operand type.. 2222let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2223defm FSELD : AForm_1r<63, 23, 2224 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2225 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2226 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 2227defm FSELS : AForm_1r<63, 23, 2228 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2229 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2230 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 2231let Uses = [RM] in { 2232 let isCommutable = 1 in { 2233 defm FADD : AForm_2r<63, 21, 2234 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2235 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 2236 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>; 2237 defm FADDS : AForm_2r<59, 21, 2238 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2239 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 2240 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>; 2241 } // isCommutable 2242 defm FDIV : AForm_2r<63, 18, 2243 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2244 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 2245 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>; 2246 defm FDIVS : AForm_2r<59, 18, 2247 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2248 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 2249 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>; 2250 let isCommutable = 1 in { 2251 defm FMUL : AForm_3r<63, 25, 2252 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 2253 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 2254 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>; 2255 defm FMULS : AForm_3r<59, 25, 2256 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 2257 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 2258 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>; 2259 } // isCommutable 2260 defm FSUB : AForm_2r<63, 20, 2261 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2262 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 2263 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>; 2264 defm FSUBS : AForm_2r<59, 20, 2265 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2266 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 2267 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>; 2268 } 2269} 2270 2271let neverHasSideEffects = 1 in { 2272let PPC970_Unit = 1 in { // FXU Operations. 2273 let isSelect = 1 in 2274 def ISEL : AForm_4<31, 15, 2275 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), 2276 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral, 2277 []>; 2278} 2279 2280let PPC970_Unit = 1 in { // FXU Operations. 2281// M-Form instructions. rotate and mask instructions. 2282// 2283let isCommutable = 1 in { 2284// RLWIMI can be commuted if the rotate amount is zero. 2285defm RLWIMI : MForm_2r<20, (outs gprc:$rA), 2286 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, 2287 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 2288 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 2289 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 2290} 2291let BaseName = "rlwinm" in { 2292def RLWINM : MForm_2<21, 2293 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2294 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 2295 []>, RecFormRel; 2296let Defs = [CR0] in 2297def RLWINMo : MForm_2<21, 2298 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2299 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 2300 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked; 2301} 2302defm RLWNM : MForm_2r<23, (outs gprc:$rA), 2303 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), 2304 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 2305 []>; 2306} 2307} // neverHasSideEffects = 1 2308 2309//===----------------------------------------------------------------------===// 2310// PowerPC Instruction Patterns 2311// 2312 2313// Arbitrary immediate support. Implement in terms of LIS/ORI. 2314def : Pat<(i32 imm:$imm), 2315 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 2316 2317// Implement the 'not' operation with the NOR instruction. 2318def i32not : OutPatFrag<(ops node:$in), 2319 (NOR $in, $in)>; 2320def : Pat<(not i32:$in), 2321 (i32not $in)>; 2322 2323// ADD an arbitrary immediate. 2324def : Pat<(add i32:$in, imm:$imm), 2325 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 2326// OR an arbitrary immediate. 2327def : Pat<(or i32:$in, imm:$imm), 2328 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2329// XOR an arbitrary immediate. 2330def : Pat<(xor i32:$in, imm:$imm), 2331 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2332// SUBFIC 2333def : Pat<(sub imm32SExt16:$imm, i32:$in), 2334 (SUBFIC $in, imm:$imm)>; 2335 2336// SHL/SRL 2337def : Pat<(shl i32:$in, (i32 imm:$imm)), 2338 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 2339def : Pat<(srl i32:$in, (i32 imm:$imm)), 2340 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 2341 2342// ROTL 2343def : Pat<(rotl i32:$in, i32:$sh), 2344 (RLWNM $in, $sh, 0, 31)>; 2345def : Pat<(rotl i32:$in, (i32 imm:$imm)), 2346 (RLWINM $in, imm:$imm, 0, 31)>; 2347 2348// RLWNM 2349def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 2350 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 2351 2352// Calls 2353def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 2354 (BL tglobaladdr:$dst)>; 2355def : Pat<(PPCcall (i32 texternalsym:$dst)), 2356 (BL texternalsym:$dst)>; 2357 2358 2359def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 2360 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 2361 2362def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 2363 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 2364 2365def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 2366 (TCRETURNri CTRRC:$dst, imm:$imm)>; 2367 2368 2369 2370// Hi and Lo for Darwin Global Addresses. 2371def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 2372def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 2373def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 2374def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 2375def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 2376def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 2377def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 2378def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 2379def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 2380 (ADDIS $in, tglobaltlsaddr:$g)>; 2381def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 2382 (ADDI $in, tglobaltlsaddr:$g)>; 2383def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 2384 (ADDIS $in, tglobaladdr:$g)>; 2385def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 2386 (ADDIS $in, tconstpool:$g)>; 2387def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 2388 (ADDIS $in, tjumptable:$g)>; 2389def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 2390 (ADDIS $in, tblockaddress:$g)>; 2391 2392// Support for thread-local storage. 2393def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 2394 [(set i32:$rD, (PPCppc32GOT))]>; 2395 2396def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 2397 "#LDgotTprelL32", 2398 [(set i32:$rD, 2399 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 2400def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 2401 (ADD4TLS $in, tglobaltlsaddr:$g)>; 2402 2403// Standard shifts. These are represented separately from the real shifts above 2404// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 2405// amounts. 2406def : Pat<(sra i32:$rS, i32:$rB), 2407 (SRAW $rS, $rB)>; 2408def : Pat<(srl i32:$rS, i32:$rB), 2409 (SRW $rS, $rB)>; 2410def : Pat<(shl i32:$rS, i32:$rB), 2411 (SLW $rS, $rB)>; 2412 2413def : Pat<(zextloadi1 iaddr:$src), 2414 (LBZ iaddr:$src)>; 2415def : Pat<(zextloadi1 xaddr:$src), 2416 (LBZX xaddr:$src)>; 2417def : Pat<(extloadi1 iaddr:$src), 2418 (LBZ iaddr:$src)>; 2419def : Pat<(extloadi1 xaddr:$src), 2420 (LBZX xaddr:$src)>; 2421def : Pat<(extloadi8 iaddr:$src), 2422 (LBZ iaddr:$src)>; 2423def : Pat<(extloadi8 xaddr:$src), 2424 (LBZX xaddr:$src)>; 2425def : Pat<(extloadi16 iaddr:$src), 2426 (LHZ iaddr:$src)>; 2427def : Pat<(extloadi16 xaddr:$src), 2428 (LHZX xaddr:$src)>; 2429def : Pat<(f64 (extloadf32 iaddr:$src)), 2430 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 2431def : Pat<(f64 (extloadf32 xaddr:$src)), 2432 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 2433 2434def : Pat<(f64 (fextend f32:$src)), 2435 (COPY_TO_REGCLASS $src, F8RC)>; 2436 2437def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>; 2438def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>; 2439 2440// Additional FNMSUB patterns: -a*c + b == -(a*c - b) 2441def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B), 2442 (FNMSUB $A, $C, $B)>; 2443def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B), 2444 (FNMSUB $A, $C, $B)>; 2445def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B), 2446 (FNMSUBS $A, $C, $B)>; 2447def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B), 2448 (FNMSUBS $A, $C, $B)>; 2449 2450// FCOPYSIGN's operand types need not agree. 2451def : Pat<(fcopysign f64:$frB, f32:$frA), 2452 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 2453def : Pat<(fcopysign f32:$frB, f64:$frA), 2454 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 2455 2456include "PPCInstrAltivec.td" 2457include "PPCInstr64Bit.td" 2458include "PPCInstrVSX.td" 2459 2460def crnot : OutPatFrag<(ops node:$in), 2461 (CRNOR $in, $in)>; 2462def : Pat<(not i1:$in), 2463 (crnot $in)>; 2464 2465// Patterns for arithmetic i1 operations. 2466def : Pat<(add i1:$a, i1:$b), 2467 (CRXOR $a, $b)>; 2468def : Pat<(sub i1:$a, i1:$b), 2469 (CRXOR $a, $b)>; 2470def : Pat<(mul i1:$a, i1:$b), 2471 (CRAND $a, $b)>; 2472 2473// We're sometimes asked to materialize i1 -1, which is just 1 in this case 2474// (-1 is used to mean all bits set). 2475def : Pat<(i1 -1), (CRSET)>; 2476 2477// i1 extensions, implemented in terms of isel. 2478def : Pat<(i32 (zext i1:$in)), 2479 (SELECT_I4 $in, (LI 1), (LI 0))>; 2480def : Pat<(i32 (sext i1:$in)), 2481 (SELECT_I4 $in, (LI -1), (LI 0))>; 2482 2483def : Pat<(i64 (zext i1:$in)), 2484 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 2485def : Pat<(i64 (sext i1:$in)), 2486 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 2487 2488// FIXME: We should choose either a zext or a sext based on other constants 2489// already around. 2490def : Pat<(i32 (anyext i1:$in)), 2491 (SELECT_I4 $in, (LI 1), (LI 0))>; 2492def : Pat<(i64 (anyext i1:$in)), 2493 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 2494 2495// match setcc on i1 variables. 2496def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 2497 (CRANDC $s2, $s1)>; 2498def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 2499 (CRANDC $s2, $s1)>; 2500def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 2501 (CRORC $s2, $s1)>; 2502def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 2503 (CRORC $s2, $s1)>; 2504def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 2505 (CREQV $s1, $s2)>; 2506def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 2507 (CRORC $s1, $s2)>; 2508def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 2509 (CRORC $s1, $s2)>; 2510def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 2511 (CRANDC $s1, $s2)>; 2512def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 2513 (CRANDC $s1, $s2)>; 2514def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 2515 (CRXOR $s1, $s2)>; 2516 2517// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 2518// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 2519// floating-point types. 2520 2521multiclass CRNotPat<dag pattern, dag result> { 2522 def : Pat<pattern, (crnot result)>; 2523 def : Pat<(not pattern), result>; 2524 2525 // We can also fold the crnot into an extension: 2526 def : Pat<(i32 (zext pattern)), 2527 (SELECT_I4 result, (LI 0), (LI 1))>; 2528 def : Pat<(i32 (sext pattern)), 2529 (SELECT_I4 result, (LI 0), (LI -1))>; 2530 2531 // We can also fold the crnot into an extension: 2532 def : Pat<(i64 (zext pattern)), 2533 (SELECT_I8 result, (LI8 0), (LI8 1))>; 2534 def : Pat<(i64 (sext pattern)), 2535 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 2536 2537 // FIXME: We should choose either a zext or a sext based on other constants 2538 // already around. 2539 def : Pat<(i32 (anyext pattern)), 2540 (SELECT_I4 result, (LI 0), (LI 1))>; 2541 2542 def : Pat<(i64 (anyext pattern)), 2543 (SELECT_I8 result, (LI8 0), (LI8 1))>; 2544} 2545 2546// FIXME: Because of what seems like a bug in TableGen's type-inference code, 2547// we need to write imm:$imm in the output patterns below, not just $imm, or 2548// else the resulting matcher will not correctly add the immediate operand 2549// (making it a register operand instead). 2550 2551// extended SETCC. 2552multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 2553 OutPatFrag rfrag, OutPatFrag rfrag8> { 2554 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 2555 (rfrag $s1)>; 2556 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 2557 (rfrag8 $s1)>; 2558 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 2559 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 2560 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 2561 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 2562 2563 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 2564 (rfrag $s1)>; 2565 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 2566 (rfrag8 $s1)>; 2567 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 2568 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 2569 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 2570 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 2571} 2572 2573// Note that we do all inversions below with i(32|64)not, instead of using 2574// (xori x, 1) because on the A2 nor has single-cycle latency while xori 2575// has 2-cycle latency. 2576 2577defm : ExtSetCCPat<SETEQ, 2578 PatFrag<(ops node:$in, node:$cc), 2579 (setcc $in, 0, $cc)>, 2580 OutPatFrag<(ops node:$in), 2581 (RLWINM (CNTLZW $in), 27, 31, 31)>, 2582 OutPatFrag<(ops node:$in), 2583 (RLDICL (CNTLZD $in), 58, 63)> >; 2584 2585defm : ExtSetCCPat<SETNE, 2586 PatFrag<(ops node:$in, node:$cc), 2587 (setcc $in, 0, $cc)>, 2588 OutPatFrag<(ops node:$in), 2589 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 2590 OutPatFrag<(ops node:$in), 2591 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 2592 2593defm : ExtSetCCPat<SETLT, 2594 PatFrag<(ops node:$in, node:$cc), 2595 (setcc $in, 0, $cc)>, 2596 OutPatFrag<(ops node:$in), 2597 (RLWINM $in, 1, 31, 31)>, 2598 OutPatFrag<(ops node:$in), 2599 (RLDICL $in, 1, 63)> >; 2600 2601defm : ExtSetCCPat<SETGE, 2602 PatFrag<(ops node:$in, node:$cc), 2603 (setcc $in, 0, $cc)>, 2604 OutPatFrag<(ops node:$in), 2605 (RLWINM (i32not $in), 1, 31, 31)>, 2606 OutPatFrag<(ops node:$in), 2607 (RLDICL (i64not $in), 1, 63)> >; 2608 2609defm : ExtSetCCPat<SETGT, 2610 PatFrag<(ops node:$in, node:$cc), 2611 (setcc $in, 0, $cc)>, 2612 OutPatFrag<(ops node:$in), 2613 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 2614 OutPatFrag<(ops node:$in), 2615 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 2616 2617defm : ExtSetCCPat<SETLE, 2618 PatFrag<(ops node:$in, node:$cc), 2619 (setcc $in, 0, $cc)>, 2620 OutPatFrag<(ops node:$in), 2621 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 2622 OutPatFrag<(ops node:$in), 2623 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 2624 2625defm : ExtSetCCPat<SETLT, 2626 PatFrag<(ops node:$in, node:$cc), 2627 (setcc $in, -1, $cc)>, 2628 OutPatFrag<(ops node:$in), 2629 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 2630 OutPatFrag<(ops node:$in), 2631 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 2632 2633defm : ExtSetCCPat<SETGE, 2634 PatFrag<(ops node:$in, node:$cc), 2635 (setcc $in, -1, $cc)>, 2636 OutPatFrag<(ops node:$in), 2637 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 2638 OutPatFrag<(ops node:$in), 2639 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 2640 2641defm : ExtSetCCPat<SETGT, 2642 PatFrag<(ops node:$in, node:$cc), 2643 (setcc $in, -1, $cc)>, 2644 OutPatFrag<(ops node:$in), 2645 (RLWINM (i32not $in), 1, 31, 31)>, 2646 OutPatFrag<(ops node:$in), 2647 (RLDICL (i64not $in), 1, 63)> >; 2648 2649defm : ExtSetCCPat<SETLE, 2650 PatFrag<(ops node:$in, node:$cc), 2651 (setcc $in, -1, $cc)>, 2652 OutPatFrag<(ops node:$in), 2653 (RLWINM $in, 1, 31, 31)>, 2654 OutPatFrag<(ops node:$in), 2655 (RLDICL $in, 1, 63)> >; 2656 2657// SETCC for i32. 2658def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 2659 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 2660def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 2661 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 2662def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 2663 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 2664def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 2665 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 2666def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 2667 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 2668def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 2669 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 2670 2671// For non-equality comparisons, the default code would materialize the 2672// constant, then compare against it, like this: 2673// lis r2, 4660 2674// ori r2, r2, 22136 2675// cmpw cr0, r3, r2 2676// beq cr0,L6 2677// Since we are just comparing for equality, we can emit this instead: 2678// xoris r0,r3,0x1234 2679// cmplwi cr0,r0,0x5678 2680// beq cr0,L6 2681 2682def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 2683 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 2684 (LO16 imm:$imm)), sub_eq)>; 2685 2686defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 2687 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 2688defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 2689 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 2690defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 2691 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 2692defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 2693 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 2694defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 2695 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 2696defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 2697 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 2698 2699defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 2700 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 2701 (LO16 imm:$imm)), sub_eq)>; 2702 2703def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 2704 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 2705def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 2706 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 2707def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 2708 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 2709def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 2710 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 2711def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 2712 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 2713 2714defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 2715 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 2716defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 2717 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 2718defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 2719 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 2720defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 2721 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 2722defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 2723 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 2724 2725// SETCC for i64. 2726def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 2727 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 2728def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 2729 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 2730def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 2731 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 2732def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 2733 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 2734def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 2735 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 2736def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 2737 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 2738 2739// For non-equality comparisons, the default code would materialize the 2740// constant, then compare against it, like this: 2741// lis r2, 4660 2742// ori r2, r2, 22136 2743// cmpd cr0, r3, r2 2744// beq cr0,L6 2745// Since we are just comparing for equality, we can emit this instead: 2746// xoris r0,r3,0x1234 2747// cmpldi cr0,r0,0x5678 2748// beq cr0,L6 2749 2750def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 2751 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 2752 (LO16 imm:$imm)), sub_eq)>; 2753 2754defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 2755 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 2756defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 2757 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 2758defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 2759 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 2760defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 2761 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 2762defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 2763 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 2764defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 2765 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 2766 2767defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 2768 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 2769 (LO16 imm:$imm)), sub_eq)>; 2770 2771def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 2772 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 2773def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 2774 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 2775def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 2776 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 2777def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 2778 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 2779def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 2780 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 2781 2782defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 2783 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 2784defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 2785 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 2786defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 2787 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 2788defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 2789 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 2790defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 2791 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 2792 2793// SETCC for f32. 2794def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)), 2795 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 2796def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)), 2797 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 2798def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)), 2799 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 2800def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)), 2801 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 2802def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)), 2803 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 2804def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)), 2805 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 2806def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)), 2807 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 2808 2809defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)), 2810 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 2811defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)), 2812 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 2813defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)), 2814 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 2815defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)), 2816 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 2817defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)), 2818 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 2819defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)), 2820 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 2821defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)), 2822 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 2823 2824// SETCC for f64. 2825def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)), 2826 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 2827def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)), 2828 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 2829def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)), 2830 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 2831def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)), 2832 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 2833def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)), 2834 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 2835def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)), 2836 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 2837def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)), 2838 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 2839 2840defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)), 2841 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 2842defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)), 2843 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 2844defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)), 2845 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 2846defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)), 2847 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 2848defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)), 2849 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 2850defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)), 2851 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 2852defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)), 2853 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 2854 2855// match select on i1 variables: 2856def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 2857 (CROR (CRAND $cond , $tval), 2858 (CRAND (crnot $cond), $fval))>; 2859 2860// match selectcc on i1 variables: 2861// select (lhs == rhs), tval, fval is: 2862// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 2863def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 2864 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 2865 (CRAND (CRORC $lhs, $rhs), $fval))>; 2866def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 2867 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 2868 (CRAND (CRANDC $lhs, $rhs), $fval))>; 2869def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 2870 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 2871 (CRAND (CRXOR $lhs, $rhs), $fval))>; 2872def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 2873 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 2874 (CRAND (CRANDC $rhs, $lhs), $fval))>; 2875def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 2876 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 2877 (CRAND (CRORC $rhs, $lhs), $fval))>; 2878def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 2879 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 2880 (CRAND (CRXOR $lhs, $rhs), $tval))>; 2881 2882// match selectcc on i1 variables with non-i1 output. 2883def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 2884 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 2885def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 2886 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 2887def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 2888 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 2889def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 2890 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 2891def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 2892 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 2893def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 2894 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 2895 2896def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 2897 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 2898def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 2899 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 2900def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 2901 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 2902def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 2903 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 2904def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 2905 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 2906def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 2907 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 2908 2909def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 2910 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 2911def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 2912 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 2913def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 2914 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 2915def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 2916 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 2917def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 2918 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 2919def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 2920 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 2921 2922def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 2923 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 2924def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 2925 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 2926def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 2927 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 2928def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 2929 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 2930def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 2931 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 2932def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 2933 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 2934 2935def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 2936 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 2937def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 2938 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 2939def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 2940 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 2941def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 2942 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 2943def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 2944 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 2945def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 2946 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 2947 2948let usesCustomInserter = 1 in { 2949def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in), 2950 "#ANDIo_1_EQ_BIT", 2951 [(set i1:$dst, (trunc (not i32:$in)))]>; 2952def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in), 2953 "#ANDIo_1_GT_BIT", 2954 [(set i1:$dst, (trunc i32:$in))]>; 2955 2956def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in), 2957 "#ANDIo_1_EQ_BIT8", 2958 [(set i1:$dst, (trunc (not i64:$in)))]>; 2959def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in), 2960 "#ANDIo_1_GT_BIT8", 2961 [(set i1:$dst, (trunc i64:$in))]>; 2962} 2963 2964def : Pat<(i1 (not (trunc i32:$in))), 2965 (ANDIo_1_EQ_BIT $in)>; 2966def : Pat<(i1 (not (trunc i64:$in))), 2967 (ANDIo_1_EQ_BIT8 $in)>; 2968 2969//===----------------------------------------------------------------------===// 2970// PowerPC Instructions used for assembler/disassembler only 2971// 2972 2973def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 2974 "isync", IIC_SprISYNC, []>; 2975 2976def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), 2977 "icbi $src", IIC_LdStICBI, []>; 2978 2979def EIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2980 "eieio", IIC_LdStLoad, []>; 2981 2982def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L), 2983 "wait $L", IIC_LdStLoad, []>; 2984 2985def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L), 2986 "mtmsr $RS, $L", IIC_SprMTMSR>; 2987 2988def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), 2989 "mfmsr $RT", IIC_SprMFMSR, []>; 2990 2991def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L), 2992 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 2993 2994def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 2995 "slbie $RB", IIC_SprSLBIE, []>; 2996 2997def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), 2998 "slbmte $RS, $RB", IIC_SprSLBMTE, []>; 2999 3000def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), 3001 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; 3002 3003def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 3004 3005def TLBSYNC : XForm_0<31, 566, (outs), (ins), 3006 "tlbsync", IIC_SprTLBSYNC, []>; 3007 3008def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 3009 "tlbiel $RB", IIC_SprTLBIEL, []>; 3010 3011def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), 3012 "tlbie $RB,$RS", IIC_SprTLBIE, []>; 3013 3014//===----------------------------------------------------------------------===// 3015// PowerPC Assembler Instruction Aliases 3016// 3017 3018// Pseudo-instructions for alternate assembly syntax (never used by codegen). 3019// These are aliases that require C++ handling to convert to the target 3020// instruction, while InstAliases can be handled directly by tblgen. 3021class PPCAsmPseudo<string asm, dag iops> 3022 : Instruction { 3023 let Namespace = "PPC"; 3024 bit PPC64 = 0; // Default value, override with isPPC64 3025 3026 let OutOperandList = (outs); 3027 let InOperandList = iops; 3028 let Pattern = []; 3029 let AsmString = asm; 3030 let isAsmParserOnly = 1; 3031 let isPseudo = 1; 3032} 3033 3034def : InstAlias<"sc", (SC 0)>; 3035 3036def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>; 3037def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>; 3038def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>; 3039def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>; 3040 3041def : InstAlias<"wait", (WAIT 0)>; 3042def : InstAlias<"waitrsv", (WAIT 1)>; 3043def : InstAlias<"waitimpl", (WAIT 2)>; 3044 3045def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 3046def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 3047def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 3048def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 3049 3050def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 3051def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 3052 3053def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 3054def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 3055 3056def : InstAlias<"xnop", (XORI R0, R0, 0)>; 3057 3058def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3059def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3060 3061def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3062def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3063 3064def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 3065 3066def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 3067 3068def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 3069 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3070def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 3071 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3072def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 3073 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3074def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm", 3075 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3076 3077def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3078def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3079def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3080def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3081 3082def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 3083def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 3084 3085def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>; 3086def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>; 3087def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>; 3088def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>; 3089 3090def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>; 3091def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>; 3092def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>; 3093def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>; 3094 3095def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>; 3096def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>; 3097def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>; 3098def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>; 3099 3100def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>; 3101def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>; 3102def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>; 3103def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>; 3104 3105def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>; 3106 3107def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>; 3108def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>; 3109 3110def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 3111 3112def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>; 3113def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>; 3114 3115def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>; 3116def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>; 3117def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>; 3118def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>; 3119 3120def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 3121 3122def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 3123 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3124def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 3125 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3126def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 3127 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3128def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 3129 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3130def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 3131 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3132def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 3133 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3134def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 3135 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3136def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 3137 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3138def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 3139 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3140def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 3141 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3142def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 3143 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3144def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n", 3145 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3146def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 3147 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3148def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n", 3149 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3150def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 3151 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3152def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 3153 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3154def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 3155 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 3156def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 3157 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 3158 3159def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 3160def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 3161def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 3162def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 3163def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 3164def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 3165 3166def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 3167 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3168def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 3169 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3170def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 3171 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3172def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 3173 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3174def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 3175 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3176def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 3177 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3178def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 3179 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3180def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 3181 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3182def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 3183 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3184def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n", 3185 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3186def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 3187 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3188def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n", 3189 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3190def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 3191 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3192def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 3193 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3194def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 3195 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 3196def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 3197 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 3198 3199def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 3200def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 3201def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 3202def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 3203def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 3204def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 3205 3206// These generic branch instruction forms are used for the assembler parser only. 3207// Defs and Uses are conservative, since we don't know the BO value. 3208let PPC970_Unit = 7 in { 3209 let Defs = [CTR], Uses = [CTR, RM] in { 3210 def gBC : BForm_3<16, 0, 0, (outs), 3211 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 3212 "bc $bo, $bi, $dst">; 3213 def gBCA : BForm_3<16, 1, 0, (outs), 3214 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 3215 "bca $bo, $bi, $dst">; 3216 } 3217 let Defs = [LR, CTR], Uses = [CTR, RM] in { 3218 def gBCL : BForm_3<16, 0, 1, (outs), 3219 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 3220 "bcl $bo, $bi, $dst">; 3221 def gBCLA : BForm_3<16, 1, 1, (outs), 3222 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 3223 "bcla $bo, $bi, $dst">; 3224 } 3225 let Defs = [CTR], Uses = [CTR, LR, RM] in 3226 def gBCLR : XLForm_2<19, 16, 0, (outs), 3227 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 3228 "bclr $bo, $bi, $bh", IIC_BrB, []>; 3229 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 3230 def gBCLRL : XLForm_2<19, 16, 1, (outs), 3231 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 3232 "bclrl $bo, $bi, $bh", IIC_BrB, []>; 3233 let Defs = [CTR], Uses = [CTR, LR, RM] in 3234 def gBCCTR : XLForm_2<19, 528, 0, (outs), 3235 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 3236 "bcctr $bo, $bi, $bh", IIC_BrB, []>; 3237 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 3238 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 3239 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 3240 "bcctrl $bo, $bi, $bh", IIC_BrB, []>; 3241} 3242def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 3243def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 3244def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 3245def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 3246 3247multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 3248 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 3249 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 3250 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 3251 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 3252 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 3253 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 3254} 3255multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 3256 : BranchSimpleMnemonic1<name, pm, bo> { 3257 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 3258 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 3259} 3260defm : BranchSimpleMnemonic2<"t", "", 12>; 3261defm : BranchSimpleMnemonic2<"f", "", 4>; 3262defm : BranchSimpleMnemonic2<"t", "-", 14>; 3263defm : BranchSimpleMnemonic2<"f", "-", 6>; 3264defm : BranchSimpleMnemonic2<"t", "+", 15>; 3265defm : BranchSimpleMnemonic2<"f", "+", 7>; 3266defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 3267defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 3268defm : BranchSimpleMnemonic1<"dzt", "", 10>; 3269defm : BranchSimpleMnemonic1<"dzf", "", 2>; 3270 3271multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 3272 def : InstAlias<"b"#name#pm#" $cc, $dst", 3273 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 3274 def : InstAlias<"b"#name#pm#" $dst", 3275 (BCC bibo, CR0, condbrtarget:$dst)>; 3276 3277 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 3278 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 3279 def : InstAlias<"b"#name#"a"#pm#" $dst", 3280 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 3281 3282 def : InstAlias<"b"#name#"lr"#pm#" $cc", 3283 (BCCLR bibo, crrc:$cc)>; 3284 def : InstAlias<"b"#name#"lr"#pm, 3285 (BCCLR bibo, CR0)>; 3286 3287 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 3288 (BCCCTR bibo, crrc:$cc)>; 3289 def : InstAlias<"b"#name#"ctr"#pm, 3290 (BCCCTR bibo, CR0)>; 3291 3292 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 3293 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 3294 def : InstAlias<"b"#name#"l"#pm#" $dst", 3295 (BCCL bibo, CR0, condbrtarget:$dst)>; 3296 3297 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 3298 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 3299 def : InstAlias<"b"#name#"la"#pm#" $dst", 3300 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 3301 3302 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 3303 (BCCLRL bibo, crrc:$cc)>; 3304 def : InstAlias<"b"#name#"lrl"#pm, 3305 (BCCLRL bibo, CR0)>; 3306 3307 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 3308 (BCCCTRL bibo, crrc:$cc)>; 3309 def : InstAlias<"b"#name#"ctrl"#pm, 3310 (BCCCTRL bibo, CR0)>; 3311} 3312multiclass BranchExtendedMnemonic<string name, int bibo> { 3313 defm : BranchExtendedMnemonicPM<name, "", bibo>; 3314 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 3315 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 3316} 3317defm : BranchExtendedMnemonic<"lt", 12>; 3318defm : BranchExtendedMnemonic<"gt", 44>; 3319defm : BranchExtendedMnemonic<"eq", 76>; 3320defm : BranchExtendedMnemonic<"un", 108>; 3321defm : BranchExtendedMnemonic<"so", 108>; 3322defm : BranchExtendedMnemonic<"ge", 4>; 3323defm : BranchExtendedMnemonic<"nl", 4>; 3324defm : BranchExtendedMnemonic<"le", 36>; 3325defm : BranchExtendedMnemonic<"ng", 36>; 3326defm : BranchExtendedMnemonic<"ne", 68>; 3327defm : BranchExtendedMnemonic<"nu", 100>; 3328defm : BranchExtendedMnemonic<"ns", 100>; 3329 3330def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 3331def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 3332def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 3333def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 3334def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 3335def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 3336def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 3337def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 3338 3339def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 3340def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 3341def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 3342def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 3343def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 3344def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 3345def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 3346def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 3347 3348multiclass TrapExtendedMnemonic<string name, int to> { 3349 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 3350 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 3351 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 3352 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 3353} 3354defm : TrapExtendedMnemonic<"lt", 16>; 3355defm : TrapExtendedMnemonic<"le", 20>; 3356defm : TrapExtendedMnemonic<"eq", 4>; 3357defm : TrapExtendedMnemonic<"ge", 12>; 3358defm : TrapExtendedMnemonic<"gt", 8>; 3359defm : TrapExtendedMnemonic<"nl", 12>; 3360defm : TrapExtendedMnemonic<"ne", 24>; 3361defm : TrapExtendedMnemonic<"ng", 20>; 3362defm : TrapExtendedMnemonic<"llt", 2>; 3363defm : TrapExtendedMnemonic<"lle", 6>; 3364defm : TrapExtendedMnemonic<"lge", 5>; 3365defm : TrapExtendedMnemonic<"lgt", 1>; 3366defm : TrapExtendedMnemonic<"lnl", 5>; 3367defm : TrapExtendedMnemonic<"lng", 6>; 3368defm : TrapExtendedMnemonic<"u", 31>; 3369 3370