PPCInstrInfo.td revision d5275157b540f53fe3795489229c021390e90b3f
1//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl 24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32> 25]>; 26def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 27 28def SDT_PPCvperm : SDTypeProfile<1, 3, [ 29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 30]>; 31 32def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 34]>; 35 36def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 37 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 38]>; 39 40def SDT_PPClbrx : SDTypeProfile<1, 3, [ 41 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> 42]>; 43def SDT_PPCstbrx : SDTypeProfile<0, 4, [ 44 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> 45]>; 46 47//===----------------------------------------------------------------------===// 48// PowerPC specific DAG Nodes. 49// 50 51def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 52def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 53def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 54def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>; 55 56def PPCfsel : SDNode<"PPCISD::FSEL", 57 // Type constraint for fsel. 58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 59 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 60 61def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 62def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 63def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 64def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 65 66def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 67 68// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 69// amounts. These nodes are generated by the multi-precision shift code. 70def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>; 71def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>; 72def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>; 73 74def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 75def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq, 79 [SDNPHasChain, SDNPOutFlag]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq, 81 [SDNPHasChain, SDNPOutFlag]>; 82 83def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 84def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 85 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 86def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 87 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 88def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet, 89 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 90 91def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet, 92 [SDNPHasChain, SDNPOptInFlag]>; 93 94def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 95def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>; 96 97def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 98 [SDNPHasChain, SDNPOptInFlag]>; 99 100def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>; 101def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>; 102 103// Instructions to support dynamic alloca. 104def SDTDynOp : SDTypeProfile<1, 2, []>; 105def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 106 107//===----------------------------------------------------------------------===// 108// PowerPC specific transformation functions and pattern fragments. 109// 110 111def SHL32 : SDNodeXForm<imm, [{ 112 // Transformation function: 31 - imm 113 return getI32Imm(31 - N->getValue()); 114}]>; 115 116def SRL32 : SDNodeXForm<imm, [{ 117 // Transformation function: 32 - imm 118 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0); 119}]>; 120 121def LO16 : SDNodeXForm<imm, [{ 122 // Transformation function: get the low 16 bits. 123 return getI32Imm((unsigned short)N->getValue()); 124}]>; 125 126def HI16 : SDNodeXForm<imm, [{ 127 // Transformation function: shift the immediate value down into the low bits. 128 return getI32Imm((unsigned)N->getValue() >> 16); 129}]>; 130 131def HA16 : SDNodeXForm<imm, [{ 132 // Transformation function: shift the immediate value down into the low bits. 133 signed int Val = N->getValue(); 134 return getI32Imm((Val - (signed short)Val) >> 16); 135}]>; 136def MB : SDNodeXForm<imm, [{ 137 // Transformation function: get the start bit of a mask 138 unsigned mb, me; 139 (void)isRunOfOnes((unsigned)N->getValue(), mb, me); 140 return getI32Imm(mb); 141}]>; 142 143def ME : SDNodeXForm<imm, [{ 144 // Transformation function: get the end bit of a mask 145 unsigned mb, me; 146 (void)isRunOfOnes((unsigned)N->getValue(), mb, me); 147 return getI32Imm(me); 148}]>; 149def maskimm32 : PatLeaf<(imm), [{ 150 // maskImm predicate - True if immediate is a run of ones. 151 unsigned mb, me; 152 if (N->getValueType(0) == MVT::i32) 153 return isRunOfOnes((unsigned)N->getValue(), mb, me); 154 else 155 return false; 156}]>; 157 158def immSExt16 : PatLeaf<(imm), [{ 159 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 160 // field. Used by instructions like 'addi'. 161 if (N->getValueType(0) == MVT::i32) 162 return (int32_t)N->getValue() == (short)N->getValue(); 163 else 164 return (int64_t)N->getValue() == (short)N->getValue(); 165}]>; 166def immZExt16 : PatLeaf<(imm), [{ 167 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 168 // field. Used by instructions like 'ori'. 169 return (uint64_t)N->getValue() == (unsigned short)N->getValue(); 170}], LO16>; 171 172// imm16Shifted* - These match immediates where the low 16-bits are zero. There 173// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 174// identical in 32-bit mode, but in 64-bit mode, they return true if the 175// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 176// clear). 177def imm16ShiftedZExt : PatLeaf<(imm), [{ 178 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 179 // immediate are set. Used by instructions like 'xoris'. 180 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0; 181}], HI16>; 182 183def imm16ShiftedSExt : PatLeaf<(imm), [{ 184 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 185 // immediate are set. Used by instructions like 'addis'. Identical to 186 // imm16ShiftedZExt in 32-bit mode. 187 if (N->getValue() & 0xFFFF) return false; 188 if (N->getValueType(0) == MVT::i32) 189 return true; 190 // For 64-bit, make sure it is sext right. 191 return N->getValue() == (uint64_t)(int)N->getValue(); 192}], HI16>; 193 194 195//===----------------------------------------------------------------------===// 196// PowerPC Flag Definitions. 197 198class isPPC64 { bit PPC64 = 1; } 199class isDOT { 200 list<Register> Defs = [CR0]; 201 bit RC = 1; 202} 203 204class RegConstraint<string C> { 205 string Constraints = C; 206} 207class NoEncode<string E> { 208 string DisableEncoding = E; 209} 210 211 212//===----------------------------------------------------------------------===// 213// PowerPC Operand Definitions. 214 215def s5imm : Operand<i32> { 216 let PrintMethod = "printS5ImmOperand"; 217} 218def u5imm : Operand<i32> { 219 let PrintMethod = "printU5ImmOperand"; 220} 221def u6imm : Operand<i32> { 222 let PrintMethod = "printU6ImmOperand"; 223} 224def s16imm : Operand<i32> { 225 let PrintMethod = "printS16ImmOperand"; 226} 227def u16imm : Operand<i32> { 228 let PrintMethod = "printU16ImmOperand"; 229} 230def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 231 let PrintMethod = "printS16X4ImmOperand"; 232} 233def target : Operand<OtherVT> { 234 let PrintMethod = "printBranchOperand"; 235} 236def calltarget : Operand<iPTR> { 237 let PrintMethod = "printCallOperand"; 238} 239def aaddr : Operand<iPTR> { 240 let PrintMethod = "printAbsAddrOperand"; 241} 242def piclabel: Operand<iPTR> { 243 let PrintMethod = "printPICLabel"; 244} 245def symbolHi: Operand<i32> { 246 let PrintMethod = "printSymbolHi"; 247} 248def symbolLo: Operand<i32> { 249 let PrintMethod = "printSymbolLo"; 250} 251def crbitm: Operand<i8> { 252 let PrintMethod = "printcrbitm"; 253} 254// Address operands 255def memri : Operand<iPTR> { 256 let PrintMethod = "printMemRegImm"; 257 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 258} 259def memrr : Operand<iPTR> { 260 let PrintMethod = "printMemRegReg"; 261 let MIOperandInfo = (ops ptr_rc, ptr_rc); 262} 263def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 264 let PrintMethod = "printMemRegImmShifted"; 265 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 266} 267 268// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg 269// that doesn't matter. 270def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 20), CR0)> { 271 let PrintMethod = "printPredicateOperand"; 272} 273 274// Define PowerPC specific addressing mode. 275def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 276def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 277def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 278def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 279 280/// This is just the offset part of iaddr, used for preinc. 281def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 282 283//===----------------------------------------------------------------------===// 284// PowerPC Instruction Predicate Definitions. 285def FPContractions : Predicate<"!NoExcessFPPrecision">; 286 287 288//===----------------------------------------------------------------------===// 289// PowerPC Instruction Definitions. 290 291// Pseudo-instructions: 292 293let hasCtrlDep = 1 in { 294def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), 295 "${:comment} ADJCALLSTACKDOWN", 296 [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>; 297def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), 298 "${:comment} ADJCALLSTACKUP", 299 [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>; 300 301def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS), 302 "UPDATE_VRSAVE $rD, $rS", []>; 303} 304 305def DYNALLOC : Pseudo<(ops GPRC:$result, GPRC:$negsize, memri:$fpsi), 306 "${:comment} DYNALLOC $result, $negsize, $fpsi", 307 [(set GPRC:$result, 308 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>, 309 Imp<[R1],[R1]>; 310 311def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD),"${:comment}IMPLICIT_DEF_GPRC $rD", 312 [(set GPRC:$rD, (undef))]>; 313def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "${:comment} IMPLICIT_DEF_F8 $rD", 314 [(set F8RC:$rD, (undef))]>; 315def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "${:comment} IMPLICIT_DEF_F4 $rD", 316 [(set F4RC:$rD, (undef))]>; 317 318// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 319// scheduler into a branch sequence. 320let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler. 321 PPC970_Single = 1 in { 322 def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F, 323 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 324 []>; 325 def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F, 326 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 327 []>; 328 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F, 329 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 330 []>; 331 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F, 332 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 333 []>; 334 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F, 335 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 336 []>; 337} 338 339let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in { 340 let isReturn = 1 in 341 def BLR : XLForm_2_br<19, 16, 0, (ops pred:$p), 342 "b${p:cc}lr ${p:reg}", BrB, 343 [(retflag)]>; 344 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>; 345} 346 347 348 349let Defs = [LR] in 350 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>, 351 PPC970_Unit_BRU; 352 353let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, 354 noResults = 1, PPC970_Unit = 7 in { 355 let isBarrier = 1 in { 356 def B : IForm<18, 0, 0, (ops target:$dst), 357 "b $dst", BrB, 358 [(br bb:$dst)]>; 359 } 360 361 // BCC represents an arbitrary conditional branch on a predicate. 362 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 363 // a two-value operand where a dag node expects two operands. :( 364 def BCC : CBForm<16, 0, 0, (ops pred:$cond, target:$dst), 365 "b${cond:cc} ${cond:reg}, $dst" 366 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; 367 368// REMOVE BForm when these go away. 369 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block), 370 "blt $crS, $block", BrB>; 371 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block), 372 "ble $crS, $block", BrB>; 373 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block), 374 "beq $crS, $block", BrB>; 375 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block), 376 "bge $crS, $block", BrB>; 377 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block), 378 "bgt $crS, $block", BrB>; 379 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block), 380 "bne $crS, $block", BrB>; 381 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block), 382 "bun $crS, $block", BrB>; 383 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block), 384 "bnu $crS, $block", BrB>; 385} 386 387let isCall = 1, noResults = 1, PPC970_Unit = 7, 388 // All calls clobber the non-callee saved registers... 389 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 390 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 391 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 392 LR,CTR, 393 CR0,CR1,CR5,CR6,CR7] in { 394 // Convenient aliases for call instructions 395 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops), 396 "bl $func", BrB, []>; // See Pat patterns below. 397 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), 398 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>; 399 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB, 400 [(PPCbctrl)]>; 401} 402 403// DCB* instructions. 404def DCBA : DCB_Form<758, 0, (ops memrr:$dst), 405 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 406 PPC970_DGroup_Single; 407def DCBF : DCB_Form<86, 0, (ops memrr:$dst), 408 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 409 PPC970_DGroup_Single; 410def DCBI : DCB_Form<470, 0, (ops memrr:$dst), 411 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 412 PPC970_DGroup_Single; 413def DCBST : DCB_Form<54, 0, (ops memrr:$dst), 414 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 415 PPC970_DGroup_Single; 416def DCBT : DCB_Form<278, 0, (ops memrr:$dst), 417 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 418 PPC970_DGroup_Single; 419def DCBTST : DCB_Form<246, 0, (ops memrr:$dst), 420 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 421 PPC970_DGroup_Single; 422def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst), 423 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 424 PPC970_DGroup_Single; 425def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst), 426 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 427 PPC970_DGroup_Single; 428 429//===----------------------------------------------------------------------===// 430// PPC32 Load Instructions. 431// 432 433// Unindexed (r+i) Loads. 434let isLoad = 1, PPC970_Unit = 2 in { 435def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src), 436 "lbz $rD, $src", LdStGeneral, 437 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 438def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src), 439 "lha $rD, $src", LdStLHA, 440 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, 441 PPC970_DGroup_Cracked; 442def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src), 443 "lhz $rD, $src", LdStGeneral, 444 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; 445def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src), 446 "lwz $rD, $src", LdStGeneral, 447 [(set GPRC:$rD, (load iaddr:$src))]>; 448 449def LFS : DForm_1<48, (ops F4RC:$rD, memri:$src), 450 "lfs $rD, $src", LdStLFDU, 451 [(set F4RC:$rD, (load iaddr:$src))]>; 452def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src), 453 "lfd $rD, $src", LdStLFD, 454 [(set F8RC:$rD, (load iaddr:$src))]>; 455 456 457// Unindexed (r+i) Loads with Update (preinc). 458def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), 459 "lbzu $rD, $addr", LdStGeneral, 460 []>, RegConstraint<"$addr.reg = $ea_result">, 461 NoEncode<"$ea_result">; 462 463def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), 464 "lhau $rD, $addr", LdStGeneral, 465 []>, RegConstraint<"$addr.reg = $ea_result">, 466 NoEncode<"$ea_result">; 467 468def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), 469 "lhzu $rD, $addr", LdStGeneral, 470 []>, RegConstraint<"$addr.reg = $ea_result">, 471 NoEncode<"$ea_result">; 472 473def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), 474 "lwzu $rD, $addr", LdStGeneral, 475 []>, RegConstraint<"$addr.reg = $ea_result">, 476 NoEncode<"$ea_result">; 477 478def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$ea_result, memri:$addr), 479 "lfs $rD, $addr", LdStLFDU, 480 []>, RegConstraint<"$addr.reg = $ea_result">, 481 NoEncode<"$ea_result">; 482 483def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$ea_result, memri:$addr), 484 "lfd $rD, $addr", LdStLFD, 485 []>, RegConstraint<"$addr.reg = $ea_result">, 486 NoEncode<"$ea_result">; 487} 488 489// Indexed (r+r) Loads. 490// 491let isLoad = 1, PPC970_Unit = 2 in { 492def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src), 493 "lbzx $rD, $src", LdStGeneral, 494 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; 495def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src), 496 "lhax $rD, $src", LdStLHA, 497 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, 498 PPC970_DGroup_Cracked; 499def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src), 500 "lhzx $rD, $src", LdStGeneral, 501 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; 502def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src), 503 "lwzx $rD, $src", LdStGeneral, 504 [(set GPRC:$rD, (load xaddr:$src))]>; 505 506 507def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src), 508 "lhbrx $rD, $src", LdStGeneral, 509 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>; 510def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src), 511 "lwbrx $rD, $src", LdStGeneral, 512 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>; 513 514def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src), 515 "lfsx $frD, $src", LdStLFDU, 516 [(set F4RC:$frD, (load xaddr:$src))]>; 517def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src), 518 "lfdx $frD, $src", LdStLFDU, 519 [(set F8RC:$frD, (load xaddr:$src))]>; 520} 521 522//===----------------------------------------------------------------------===// 523// PPC32 Store Instructions. 524// 525 526// Unindexed (r+i) Stores. 527let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 528def STB : DForm_1<38, (ops GPRC:$rS, memri:$src), 529 "stb $rS, $src", LdStGeneral, 530 [(truncstorei8 GPRC:$rS, iaddr:$src)]>; 531def STH : DForm_1<44, (ops GPRC:$rS, memri:$src), 532 "sth $rS, $src", LdStGeneral, 533 [(truncstorei16 GPRC:$rS, iaddr:$src)]>; 534def STW : DForm_1<36, (ops GPRC:$rS, memri:$src), 535 "stw $rS, $src", LdStGeneral, 536 [(store GPRC:$rS, iaddr:$src)]>; 537def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst), 538 "stfs $rS, $dst", LdStUX, 539 [(store F4RC:$rS, iaddr:$dst)]>; 540def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst), 541 "stfd $rS, $dst", LdStUX, 542 [(store F8RC:$rS, iaddr:$dst)]>; 543} 544 545// Unindexed (r+i) Stores with Update (preinc). 546let isStore = 1, PPC970_Unit = 2 in { 547def STBU : DForm_1<39, (ops ptr_rc:$ea_res, GPRC:$rS, 548 symbolLo:$ptroff, ptr_rc:$ptrreg), 549 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 550 [(set ptr_rc:$ea_res, 551 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, 552 iaddroff:$ptroff))]>, 553 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 554def STHU : DForm_1<45, (ops ptr_rc:$ea_res, GPRC:$rS, 555 symbolLo:$ptroff, ptr_rc:$ptrreg), 556 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 557 [(set ptr_rc:$ea_res, 558 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, 559 iaddroff:$ptroff))]>, 560 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 561def STWU : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS, 562 symbolLo:$ptroff, ptr_rc:$ptrreg), 563 "stwu $rS, $ptroff($ptrreg)", LdStGeneral, 564 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg, 565 iaddroff:$ptroff))]>, 566 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 567def STFSU : DForm_1<37, (ops ptr_rc:$ea_res, F4RC:$rS, 568 symbolLo:$ptroff, ptr_rc:$ptrreg), 569 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral, 570 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg, 571 iaddroff:$ptroff))]>, 572 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 573def STFDU : DForm_1<37, (ops ptr_rc:$ea_res, F8RC:$rS, 574 symbolLo:$ptroff, ptr_rc:$ptrreg), 575 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral, 576 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg, 577 iaddroff:$ptroff))]>, 578 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 579} 580 581 582// Indexed (r+r) Stores. 583// 584let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 585def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst), 586 "stbx $rS, $dst", LdStGeneral, 587 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, 588 PPC970_DGroup_Cracked; 589def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst), 590 "sthx $rS, $dst", LdStGeneral, 591 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, 592 PPC970_DGroup_Cracked; 593def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst), 594 "stwx $rS, $dst", LdStGeneral, 595 [(store GPRC:$rS, xaddr:$dst)]>, 596 PPC970_DGroup_Cracked; 597def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 598 "stwux $rS, $rA, $rB", LdStGeneral, 599 []>; 600def STHBRX: XForm_8<31, 918, (ops GPRC:$rS, memrr:$dst), 601 "sthbrx $rS, $dst", LdStGeneral, 602 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>, 603 PPC970_DGroup_Cracked; 604def STWBRX: XForm_8<31, 662, (ops GPRC:$rS, memrr:$dst), 605 "stwbrx $rS, $dst", LdStGeneral, 606 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>, 607 PPC970_DGroup_Cracked; 608 609def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst), 610 "stfiwx $frS, $dst", LdStUX, 611 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 612def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst), 613 "stfsx $frS, $dst", LdStUX, 614 [(store F4RC:$frS, xaddr:$dst)]>; 615def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst), 616 "stfdx $frS, $dst", LdStUX, 617 [(store F8RC:$frS, xaddr:$dst)]>; 618} 619 620 621//===----------------------------------------------------------------------===// 622// PPC32 Arithmetic Instructions. 623// 624 625let PPC970_Unit = 1 in { // FXU Operations. 626def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 627 "addi $rD, $rA, $imm", IntGeneral, 628 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 629def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 630 "addic $rD, $rA, $imm", IntGeneral, 631 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 632 PPC970_DGroup_Cracked; 633def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 634 "addic. $rD, $rA, $imm", IntGeneral, 635 []>; 636def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm), 637 "addis $rD, $rA, $imm", IntGeneral, 638 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; 639def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym), 640 "la $rD, $sym($rA)", IntGeneral, 641 [(set GPRC:$rD, (add GPRC:$rA, 642 (PPClo tglobaladdr:$sym, 0)))]>; 643def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 644 "mulli $rD, $rA, $imm", IntMulLI, 645 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 646def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 647 "subfic $rD, $rA, $imm", IntGeneral, 648 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 649def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm), 650 "li $rD, $imm", IntGeneral, 651 [(set GPRC:$rD, immSExt16:$imm)]>; 652def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm), 653 "lis $rD, $imm", IntGeneral, 654 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; 655} 656 657let PPC970_Unit = 1 in { // FXU Operations. 658def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 659 "andi. $dst, $src1, $src2", IntGeneral, 660 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 661 isDOT; 662def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 663 "andis. $dst, $src1, $src2", IntGeneral, 664 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, 665 isDOT; 666def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 667 "ori $dst, $src1, $src2", IntGeneral, 668 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 669def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 670 "oris $dst, $src1, $src2", IntGeneral, 671 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; 672def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 673 "xori $dst, $src1, $src2", IntGeneral, 674 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 675def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 676 "xoris $dst, $src1, $src2", IntGeneral, 677 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; 678def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral, 679 []>; 680def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 681 "cmpwi $crD, $rA, $imm", IntCompare>; 682def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 683 "cmplwi $dst, $src1, $src2", IntCompare>; 684} 685 686 687let PPC970_Unit = 1 in { // FXU Operations. 688def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 689 "nand $rA, $rS, $rB", IntGeneral, 690 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 691def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 692 "and $rA, $rS, $rB", IntGeneral, 693 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 694def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 695 "andc $rA, $rS, $rB", IntGeneral, 696 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 697def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 698 "or $rA, $rS, $rB", IntGeneral, 699 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 700def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 701 "nor $rA, $rS, $rB", IntGeneral, 702 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 703def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 704 "orc $rA, $rS, $rB", IntGeneral, 705 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 706def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 707 "eqv $rA, $rS, $rB", IntGeneral, 708 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 709def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 710 "xor $rA, $rS, $rB", IntGeneral, 711 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 712def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 713 "slw $rA, $rS, $rB", IntGeneral, 714 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 715def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 716 "srw $rA, $rS, $rB", IntGeneral, 717 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 718def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 719 "sraw $rA, $rS, $rB", IntShift, 720 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 721} 722 723let PPC970_Unit = 1 in { // FXU Operations. 724def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), 725 "srawi $rA, $rS, $SH", IntShift, 726 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 727def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS), 728 "cntlzw $rA, $rS", IntGeneral, 729 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 730def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS), 731 "extsb $rA, $rS", IntGeneral, 732 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 733def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS), 734 "extsh $rA, $rS", IntGeneral, 735 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 736 737def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 738 "cmpw $crD, $rA, $rB", IntCompare>; 739def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 740 "cmplw $crD, $rA, $rB", IntCompare>; 741} 742let PPC970_Unit = 3 in { // FPU Operations. 743//def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB), 744// "fcmpo $crD, $fA, $fB", FPCompare>; 745def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB), 746 "fcmpu $crD, $fA, $fB", FPCompare>; 747def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB), 748 "fcmpu $crD, $fA, $fB", FPCompare>; 749 750def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB), 751 "fctiwz $frD, $frB", FPGeneral, 752 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 753def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB), 754 "frsp $frD, $frB", FPGeneral, 755 [(set F4RC:$frD, (fround F8RC:$frB))]>; 756def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB), 757 "fsqrt $frD, $frB", FPSqrt, 758 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 759def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB), 760 "fsqrts $frD, $frB", FPSqrt, 761 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 762} 763 764/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending. 765/// 766/// Note that these are defined as pseudo-ops on the PPC970 because they are 767/// often coalesced away and we don't want the dispatch group builder to think 768/// that they will fill slots (which could cause the load of a LSU reject to 769/// sneak into a d-group with a store). 770def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB), 771 "fmr $frD, $frB", FPGeneral, 772 []>, // (set F4RC:$frD, F4RC:$frB) 773 PPC970_Unit_Pseudo; 774def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB), 775 "fmr $frD, $frB", FPGeneral, 776 []>, // (set F8RC:$frD, F8RC:$frB) 777 PPC970_Unit_Pseudo; 778def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB), 779 "fmr $frD, $frB", FPGeneral, 780 [(set F8RC:$frD, (fextend F4RC:$frB))]>, 781 PPC970_Unit_Pseudo; 782 783let PPC970_Unit = 3 in { // FPU Operations. 784// These are artificially split into two different forms, for 4/8 byte FP. 785def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB), 786 "fabs $frD, $frB", FPGeneral, 787 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 788def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB), 789 "fabs $frD, $frB", FPGeneral, 790 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 791def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB), 792 "fnabs $frD, $frB", FPGeneral, 793 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 794def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB), 795 "fnabs $frD, $frB", FPGeneral, 796 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 797def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB), 798 "fneg $frD, $frB", FPGeneral, 799 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 800def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB), 801 "fneg $frD, $frB", FPGeneral, 802 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 803} 804 805 806// XL-Form instructions. condition register logical ops. 807// 808def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA), 809 "mcrf $BF, $BFA", BrMCR>, 810 PPC970_DGroup_First, PPC970_Unit_CRU; 811 812// XFX-Form instructions. Instructions that deal with SPRs. 813// 814def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>, 815 PPC970_DGroup_First, PPC970_Unit_FXU; 816let Pattern = [(PPCmtctr GPRC:$rS)] in { 817def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>, 818 PPC970_DGroup_First, PPC970_Unit_FXU; 819} 820 821def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>, 822 PPC970_DGroup_First, PPC970_Unit_FXU; 823def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>, 824 PPC970_DGroup_First, PPC970_Unit_FXU; 825 826// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 827// a GPR on the PPC970. As such, copies in and out have the same performance 828// characteristics as an OR instruction. 829def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), 830 "mtspr 256, $rS", IntGeneral>, 831 PPC970_DGroup_Single, PPC970_Unit_FXU; 832def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), 833 "mfspr $rT, 256", IntGeneral>, 834 PPC970_DGroup_First, PPC970_Unit_FXU; 835 836def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS), 837 "mtcrf $FXM, $rS", BrMCRX>, 838 PPC970_MicroCode, PPC970_Unit_CRU; 839def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>, 840 PPC970_MicroCode, PPC970_Unit_CRU; 841def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM), 842 "mfcr $rT, $FXM", SprMFCR>, 843 PPC970_DGroup_First, PPC970_Unit_CRU; 844 845let PPC970_Unit = 1 in { // FXU Operations. 846 847// XO-Form instructions. Arithmetic instructions that can set overflow bit 848// 849def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 850 "add $rT, $rA, $rB", IntGeneral, 851 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 852def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 853 "addc $rT, $rA, $rB", IntGeneral, 854 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 855 PPC970_DGroup_Cracked; 856def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 857 "adde $rT, $rA, $rB", IntGeneral, 858 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 859def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 860 "divw $rT, $rA, $rB", IntDivW, 861 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 862 PPC970_DGroup_First, PPC970_DGroup_Cracked; 863def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 864 "divwu $rT, $rA, $rB", IntDivW, 865 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 866 PPC970_DGroup_First, PPC970_DGroup_Cracked; 867def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 868 "mulhw $rT, $rA, $rB", IntMulHW, 869 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 870def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 871 "mulhwu $rT, $rA, $rB", IntMulHWU, 872 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 873def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 874 "mullw $rT, $rA, $rB", IntMulHW, 875 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 876def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 877 "subf $rT, $rA, $rB", IntGeneral, 878 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 879def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 880 "subfc $rT, $rA, $rB", IntGeneral, 881 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 882 PPC970_DGroup_Cracked; 883def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 884 "subfe $rT, $rA, $rB", IntGeneral, 885 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 886def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA), 887 "addme $rT, $rA", IntGeneral, 888 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>; 889def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA), 890 "addze $rT, $rA", IntGeneral, 891 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 892def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA), 893 "neg $rT, $rA", IntGeneral, 894 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 895def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA), 896 "subfme $rT, $rA", IntGeneral, 897 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>; 898def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA), 899 "subfze $rT, $rA", IntGeneral, 900 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 901} 902 903// A-Form instructions. Most of the instructions executed in the FPU are of 904// this type. 905// 906let PPC970_Unit = 3 in { // FPU Operations. 907def FMADD : AForm_1<63, 29, 908 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 909 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 910 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), 911 F8RC:$FRB))]>, 912 Requires<[FPContractions]>; 913def FMADDS : AForm_1<59, 29, 914 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 915 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 916 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), 917 F4RC:$FRB))]>, 918 Requires<[FPContractions]>; 919def FMSUB : AForm_1<63, 28, 920 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 921 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 922 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), 923 F8RC:$FRB))]>, 924 Requires<[FPContractions]>; 925def FMSUBS : AForm_1<59, 28, 926 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 927 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 928 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), 929 F4RC:$FRB))]>, 930 Requires<[FPContractions]>; 931def FNMADD : AForm_1<63, 31, 932 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 933 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 934 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), 935 F8RC:$FRB)))]>, 936 Requires<[FPContractions]>; 937def FNMADDS : AForm_1<59, 31, 938 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 939 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 940 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), 941 F4RC:$FRB)))]>, 942 Requires<[FPContractions]>; 943def FNMSUB : AForm_1<63, 30, 944 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 945 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 946 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), 947 F8RC:$FRB)))]>, 948 Requires<[FPContractions]>; 949def FNMSUBS : AForm_1<59, 30, 950 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 951 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 952 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), 953 F4RC:$FRB)))]>, 954 Requires<[FPContractions]>; 955// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 956// having 4 of these, force the comparison to always be an 8-byte double (code 957// should use an FMRSD if the input comparison value really wants to be a float) 958// and 4/8 byte forms for the result and operand type.. 959def FSELD : AForm_1<63, 23, 960 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 961 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 962 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 963def FSELS : AForm_1<63, 23, 964 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 965 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 966 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 967def FADD : AForm_2<63, 21, 968 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 969 "fadd $FRT, $FRA, $FRB", FPGeneral, 970 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 971def FADDS : AForm_2<59, 21, 972 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 973 "fadds $FRT, $FRA, $FRB", FPGeneral, 974 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 975def FDIV : AForm_2<63, 18, 976 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 977 "fdiv $FRT, $FRA, $FRB", FPDivD, 978 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 979def FDIVS : AForm_2<59, 18, 980 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 981 "fdivs $FRT, $FRA, $FRB", FPDivS, 982 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 983def FMUL : AForm_3<63, 25, 984 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 985 "fmul $FRT, $FRA, $FRB", FPFused, 986 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 987def FMULS : AForm_3<59, 25, 988 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 989 "fmuls $FRT, $FRA, $FRB", FPGeneral, 990 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 991def FSUB : AForm_2<63, 20, 992 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 993 "fsub $FRT, $FRA, $FRB", FPGeneral, 994 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 995def FSUBS : AForm_2<59, 20, 996 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 997 "fsubs $FRT, $FRA, $FRB", FPGeneral, 998 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 999} 1000 1001let PPC970_Unit = 1 in { // FXU Operations. 1002// M-Form instructions. rotate and mask instructions. 1003// 1004let isCommutable = 1 in { 1005// RLWIMI can be commuted if the rotate amount is zero. 1006def RLWIMI : MForm_2<20, 1007 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 1008 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 1009 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 1010 NoEncode<"$rSi">; 1011} 1012def RLWINM : MForm_2<21, 1013 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1014 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 1015 []>; 1016def RLWINMo : MForm_2<21, 1017 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1018 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 1019 []>, isDOT, PPC970_DGroup_Cracked; 1020def RLWNM : MForm_2<23, 1021 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 1022 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 1023 []>; 1024} 1025 1026 1027//===----------------------------------------------------------------------===// 1028// DWARF Pseudo Instructions 1029// 1030 1031def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file), 1032 "${:comment} .loc $file, $line, $col", 1033 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), 1034 (i32 imm:$file))]>; 1035 1036def DWARF_LABEL : Pseudo<(ops i32imm:$id), 1037 "\n${:private}debug_loc$id:", 1038 [(dwarf_label (i32 imm:$id))]>; 1039 1040//===----------------------------------------------------------------------===// 1041// PowerPC Instruction Patterns 1042// 1043 1044// Arbitrary immediate support. Implement in terms of LIS/ORI. 1045def : Pat<(i32 imm:$imm), 1046 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1047 1048// Implement the 'not' operation with the NOR instruction. 1049def NOT : Pat<(not GPRC:$in), 1050 (NOR GPRC:$in, GPRC:$in)>; 1051 1052// ADD an arbitrary immediate. 1053def : Pat<(add GPRC:$in, imm:$imm), 1054 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1055// OR an arbitrary immediate. 1056def : Pat<(or GPRC:$in, imm:$imm), 1057 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1058// XOR an arbitrary immediate. 1059def : Pat<(xor GPRC:$in, imm:$imm), 1060 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1061// SUBFIC 1062def : Pat<(sub immSExt16:$imm, GPRC:$in), 1063 (SUBFIC GPRC:$in, imm:$imm)>; 1064 1065// Return void support. 1066def : Pat<(ret), (BLR)>; 1067 1068// SHL/SRL 1069def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1070 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1071def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1072 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1073 1074// ROTL 1075def : Pat<(rotl GPRC:$in, GPRC:$sh), 1076 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1077def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1078 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1079 1080// RLWNM 1081def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm), 1082 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 1083 1084// Calls 1085def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 1086 (BL tglobaladdr:$dst)>; 1087def : Pat<(PPCcall (i32 texternalsym:$dst)), 1088 (BL texternalsym:$dst)>; 1089 1090// Hi and Lo for Darwin Global Addresses. 1091def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1092def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1093def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1094def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1095def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1096def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1097def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1098 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1099def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1100 (ADDIS GPRC:$in, tconstpool:$g)>; 1101def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 1102 (ADDIS GPRC:$in, tjumptable:$g)>; 1103 1104// Fused negative multiply subtract, alternate pattern 1105def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), 1106 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>, 1107 Requires<[FPContractions]>; 1108def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)), 1109 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>, 1110 Requires<[FPContractions]>; 1111 1112// Standard shifts. These are represented separately from the real shifts above 1113// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1114// amounts. 1115def : Pat<(sra GPRC:$rS, GPRC:$rB), 1116 (SRAW GPRC:$rS, GPRC:$rB)>; 1117def : Pat<(srl GPRC:$rS, GPRC:$rB), 1118 (SRW GPRC:$rS, GPRC:$rB)>; 1119def : Pat<(shl GPRC:$rS, GPRC:$rB), 1120 (SLW GPRC:$rS, GPRC:$rB)>; 1121 1122def : Pat<(zextloadi1 iaddr:$src), 1123 (LBZ iaddr:$src)>; 1124def : Pat<(zextloadi1 xaddr:$src), 1125 (LBZX xaddr:$src)>; 1126def : Pat<(extloadi1 iaddr:$src), 1127 (LBZ iaddr:$src)>; 1128def : Pat<(extloadi1 xaddr:$src), 1129 (LBZX xaddr:$src)>; 1130def : Pat<(extloadi8 iaddr:$src), 1131 (LBZ iaddr:$src)>; 1132def : Pat<(extloadi8 xaddr:$src), 1133 (LBZX xaddr:$src)>; 1134def : Pat<(extloadi16 iaddr:$src), 1135 (LHZ iaddr:$src)>; 1136def : Pat<(extloadi16 xaddr:$src), 1137 (LHZX xaddr:$src)>; 1138def : Pat<(extloadf32 iaddr:$src), 1139 (FMRSD (LFS iaddr:$src))>; 1140def : Pat<(extloadf32 xaddr:$src), 1141 (FMRSD (LFSX xaddr:$src))>; 1142 1143include "PPCInstrAltivec.td" 1144include "PPCInstr64Bit.td" 1145