PPCInstrInfo.td revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 24 SDTCisVT<0, f64>, SDTCisPtrTy<1> 25]>; 26 27def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 28def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 29 SDTCisVT<1, i32> ]>; 30def SDT_PPCvperm : SDTypeProfile<1, 3, [ 31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 32]>; 33 34def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 36]>; 37 38def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 40]>; 41 42def SDT_PPClbrx : SDTypeProfile<1, 2, [ 43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 44]>; 45def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 47]>; 48 49def SDT_PPClarx : SDTypeProfile<1, 1, [ 50 SDTCisInt<0>, SDTCisPtrTy<1> 51]>; 52def SDT_PPCstcx : SDTypeProfile<0, 2, [ 53 SDTCisInt<0>, SDTCisPtrTy<1> 54]>; 55 56def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 57 SDTCisPtrTy<0>, SDTCisVT<1, i32> 58]>; 59 60 61//===----------------------------------------------------------------------===// 62// PowerPC specific DAG Nodes. 63// 64 65def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 66def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 67 68def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 69def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 70def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 71def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 72def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 73def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 74def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 75def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 76def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 77 [SDNPHasChain, SDNPMayStore]>; 78def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 79 [SDNPHasChain, SDNPMayLoad]>; 80def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 81 [SDNPHasChain, SDNPMayLoad]>; 82 83// Extract FPSCR (not modeled at the DAG level). 84def PPCmffs : SDNode<"PPCISD::MFFS", 85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>; 86 87// Perform FADD in round-to-zero mode. 88def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 89 90 91def PPCfsel : SDNode<"PPCISD::FSEL", 92 // Type constraint for fsel. 93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 95 96def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 97def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 98def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>; 99def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 100def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 101 102def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 103 104def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 105def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 106 [SDNPMayLoad]>; 107def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 108def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 109def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 110def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 111def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 112def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 113def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 114def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp, 115 [SDNPHasChain]>; 116def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 117 118def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 119 120// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 121// amounts. These nodes are generated by the multi-precision shift code. 122def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 123def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 124def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 125 126// These are target-independent nodes, but have target-specific formats. 127def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 128 [SDNPHasChain, SDNPOutGlue]>; 129def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 131 132def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 133def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 135 SDNPVariadic]>; 136def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 138 SDNPVariadic]>; 139def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>, 140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 141def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>, 142 [SDNPHasChain, SDNPSideEffect, 143 SDNPInGlue, SDNPOutGlue]>; 144def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>, 145 [SDNPHasChain, SDNPSideEffect, 146 SDNPInGlue, SDNPOutGlue]>; 147def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 149def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 151 SDNPVariadic]>; 152 153def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 154 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 155 156def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 157 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 158 159def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 160 SDTypeProfile<1, 1, [SDTCisInt<0>, 161 SDTCisPtrTy<1>]>, 162 [SDNPHasChain, SDNPSideEffect]>; 163def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 164 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 165 [SDNPHasChain, SDNPSideEffect]>; 166 167def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 168def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 169 [SDNPHasChain, SDNPSideEffect]>; 170 171def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 172def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 173 174def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 175 [SDNPHasChain, SDNPOptInGlue]>; 176 177def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 178 [SDNPHasChain, SDNPMayLoad]>; 179def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 180 [SDNPHasChain, SDNPMayStore]>; 181 182// Instructions to set/unset CR bit 6 for SVR4 vararg calls 183def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 185def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 187 188// Instructions to support atomic operations 189def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, 190 [SDNPHasChain, SDNPMayLoad]>; 191def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, 192 [SDNPHasChain, SDNPMayStore]>; 193 194// Instructions to support medium and large code model 195def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>; 196def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>; 197def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>; 198 199 200// Instructions to support dynamic alloca. 201def SDTDynOp : SDTypeProfile<1, 2, []>; 202def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 203 204//===----------------------------------------------------------------------===// 205// PowerPC specific transformation functions and pattern fragments. 206// 207 208def SHL32 : SDNodeXForm<imm, [{ 209 // Transformation function: 31 - imm 210 return getI32Imm(31 - N->getZExtValue()); 211}]>; 212 213def SRL32 : SDNodeXForm<imm, [{ 214 // Transformation function: 32 - imm 215 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0); 216}]>; 217 218def LO16 : SDNodeXForm<imm, [{ 219 // Transformation function: get the low 16 bits. 220 return getI32Imm((unsigned short)N->getZExtValue()); 221}]>; 222 223def HI16 : SDNodeXForm<imm, [{ 224 // Transformation function: shift the immediate value down into the low bits. 225 return getI32Imm((unsigned)N->getZExtValue() >> 16); 226}]>; 227 228def HA16 : SDNodeXForm<imm, [{ 229 // Transformation function: shift the immediate value down into the low bits. 230 signed int Val = N->getZExtValue(); 231 return getI32Imm((Val - (signed short)Val) >> 16); 232}]>; 233def MB : SDNodeXForm<imm, [{ 234 // Transformation function: get the start bit of a mask 235 unsigned mb = 0, me; 236 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 237 return getI32Imm(mb); 238}]>; 239 240def ME : SDNodeXForm<imm, [{ 241 // Transformation function: get the end bit of a mask 242 unsigned mb, me = 0; 243 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 244 return getI32Imm(me); 245}]>; 246def maskimm32 : PatLeaf<(imm), [{ 247 // maskImm predicate - True if immediate is a run of ones. 248 unsigned mb, me; 249 if (N->getValueType(0) == MVT::i32) 250 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 251 else 252 return false; 253}]>; 254 255def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 256 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 257 // sign extended field. Used by instructions like 'addi'. 258 return (int32_t)Imm == (short)Imm; 259}]>; 260def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 261 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 262 // sign extended field. Used by instructions like 'addi'. 263 return (int64_t)Imm == (short)Imm; 264}]>; 265def immZExt16 : PatLeaf<(imm), [{ 266 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 267 // field. Used by instructions like 'ori'. 268 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 269}], LO16>; 270 271// imm16Shifted* - These match immediates where the low 16-bits are zero. There 272// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 273// identical in 32-bit mode, but in 64-bit mode, they return true if the 274// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 275// clear). 276def imm16ShiftedZExt : PatLeaf<(imm), [{ 277 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 278 // immediate are set. Used by instructions like 'xoris'. 279 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 280}], HI16>; 281 282def imm16ShiftedSExt : PatLeaf<(imm), [{ 283 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 284 // immediate are set. Used by instructions like 'addis'. Identical to 285 // imm16ShiftedZExt in 32-bit mode. 286 if (N->getZExtValue() & 0xFFFF) return false; 287 if (N->getValueType(0) == MVT::i32) 288 return true; 289 // For 64-bit, make sure it is sext right. 290 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 291}], HI16>; 292 293def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 294 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 295 // zero extended field. 296 return isUInt<32>(Imm); 297}]>; 298 299// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 300// restricted memrix (4-aligned) constants are alignment sensitive. If these 301// offsets are hidden behind TOC entries than the values of the lower-order 302// bits cannot be checked directly. As a result, we need to also incorporate 303// an alignment check into the relevant patterns. 304 305def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 306 return cast<LoadSDNode>(N)->getAlignment() >= 4; 307}]>; 308def aligned4store : PatFrag<(ops node:$val, node:$ptr), 309 (store node:$val, node:$ptr), [{ 310 return cast<StoreSDNode>(N)->getAlignment() >= 4; 311}]>; 312def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 313 return cast<LoadSDNode>(N)->getAlignment() >= 4; 314}]>; 315def aligned4pre_store : PatFrag< 316 (ops node:$val, node:$base, node:$offset), 317 (pre_store node:$val, node:$base, node:$offset), [{ 318 return cast<StoreSDNode>(N)->getAlignment() >= 4; 319}]>; 320 321def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 322 return cast<LoadSDNode>(N)->getAlignment() < 4; 323}]>; 324def unaligned4store : PatFrag<(ops node:$val, node:$ptr), 325 (store node:$val, node:$ptr), [{ 326 return cast<StoreSDNode>(N)->getAlignment() < 4; 327}]>; 328def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 329 return cast<LoadSDNode>(N)->getAlignment() < 4; 330}]>; 331 332//===----------------------------------------------------------------------===// 333// PowerPC Flag Definitions. 334 335class isPPC64 { bit PPC64 = 1; } 336class isDOT { bit RC = 1; } 337 338class RegConstraint<string C> { 339 string Constraints = C; 340} 341class NoEncode<string E> { 342 string DisableEncoding = E; 343} 344 345 346//===----------------------------------------------------------------------===// 347// PowerPC Operand Definitions. 348 349// In the default PowerPC assembler syntax, registers are specified simply 350// by number, so they cannot be distinguished from immediate values (without 351// looking at the opcode). This means that the default operand matching logic 352// for the asm parser does not work, and we need to specify custom matchers. 353// Since those can only be specified with RegisterOperand classes and not 354// directly on the RegisterClass, all instructions patterns used by the asm 355// parser need to use a RegisterOperand (instead of a RegisterClass) for 356// all their register operands. 357// For this purpose, we define one RegisterOperand for each RegisterClass, 358// using the same name as the class, just in lower case. 359 360def PPCRegGPRCAsmOperand : AsmOperandClass { 361 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber"; 362} 363def gprc : RegisterOperand<GPRC> { 364 let ParserMatchClass = PPCRegGPRCAsmOperand; 365} 366def PPCRegG8RCAsmOperand : AsmOperandClass { 367 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber"; 368} 369def g8rc : RegisterOperand<G8RC> { 370 let ParserMatchClass = PPCRegG8RCAsmOperand; 371} 372def PPCRegGPRCNoR0AsmOperand : AsmOperandClass { 373 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber"; 374} 375def gprc_nor0 : RegisterOperand<GPRC_NOR0> { 376 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand; 377} 378def PPCRegG8RCNoX0AsmOperand : AsmOperandClass { 379 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber"; 380} 381def g8rc_nox0 : RegisterOperand<G8RC_NOX0> { 382 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand; 383} 384def PPCRegF8RCAsmOperand : AsmOperandClass { 385 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber"; 386} 387def f8rc : RegisterOperand<F8RC> { 388 let ParserMatchClass = PPCRegF8RCAsmOperand; 389} 390def PPCRegF4RCAsmOperand : AsmOperandClass { 391 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber"; 392} 393def f4rc : RegisterOperand<F4RC> { 394 let ParserMatchClass = PPCRegF4RCAsmOperand; 395} 396def PPCRegVRRCAsmOperand : AsmOperandClass { 397 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber"; 398} 399def vrrc : RegisterOperand<VRRC> { 400 let ParserMatchClass = PPCRegVRRCAsmOperand; 401} 402def PPCRegCRBITRCAsmOperand : AsmOperandClass { 403 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; 404} 405def crbitrc : RegisterOperand<CRBITRC> { 406 let ParserMatchClass = PPCRegCRBITRCAsmOperand; 407} 408def PPCRegCRRCAsmOperand : AsmOperandClass { 409 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber"; 410} 411def crrc : RegisterOperand<CRRC> { 412 let ParserMatchClass = PPCRegCRRCAsmOperand; 413} 414 415def PPCU2ImmAsmOperand : AsmOperandClass { 416 let Name = "U2Imm"; let PredicateMethod = "isU2Imm"; 417 let RenderMethod = "addImmOperands"; 418} 419def u2imm : Operand<i32> { 420 let PrintMethod = "printU2ImmOperand"; 421 let ParserMatchClass = PPCU2ImmAsmOperand; 422} 423def PPCS5ImmAsmOperand : AsmOperandClass { 424 let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; 425 let RenderMethod = "addImmOperands"; 426} 427def s5imm : Operand<i32> { 428 let PrintMethod = "printS5ImmOperand"; 429 let ParserMatchClass = PPCS5ImmAsmOperand; 430 let DecoderMethod = "decodeSImmOperand<5>"; 431} 432def PPCU5ImmAsmOperand : AsmOperandClass { 433 let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; 434 let RenderMethod = "addImmOperands"; 435} 436def u5imm : Operand<i32> { 437 let PrintMethod = "printU5ImmOperand"; 438 let ParserMatchClass = PPCU5ImmAsmOperand; 439 let DecoderMethod = "decodeUImmOperand<5>"; 440} 441def PPCU6ImmAsmOperand : AsmOperandClass { 442 let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; 443 let RenderMethod = "addImmOperands"; 444} 445def u6imm : Operand<i32> { 446 let PrintMethod = "printU6ImmOperand"; 447 let ParserMatchClass = PPCU6ImmAsmOperand; 448 let DecoderMethod = "decodeUImmOperand<6>"; 449} 450def PPCS16ImmAsmOperand : AsmOperandClass { 451 let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; 452 let RenderMethod = "addImmOperands"; 453} 454def s16imm : Operand<i32> { 455 let PrintMethod = "printS16ImmOperand"; 456 let EncoderMethod = "getImm16Encoding"; 457 let ParserMatchClass = PPCS16ImmAsmOperand; 458 let DecoderMethod = "decodeSImmOperand<16>"; 459} 460def PPCU16ImmAsmOperand : AsmOperandClass { 461 let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; 462 let RenderMethod = "addImmOperands"; 463} 464def u16imm : Operand<i32> { 465 let PrintMethod = "printU16ImmOperand"; 466 let EncoderMethod = "getImm16Encoding"; 467 let ParserMatchClass = PPCU16ImmAsmOperand; 468 let DecoderMethod = "decodeUImmOperand<16>"; 469} 470def PPCS17ImmAsmOperand : AsmOperandClass { 471 let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; 472 let RenderMethod = "addImmOperands"; 473} 474def s17imm : Operand<i32> { 475 // This operand type is used for addis/lis to allow the assembler parser 476 // to accept immediates in the range -65536..65535 for compatibility with 477 // the GNU assembler. The operand is treated as 16-bit otherwise. 478 let PrintMethod = "printS16ImmOperand"; 479 let EncoderMethod = "getImm16Encoding"; 480 let ParserMatchClass = PPCS17ImmAsmOperand; 481 let DecoderMethod = "decodeSImmOperand<16>"; 482} 483def PPCDirectBrAsmOperand : AsmOperandClass { 484 let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; 485 let RenderMethod = "addBranchTargetOperands"; 486} 487def directbrtarget : Operand<OtherVT> { 488 let PrintMethod = "printBranchOperand"; 489 let EncoderMethod = "getDirectBrEncoding"; 490 let ParserMatchClass = PPCDirectBrAsmOperand; 491} 492def absdirectbrtarget : Operand<OtherVT> { 493 let PrintMethod = "printAbsBranchOperand"; 494 let EncoderMethod = "getAbsDirectBrEncoding"; 495 let ParserMatchClass = PPCDirectBrAsmOperand; 496} 497def PPCCondBrAsmOperand : AsmOperandClass { 498 let Name = "CondBr"; let PredicateMethod = "isCondBr"; 499 let RenderMethod = "addBranchTargetOperands"; 500} 501def condbrtarget : Operand<OtherVT> { 502 let PrintMethod = "printBranchOperand"; 503 let EncoderMethod = "getCondBrEncoding"; 504 let ParserMatchClass = PPCCondBrAsmOperand; 505} 506def abscondbrtarget : Operand<OtherVT> { 507 let PrintMethod = "printAbsBranchOperand"; 508 let EncoderMethod = "getAbsCondBrEncoding"; 509 let ParserMatchClass = PPCCondBrAsmOperand; 510} 511def calltarget : Operand<iPTR> { 512 let PrintMethod = "printBranchOperand"; 513 let EncoderMethod = "getDirectBrEncoding"; 514 let ParserMatchClass = PPCDirectBrAsmOperand; 515} 516def abscalltarget : Operand<iPTR> { 517 let PrintMethod = "printAbsBranchOperand"; 518 let EncoderMethod = "getAbsDirectBrEncoding"; 519 let ParserMatchClass = PPCDirectBrAsmOperand; 520} 521def PPCCRBitMaskOperand : AsmOperandClass { 522 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask"; 523} 524def crbitm: Operand<i8> { 525 let PrintMethod = "printcrbitm"; 526 let EncoderMethod = "get_crbitm_encoding"; 527 let DecoderMethod = "decodeCRBitMOperand"; 528 let ParserMatchClass = PPCCRBitMaskOperand; 529} 530// Address operands 531// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 532def PPCRegGxRCNoR0Operand : AsmOperandClass { 533 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; 534} 535def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { 536 let ParserMatchClass = PPCRegGxRCNoR0Operand; 537} 538// A version of ptr_rc usable with the asm parser. 539def PPCRegGxRCOperand : AsmOperandClass { 540 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; 541} 542def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { 543 let ParserMatchClass = PPCRegGxRCOperand; 544} 545 546def PPCDispRIOperand : AsmOperandClass { 547 let Name = "DispRI"; let PredicateMethod = "isS16Imm"; 548 let RenderMethod = "addImmOperands"; 549} 550def dispRI : Operand<iPTR> { 551 let ParserMatchClass = PPCDispRIOperand; 552} 553def PPCDispRIXOperand : AsmOperandClass { 554 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; 555 let RenderMethod = "addImmOperands"; 556} 557def dispRIX : Operand<iPTR> { 558 let ParserMatchClass = PPCDispRIXOperand; 559} 560 561def memri : Operand<iPTR> { 562 let PrintMethod = "printMemRegImm"; 563 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 564 let EncoderMethod = "getMemRIEncoding"; 565 let DecoderMethod = "decodeMemRIOperands"; 566} 567def memrr : Operand<iPTR> { 568 let PrintMethod = "printMemRegReg"; 569 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); 570} 571def memrix : Operand<iPTR> { // memri where the imm is 4-aligned. 572 let PrintMethod = "printMemRegImm"; 573 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 574 let EncoderMethod = "getMemRIXEncoding"; 575 let DecoderMethod = "decodeMemRIXOperands"; 576} 577 578// A single-register address. This is used with the SjLj 579// pseudo-instructions. 580def memr : Operand<iPTR> { 581 let MIOperandInfo = (ops ptr_rc:$ptrreg); 582} 583def PPCTLSRegOperand : AsmOperandClass { 584 let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; 585 let RenderMethod = "addTLSRegOperands"; 586} 587def tlsreg32 : Operand<i32> { 588 let EncoderMethod = "getTLSRegEncoding"; 589 let ParserMatchClass = PPCTLSRegOperand; 590} 591 592// PowerPC Predicate operand. 593def pred : Operand<OtherVT> { 594 let PrintMethod = "printPredicateOperand"; 595 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg); 596} 597 598// Define PowerPC specific addressing mode. 599def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 600def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 601def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 602def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 603 604// The address in a single register. This is used with the SjLj 605// pseudo-instructions. 606def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 607 608/// This is just the offset part of iaddr, used for preinc. 609def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 610 611//===----------------------------------------------------------------------===// 612// PowerPC Instruction Predicate Definitions. 613def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">; 614def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">; 615def IsBookE : Predicate<"PPCSubTarget->isBookE()">; 616def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">; 617 618//===----------------------------------------------------------------------===// 619// PowerPC Multiclass Definitions. 620 621multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 622 string asmbase, string asmstr, InstrItinClass itin, 623 list<dag> pattern> { 624 let BaseName = asmbase in { 625 def NAME : XForm_6<opcode, xo, OOL, IOL, 626 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 627 pattern>, RecFormRel; 628 let Defs = [CR0] in 629 def o : XForm_6<opcode, xo, OOL, IOL, 630 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 631 []>, isDOT, RecFormRel; 632 } 633} 634 635multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 636 string asmbase, string asmstr, InstrItinClass itin, 637 list<dag> pattern> { 638 let BaseName = asmbase in { 639 let Defs = [CARRY] in 640 def NAME : XForm_6<opcode, xo, OOL, IOL, 641 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 642 pattern>, RecFormRel; 643 let Defs = [CARRY, CR0] in 644 def o : XForm_6<opcode, xo, OOL, IOL, 645 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 646 []>, isDOT, RecFormRel; 647 } 648} 649 650multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 651 string asmbase, string asmstr, InstrItinClass itin, 652 list<dag> pattern> { 653 let BaseName = asmbase in { 654 let Defs = [CARRY] in 655 def NAME : XForm_10<opcode, xo, OOL, IOL, 656 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 657 pattern>, RecFormRel; 658 let Defs = [CARRY, CR0] in 659 def o : XForm_10<opcode, xo, OOL, IOL, 660 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 661 []>, isDOT, RecFormRel; 662 } 663} 664 665multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 666 string asmbase, string asmstr, InstrItinClass itin, 667 list<dag> pattern> { 668 let BaseName = asmbase in { 669 def NAME : XForm_11<opcode, xo, OOL, IOL, 670 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 671 pattern>, RecFormRel; 672 let Defs = [CR0] in 673 def o : XForm_11<opcode, xo, OOL, IOL, 674 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 675 []>, isDOT, RecFormRel; 676 } 677} 678 679multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 680 string asmbase, string asmstr, InstrItinClass itin, 681 list<dag> pattern> { 682 let BaseName = asmbase in { 683 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 684 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 685 pattern>, RecFormRel; 686 let Defs = [CR0] in 687 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 688 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 689 []>, isDOT, RecFormRel; 690 } 691} 692 693multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 694 string asmbase, string asmstr, InstrItinClass itin, 695 list<dag> pattern> { 696 let BaseName = asmbase in { 697 let Defs = [CARRY] in 698 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 699 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 700 pattern>, RecFormRel; 701 let Defs = [CARRY, CR0] in 702 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 703 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 704 []>, isDOT, RecFormRel; 705 } 706} 707 708multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 709 string asmbase, string asmstr, InstrItinClass itin, 710 list<dag> pattern> { 711 let BaseName = asmbase in { 712 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 713 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 714 pattern>, RecFormRel; 715 let Defs = [CR0] in 716 def o : XOForm_3<opcode, xo, oe, OOL, IOL, 717 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 718 []>, isDOT, RecFormRel; 719 } 720} 721 722multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 723 string asmbase, string asmstr, InstrItinClass itin, 724 list<dag> pattern> { 725 let BaseName = asmbase in { 726 let Defs = [CARRY] in 727 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 728 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 729 pattern>, RecFormRel; 730 let Defs = [CARRY, CR0] in 731 def o : XOForm_3<opcode, xo, oe, OOL, IOL, 732 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 733 []>, isDOT, RecFormRel; 734 } 735} 736 737multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 738 string asmbase, string asmstr, InstrItinClass itin, 739 list<dag> pattern> { 740 let BaseName = asmbase in { 741 def NAME : MForm_2<opcode, OOL, IOL, 742 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 743 pattern>, RecFormRel; 744 let Defs = [CR0] in 745 def o : MForm_2<opcode, OOL, IOL, 746 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 747 []>, isDOT, RecFormRel; 748 } 749} 750 751multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 752 string asmbase, string asmstr, InstrItinClass itin, 753 list<dag> pattern> { 754 let BaseName = asmbase in { 755 def NAME : MDForm_1<opcode, xo, OOL, IOL, 756 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 757 pattern>, RecFormRel; 758 let Defs = [CR0] in 759 def o : MDForm_1<opcode, xo, OOL, IOL, 760 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 761 []>, isDOT, RecFormRel; 762 } 763} 764 765multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 766 string asmbase, string asmstr, InstrItinClass itin, 767 list<dag> pattern> { 768 let BaseName = asmbase in { 769 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 770 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 771 pattern>, RecFormRel; 772 let Defs = [CR0] in 773 def o : MDSForm_1<opcode, xo, OOL, IOL, 774 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 775 []>, isDOT, RecFormRel; 776 } 777} 778 779multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 780 string asmbase, string asmstr, InstrItinClass itin, 781 list<dag> pattern> { 782 let BaseName = asmbase in { 783 let Defs = [CARRY] in 784 def NAME : XSForm_1<opcode, xo, OOL, IOL, 785 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 786 pattern>, RecFormRel; 787 let Defs = [CARRY, CR0] in 788 def o : XSForm_1<opcode, xo, OOL, IOL, 789 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 790 []>, isDOT, RecFormRel; 791 } 792} 793 794multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 795 string asmbase, string asmstr, InstrItinClass itin, 796 list<dag> pattern> { 797 let BaseName = asmbase in { 798 def NAME : XForm_26<opcode, xo, OOL, IOL, 799 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 800 pattern>, RecFormRel; 801 let Defs = [CR1] in 802 def o : XForm_26<opcode, xo, OOL, IOL, 803 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 804 []>, isDOT, RecFormRel; 805 } 806} 807 808multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 809 string asmbase, string asmstr, InstrItinClass itin, 810 list<dag> pattern> { 811 let BaseName = asmbase in { 812 def NAME : XForm_28<opcode, xo, OOL, IOL, 813 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 814 pattern>, RecFormRel; 815 let Defs = [CR1] in 816 def o : XForm_28<opcode, xo, OOL, IOL, 817 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 818 []>, isDOT, RecFormRel; 819 } 820} 821 822multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 823 string asmbase, string asmstr, InstrItinClass itin, 824 list<dag> pattern> { 825 let BaseName = asmbase in { 826 def NAME : AForm_1<opcode, xo, OOL, IOL, 827 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 828 pattern>, RecFormRel; 829 let Defs = [CR1] in 830 def o : AForm_1<opcode, xo, OOL, IOL, 831 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 832 []>, isDOT, RecFormRel; 833 } 834} 835 836multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 837 string asmbase, string asmstr, InstrItinClass itin, 838 list<dag> pattern> { 839 let BaseName = asmbase in { 840 def NAME : AForm_2<opcode, xo, OOL, IOL, 841 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 842 pattern>, RecFormRel; 843 let Defs = [CR1] in 844 def o : AForm_2<opcode, xo, OOL, IOL, 845 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 846 []>, isDOT, RecFormRel; 847 } 848} 849 850multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 851 string asmbase, string asmstr, InstrItinClass itin, 852 list<dag> pattern> { 853 let BaseName = asmbase in { 854 def NAME : AForm_3<opcode, xo, OOL, IOL, 855 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 856 pattern>, RecFormRel; 857 let Defs = [CR1] in 858 def o : AForm_3<opcode, xo, OOL, IOL, 859 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 860 []>, isDOT, RecFormRel; 861 } 862} 863 864//===----------------------------------------------------------------------===// 865// PowerPC Instruction Definitions. 866 867// Pseudo-instructions: 868 869let hasCtrlDep = 1 in { 870let Defs = [R1], Uses = [R1] in { 871def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt", 872 [(callseq_start timm:$amt)]>; 873def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2", 874 [(callseq_end timm:$amt1, timm:$amt2)]>; 875} 876 877def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS), 878 "UPDATE_VRSAVE $rD, $rS", []>; 879} 880 881let Defs = [R1], Uses = [R1] in 882def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 883 [(set i32:$result, 884 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 885 886// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 887// instruction selection into a branch sequence. 888let usesCustomInserter = 1, // Expanded after instruction selection. 889 PPC970_Single = 1 in { 890 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 891 // because either operand might become the first operand in an isel, and 892 // that operand cannot be r0. 893 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond, 894 gprc_nor0:$T, gprc_nor0:$F, 895 i32imm:$BROPC), "#SELECT_CC_I4", 896 []>; 897 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond, 898 g8rc_nox0:$T, g8rc_nox0:$F, 899 i32imm:$BROPC), "#SELECT_CC_I8", 900 []>; 901 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 902 i32imm:$BROPC), "#SELECT_CC_F4", 903 []>; 904 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 905 i32imm:$BROPC), "#SELECT_CC_F8", 906 []>; 907 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 908 i32imm:$BROPC), "#SELECT_CC_VRRC", 909 []>; 910 911 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 912 // register bit directly. 913 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond, 914 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 915 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 916 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 917 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 918 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 919 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 920 f4rc:$T, f4rc:$F), "#SELECT_F4", 921 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 922 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 923 f8rc:$T, f8rc:$F), "#SELECT_F8", 924 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 925 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 926 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 927 [(set v4i32:$dst, 928 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 929} 930 931// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 932// scavenge a register for it. 933let mayStore = 1 in { 934def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F), 935 "#SPILL_CR", []>; 936def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F), 937 "#SPILL_CRBIT", []>; 938} 939 940// RESTORE_CR - Indicate that we're restoring the CR register (previously 941// spilled), so we'll need to scavenge a register for it. 942let mayLoad = 1 in { 943def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F), 944 "#RESTORE_CR", []>; 945def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F), 946 "#RESTORE_CRBIT", []>; 947} 948 949let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 950 let isReturn = 1, Uses = [LR, RM] in 951 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 952 [(retflag)]>; 953 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 954 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 955 []>; 956 957 let isCodeGenOnly = 1 in { 958 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 959 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 960 []>; 961 962 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 963 "bcctr 12, $bi, 0", IIC_BrB, []>; 964 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 965 "bcctr 4, $bi, 0", IIC_BrB, []>; 966 } 967 } 968} 969 970let Defs = [LR] in 971 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>, 972 PPC970_Unit_BRU; 973 974let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 975 let isBarrier = 1 in { 976 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 977 "b $dst", IIC_BrB, 978 [(br bb:$dst)]>; 979 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), 980 "ba $dst", IIC_BrB, []>; 981 } 982 983 // BCC represents an arbitrary conditional branch on a predicate. 984 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 985 // a two-value operand where a dag node expects two operands. :( 986 let isCodeGenOnly = 1 in { 987 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 988 "b${cond:cc}${cond:pm} ${cond:reg}, $dst" 989 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; 990 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), 991 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; 992 993 let isReturn = 1, Uses = [LR, RM] in 994 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), 995 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 996 } 997 998 let isCodeGenOnly = 1 in { 999 let Pattern = [(brcond i1:$bi, bb:$dst)] in 1000 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1001 "bc 12, $bi, $dst">; 1002 1003 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in 1004 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1005 "bc 4, $bi, $dst">; 1006 1007 let isReturn = 1, Uses = [LR, RM] in 1008 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), 1009 "bclr 12, $bi, 0", IIC_BrB, []>; 1010 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), 1011 "bclr 4, $bi, 0", IIC_BrB, []>; 1012 } 1013 1014 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1015 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1016 "bdzlr", IIC_BrB, []>; 1017 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1018 "bdnzlr", IIC_BrB, []>; 1019 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1020 "bdzlr+", IIC_BrB, []>; 1021 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1022 "bdnzlr+", IIC_BrB, []>; 1023 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1024 "bdzlr-", IIC_BrB, []>; 1025 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1026 "bdnzlr-", IIC_BrB, []>; 1027 } 1028 1029 let Defs = [CTR], Uses = [CTR] in { 1030 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 1031 "bdz $dst">; 1032 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 1033 "bdnz $dst">; 1034 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), 1035 "bdza $dst">; 1036 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), 1037 "bdnza $dst">; 1038 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), 1039 "bdz+ $dst">; 1040 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), 1041 "bdnz+ $dst">; 1042 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), 1043 "bdza+ $dst">; 1044 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), 1045 "bdnza+ $dst">; 1046 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), 1047 "bdz- $dst">; 1048 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), 1049 "bdnz- $dst">; 1050 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), 1051 "bdza- $dst">; 1052 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), 1053 "bdnza- $dst">; 1054 } 1055} 1056 1057// The unconditional BCL used by the SjLj setjmp code. 1058let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in { 1059 let Defs = [LR], Uses = [RM] in { 1060 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), 1061 "bcl 20, 31, $dst">; 1062 } 1063} 1064 1065let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1066 // Convenient aliases for call instructions 1067 let Uses = [RM] in { 1068 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1069 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1070 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1071 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; 1072 1073 let isCodeGenOnly = 1 in { 1074 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), 1075 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; 1076 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1077 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; 1078 1079 def BCL : BForm_4<16, 12, 0, 1, (outs), 1080 (ins crbitrc:$bi, condbrtarget:$dst), 1081 "bcl 12, $bi, $dst">; 1082 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1083 (ins crbitrc:$bi, condbrtarget:$dst), 1084 "bcl 4, $bi, $dst">; 1085 } 1086 } 1087 let Uses = [CTR, RM] in { 1088 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1089 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1090 Requires<[In32BitMode]>; 1091 1092 let isCodeGenOnly = 1 in { 1093 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 1094 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1095 []>; 1096 1097 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 1098 "bcctrl 12, $bi, 0", IIC_BrB, []>; 1099 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 1100 "bcctrl 4, $bi, 0", IIC_BrB, []>; 1101 } 1102 } 1103 let Uses = [LR, RM] in { 1104 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1105 "blrl", IIC_BrB, []>; 1106 1107 let isCodeGenOnly = 1 in { 1108 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), 1109 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1110 []>; 1111 1112 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), 1113 "bclrl 12, $bi, 0", IIC_BrB, []>; 1114 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), 1115 "bclrl 4, $bi, 0", IIC_BrB, []>; 1116 } 1117 } 1118 let Defs = [CTR], Uses = [CTR, RM] in { 1119 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), 1120 "bdzl $dst">; 1121 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), 1122 "bdnzl $dst">; 1123 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), 1124 "bdzla $dst">; 1125 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), 1126 "bdnzla $dst">; 1127 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), 1128 "bdzl+ $dst">; 1129 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), 1130 "bdnzl+ $dst">; 1131 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), 1132 "bdzla+ $dst">; 1133 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), 1134 "bdnzla+ $dst">; 1135 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), 1136 "bdzl- $dst">; 1137 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), 1138 "bdnzl- $dst">; 1139 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), 1140 "bdzla- $dst">; 1141 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), 1142 "bdnzla- $dst">; 1143 } 1144 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1145 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1146 "bdzlrl", IIC_BrB, []>; 1147 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1148 "bdnzlrl", IIC_BrB, []>; 1149 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1150 "bdzlrl+", IIC_BrB, []>; 1151 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1152 "bdnzlrl+", IIC_BrB, []>; 1153 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1154 "bdzlrl-", IIC_BrB, []>; 1155 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1156 "bdnzlrl-", IIC_BrB, []>; 1157 } 1158} 1159 1160let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1161def TCRETURNdi :Pseudo< (outs), 1162 (ins calltarget:$dst, i32imm:$offset), 1163 "#TC_RETURNd $dst $offset", 1164 []>; 1165 1166 1167let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1168def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1169 "#TC_RETURNa $func $offset", 1170 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1171 1172let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1173def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1174 "#TC_RETURNr $dst $offset", 1175 []>; 1176 1177 1178let isCodeGenOnly = 1 in { 1179 1180let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1181 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1182def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1183 []>, Requires<[In32BitMode]>; 1184 1185let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1186 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1187def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 1188 "b $dst", IIC_BrB, 1189 []>; 1190 1191let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1192 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1193def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 1194 "ba $dst", IIC_BrB, 1195 []>; 1196 1197} 1198 1199let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 1200 let Defs = [CTR] in 1201 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 1202 "#EH_SJLJ_SETJMP32", 1203 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1204 Requires<[In32BitMode]>; 1205 let isTerminator = 1 in 1206 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf), 1207 "#EH_SJLJ_LONGJMP32", 1208 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1209 Requires<[In32BitMode]>; 1210} 1211 1212let isBranch = 1, isTerminator = 1 in { 1213 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst), 1214 "#EH_SjLj_Setup\t$dst", []>; 1215} 1216 1217// System call. 1218let PPC970_Unit = 7 in { 1219 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), 1220 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; 1221} 1222 1223// DCB* instructions. 1224def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", 1225 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 1226 PPC970_DGroup_Single; 1227def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst", 1228 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 1229 PPC970_DGroup_Single; 1230def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", 1231 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 1232 PPC970_DGroup_Single; 1233def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", 1234 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 1235 PPC970_DGroup_Single; 1236def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst", 1237 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 1238 PPC970_DGroup_Single; 1239def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst", 1240 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 1241 PPC970_DGroup_Single; 1242def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", 1243 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 1244 PPC970_DGroup_Single; 1245def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", 1246 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 1247 PPC970_DGroup_Single; 1248 1249def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 1250 (DCBT xoaddr:$dst)>; 1251 1252// Atomic operations 1253let usesCustomInserter = 1 in { 1254 let Defs = [CR0] in { 1255 def ATOMIC_LOAD_ADD_I8 : Pseudo< 1256 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1257 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>; 1258 def ATOMIC_LOAD_SUB_I8 : Pseudo< 1259 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1260 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>; 1261 def ATOMIC_LOAD_AND_I8 : Pseudo< 1262 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1263 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>; 1264 def ATOMIC_LOAD_OR_I8 : Pseudo< 1265 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1266 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>; 1267 def ATOMIC_LOAD_XOR_I8 : Pseudo< 1268 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1269 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>; 1270 def ATOMIC_LOAD_NAND_I8 : Pseudo< 1271 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1272 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>; 1273 def ATOMIC_LOAD_ADD_I16 : Pseudo< 1274 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1275 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>; 1276 def ATOMIC_LOAD_SUB_I16 : Pseudo< 1277 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1278 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>; 1279 def ATOMIC_LOAD_AND_I16 : Pseudo< 1280 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1281 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>; 1282 def ATOMIC_LOAD_OR_I16 : Pseudo< 1283 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1284 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>; 1285 def ATOMIC_LOAD_XOR_I16 : Pseudo< 1286 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1287 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>; 1288 def ATOMIC_LOAD_NAND_I16 : Pseudo< 1289 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1290 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>; 1291 def ATOMIC_LOAD_ADD_I32 : Pseudo< 1292 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1293 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>; 1294 def ATOMIC_LOAD_SUB_I32 : Pseudo< 1295 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1296 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>; 1297 def ATOMIC_LOAD_AND_I32 : Pseudo< 1298 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1299 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>; 1300 def ATOMIC_LOAD_OR_I32 : Pseudo< 1301 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1302 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>; 1303 def ATOMIC_LOAD_XOR_I32 : Pseudo< 1304 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1305 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>; 1306 def ATOMIC_LOAD_NAND_I32 : Pseudo< 1307 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1308 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>; 1309 1310 def ATOMIC_CMP_SWAP_I8 : Pseudo< 1311 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1312 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>; 1313 def ATOMIC_CMP_SWAP_I16 : Pseudo< 1314 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1315 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>; 1316 def ATOMIC_CMP_SWAP_I32 : Pseudo< 1317 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1318 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>; 1319 1320 def ATOMIC_SWAP_I8 : Pseudo< 1321 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1322 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>; 1323 def ATOMIC_SWAP_I16 : Pseudo< 1324 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1325 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>; 1326 def ATOMIC_SWAP_I32 : Pseudo< 1327 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1328 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>; 1329 } 1330} 1331 1332// Instructions to support atomic operations 1333def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src), 1334 "lwarx $rD, $src", IIC_LdStLWARX, 1335 [(set i32:$rD, (PPClarx xoaddr:$src))]>; 1336 1337let Defs = [CR0] in 1338def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst), 1339 "stwcx. $rS, $dst", IIC_LdStSTWCX, 1340 [(PPCstcx i32:$rS, xoaddr:$dst)]>, 1341 isDOT; 1342 1343let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 1344def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 1345 1346def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm), 1347 "twi $to, $rA, $imm", IIC_IntTrapW, []>; 1348def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB), 1349 "tw $to, $rA, $rB", IIC_IntTrapW, []>; 1350def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm), 1351 "tdi $to, $rA, $imm", IIC_IntTrapD, []>; 1352def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB), 1353 "td $to, $rA, $rB", IIC_IntTrapD, []>; 1354 1355//===----------------------------------------------------------------------===// 1356// PPC32 Load Instructions. 1357// 1358 1359// Unindexed (r+i) Loads. 1360let canFoldAsLoad = 1, PPC970_Unit = 2 in { 1361def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), 1362 "lbz $rD, $src", IIC_LdStLoad, 1363 [(set i32:$rD, (zextloadi8 iaddr:$src))]>; 1364def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), 1365 "lha $rD, $src", IIC_LdStLHA, 1366 [(set i32:$rD, (sextloadi16 iaddr:$src))]>, 1367 PPC970_DGroup_Cracked; 1368def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), 1369 "lhz $rD, $src", IIC_LdStLoad, 1370 [(set i32:$rD, (zextloadi16 iaddr:$src))]>; 1371def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), 1372 "lwz $rD, $src", IIC_LdStLoad, 1373 [(set i32:$rD, (load iaddr:$src))]>; 1374 1375def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), 1376 "lfs $rD, $src", IIC_LdStLFD, 1377 [(set f32:$rD, (load iaddr:$src))]>; 1378def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), 1379 "lfd $rD, $src", IIC_LdStLFD, 1380 [(set f64:$rD, (load iaddr:$src))]>; 1381 1382 1383// Unindexed (r+i) Loads with Update (preinc). 1384let mayLoad = 1, neverHasSideEffects = 1 in { 1385def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1386 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1387 []>, RegConstraint<"$addr.reg = $ea_result">, 1388 NoEncode<"$ea_result">; 1389 1390def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1391 "lhau $rD, $addr", IIC_LdStLHAU, 1392 []>, RegConstraint<"$addr.reg = $ea_result">, 1393 NoEncode<"$ea_result">; 1394 1395def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1396 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1397 []>, RegConstraint<"$addr.reg = $ea_result">, 1398 NoEncode<"$ea_result">; 1399 1400def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1401 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1402 []>, RegConstraint<"$addr.reg = $ea_result">, 1403 NoEncode<"$ea_result">; 1404 1405def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1406 "lfsu $rD, $addr", IIC_LdStLFDU, 1407 []>, RegConstraint<"$addr.reg = $ea_result">, 1408 NoEncode<"$ea_result">; 1409 1410def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1411 "lfdu $rD, $addr", IIC_LdStLFDU, 1412 []>, RegConstraint<"$addr.reg = $ea_result">, 1413 NoEncode<"$ea_result">; 1414 1415 1416// Indexed (r+r) Loads with Update (preinc). 1417def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1418 (ins memrr:$addr), 1419 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1420 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1421 NoEncode<"$ea_result">; 1422 1423def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1424 (ins memrr:$addr), 1425 "lhaux $rD, $addr", IIC_LdStLHAUX, 1426 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1427 NoEncode<"$ea_result">; 1428 1429def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1430 (ins memrr:$addr), 1431 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1432 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1433 NoEncode<"$ea_result">; 1434 1435def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1436 (ins memrr:$addr), 1437 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1438 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1439 NoEncode<"$ea_result">; 1440 1441def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), 1442 (ins memrr:$addr), 1443 "lfsux $rD, $addr", IIC_LdStLFDUX, 1444 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1445 NoEncode<"$ea_result">; 1446 1447def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), 1448 (ins memrr:$addr), 1449 "lfdux $rD, $addr", IIC_LdStLFDUX, 1450 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1451 NoEncode<"$ea_result">; 1452} 1453} 1454 1455// Indexed (r+r) Loads. 1456// 1457let canFoldAsLoad = 1, PPC970_Unit = 2 in { 1458def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src), 1459 "lbzx $rD, $src", IIC_LdStLoad, 1460 [(set i32:$rD, (zextloadi8 xaddr:$src))]>; 1461def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src), 1462 "lhax $rD, $src", IIC_LdStLHA, 1463 [(set i32:$rD, (sextloadi16 xaddr:$src))]>, 1464 PPC970_DGroup_Cracked; 1465def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src), 1466 "lhzx $rD, $src", IIC_LdStLoad, 1467 [(set i32:$rD, (zextloadi16 xaddr:$src))]>; 1468def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src), 1469 "lwzx $rD, $src", IIC_LdStLoad, 1470 [(set i32:$rD, (load xaddr:$src))]>; 1471 1472 1473def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src), 1474 "lhbrx $rD, $src", IIC_LdStLoad, 1475 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>; 1476def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src), 1477 "lwbrx $rD, $src", IIC_LdStLoad, 1478 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>; 1479 1480def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src), 1481 "lfsx $frD, $src", IIC_LdStLFD, 1482 [(set f32:$frD, (load xaddr:$src))]>; 1483def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src), 1484 "lfdx $frD, $src", IIC_LdStLFD, 1485 [(set f64:$frD, (load xaddr:$src))]>; 1486 1487def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src), 1488 "lfiwax $frD, $src", IIC_LdStLFD, 1489 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>; 1490def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src), 1491 "lfiwzx $frD, $src", IIC_LdStLFD, 1492 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>; 1493} 1494 1495// Load Multiple 1496def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), 1497 "lmw $rD, $src", IIC_LdStLMW, []>; 1498 1499//===----------------------------------------------------------------------===// 1500// PPC32 Store Instructions. 1501// 1502 1503// Unindexed (r+i) Stores. 1504let PPC970_Unit = 2 in { 1505def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src), 1506 "stb $rS, $src", IIC_LdStStore, 1507 [(truncstorei8 i32:$rS, iaddr:$src)]>; 1508def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src), 1509 "sth $rS, $src", IIC_LdStStore, 1510 [(truncstorei16 i32:$rS, iaddr:$src)]>; 1511def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src), 1512 "stw $rS, $src", IIC_LdStStore, 1513 [(store i32:$rS, iaddr:$src)]>; 1514def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), 1515 "stfs $rS, $dst", IIC_LdStSTFD, 1516 [(store f32:$rS, iaddr:$dst)]>; 1517def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), 1518 "stfd $rS, $dst", IIC_LdStSTFD, 1519 [(store f64:$rS, iaddr:$dst)]>; 1520} 1521 1522// Unindexed (r+i) Stores with Update (preinc). 1523let PPC970_Unit = 2, mayStore = 1 in { 1524def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1525 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 1526 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1527def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1528 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 1529 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1530def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1531 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 1532 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1533def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), 1534 "stfsu $rS, $dst", IIC_LdStSTFDU, []>, 1535 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1536def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), 1537 "stfdu $rS, $dst", IIC_LdStSTFDU, []>, 1538 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1539} 1540 1541// Patterns to match the pre-inc stores. We can't put the patterns on 1542// the instruction definitions directly as ISel wants the address base 1543// and offset to be separate operands, not a single complex operand. 1544def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1545 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 1546def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1547 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 1548def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1549 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 1550def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1551 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 1552def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1553 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 1554 1555// Indexed (r+r) Stores. 1556let PPC970_Unit = 2 in { 1557def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst), 1558 "stbx $rS, $dst", IIC_LdStStore, 1559 [(truncstorei8 i32:$rS, xaddr:$dst)]>, 1560 PPC970_DGroup_Cracked; 1561def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst), 1562 "sthx $rS, $dst", IIC_LdStStore, 1563 [(truncstorei16 i32:$rS, xaddr:$dst)]>, 1564 PPC970_DGroup_Cracked; 1565def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst), 1566 "stwx $rS, $dst", IIC_LdStStore, 1567 [(store i32:$rS, xaddr:$dst)]>, 1568 PPC970_DGroup_Cracked; 1569 1570def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst), 1571 "sthbrx $rS, $dst", IIC_LdStStore, 1572 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>, 1573 PPC970_DGroup_Cracked; 1574def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst), 1575 "stwbrx $rS, $dst", IIC_LdStStore, 1576 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>, 1577 PPC970_DGroup_Cracked; 1578 1579def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), 1580 "stfiwx $frS, $dst", IIC_LdStSTFD, 1581 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>; 1582 1583def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), 1584 "stfsx $frS, $dst", IIC_LdStSTFD, 1585 [(store f32:$frS, xaddr:$dst)]>; 1586def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), 1587 "stfdx $frS, $dst", IIC_LdStSTFD, 1588 [(store f64:$frS, xaddr:$dst)]>; 1589} 1590 1591// Indexed (r+r) Stores with Update (preinc). 1592let PPC970_Unit = 2, mayStore = 1 in { 1593def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1594 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 1595 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1596 PPC970_DGroup_Cracked; 1597def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1598 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 1599 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1600 PPC970_DGroup_Cracked; 1601def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1602 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 1603 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1604 PPC970_DGroup_Cracked; 1605def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst), 1606 "stfsux $rS, $dst", IIC_LdStSTFDU, []>, 1607 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1608 PPC970_DGroup_Cracked; 1609def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst), 1610 "stfdux $rS, $dst", IIC_LdStSTFDU, []>, 1611 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1612 PPC970_DGroup_Cracked; 1613} 1614 1615// Patterns to match the pre-inc stores. We can't put the patterns on 1616// the instruction definitions directly as ISel wants the address base 1617// and offset to be separate operands, not a single complex operand. 1618def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1619 (STBUX $rS, $ptrreg, $ptroff)>; 1620def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1621 (STHUX $rS, $ptrreg, $ptroff)>; 1622def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1623 (STWUX $rS, $ptrreg, $ptroff)>; 1624def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1625 (STFSUX $rS, $ptrreg, $ptroff)>; 1626def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1627 (STFDUX $rS, $ptrreg, $ptroff)>; 1628 1629// Store Multiple 1630def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), 1631 "stmw $rS, $dst", IIC_LdStLMW, []>; 1632 1633def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L), 1634 "sync $L", IIC_LdStSync, []>, Requires<[IsNotBookE]>; 1635 1636let isCodeGenOnly = 1 in { 1637 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 1638 "msync", IIC_LdStSync, []>, Requires<[IsBookE]> { 1639 let L = 0; 1640 } 1641} 1642 1643def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>; 1644def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>; 1645 1646//===----------------------------------------------------------------------===// 1647// PPC32 Arithmetic Instructions. 1648// 1649 1650let PPC970_Unit = 1 in { // FXU Operations. 1651def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), 1652 "addi $rD, $rA, $imm", IIC_IntSimple, 1653 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; 1654let BaseName = "addic" in { 1655let Defs = [CARRY] in 1656def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1657 "addic $rD, $rA, $imm", IIC_IntGeneral, 1658 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, 1659 RecFormRel, PPC970_DGroup_Cracked; 1660let Defs = [CARRY, CR0] in 1661def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1662 "addic. $rD, $rA, $imm", IIC_IntGeneral, 1663 []>, isDOT, RecFormRel; 1664} 1665def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), 1666 "addis $rD, $rA, $imm", IIC_IntSimple, 1667 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; 1668let isCodeGenOnly = 1 in 1669def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), 1670 "la $rD, $sym($rA)", IIC_IntGeneral, 1671 [(set i32:$rD, (add i32:$rA, 1672 (PPClo tglobaladdr:$sym, 0)))]>; 1673def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1674 "mulli $rD, $rA, $imm", IIC_IntMulLI, 1675 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; 1676let Defs = [CARRY] in 1677def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1678 "subfic $rD, $rA, $imm", IIC_IntGeneral, 1679 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; 1680 1681let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 1682 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), 1683 "li $rD, $imm", IIC_IntSimple, 1684 [(set i32:$rD, imm32SExt16:$imm)]>; 1685 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), 1686 "lis $rD, $imm", IIC_IntSimple, 1687 [(set i32:$rD, imm16ShiftedSExt:$imm)]>; 1688} 1689} 1690 1691let PPC970_Unit = 1 in { // FXU Operations. 1692let Defs = [CR0] in { 1693def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1694 "andi. $dst, $src1, $src2", IIC_IntGeneral, 1695 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, 1696 isDOT; 1697def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1698 "andis. $dst, $src1, $src2", IIC_IntGeneral, 1699 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, 1700 isDOT; 1701} 1702def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1703 "ori $dst, $src1, $src2", IIC_IntSimple, 1704 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; 1705def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1706 "oris $dst, $src1, $src2", IIC_IntSimple, 1707 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; 1708def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1709 "xori $dst, $src1, $src2", IIC_IntSimple, 1710 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; 1711def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1712 "xoris $dst, $src1, $src2", IIC_IntSimple, 1713 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; 1714 1715def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 1716 []>; 1717let isCodeGenOnly = 1 in { 1718// The POWER6 and POWER7 have special group-terminating nops. 1719def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 1720 "ori 1, 1, 0", IIC_IntSimple, []>; 1721def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 1722 "ori 2, 2, 0", IIC_IntSimple, []>; 1723} 1724 1725let isCompare = 1, neverHasSideEffects = 1 in { 1726 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), 1727 "cmpwi $crD, $rA, $imm", IIC_IntCompare>; 1728 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), 1729 "cmplwi $dst, $src1, $src2", IIC_IntCompare>; 1730} 1731} 1732 1733let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations. 1734let isCommutable = 1 in { 1735defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1736 "nand", "$rA, $rS, $rB", IIC_IntSimple, 1737 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; 1738defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1739 "and", "$rA, $rS, $rB", IIC_IntSimple, 1740 [(set i32:$rA, (and i32:$rS, i32:$rB))]>; 1741} // isCommutable 1742defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1743 "andc", "$rA, $rS, $rB", IIC_IntSimple, 1744 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; 1745let isCommutable = 1 in { 1746defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1747 "or", "$rA, $rS, $rB", IIC_IntSimple, 1748 [(set i32:$rA, (or i32:$rS, i32:$rB))]>; 1749defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1750 "nor", "$rA, $rS, $rB", IIC_IntSimple, 1751 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; 1752} // isCommutable 1753defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1754 "orc", "$rA, $rS, $rB", IIC_IntSimple, 1755 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; 1756let isCommutable = 1 in { 1757defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1758 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 1759 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; 1760defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1761 "xor", "$rA, $rS, $rB", IIC_IntSimple, 1762 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; 1763} // isCommutable 1764defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1765 "slw", "$rA, $rS, $rB", IIC_IntGeneral, 1766 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>; 1767defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1768 "srw", "$rA, $rS, $rB", IIC_IntGeneral, 1769 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>; 1770defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1771 "sraw", "$rA, $rS, $rB", IIC_IntShift, 1772 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>; 1773} 1774 1775let PPC970_Unit = 1 in { // FXU Operations. 1776let neverHasSideEffects = 1 in { 1777defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), 1778 "srawi", "$rA, $rS, $SH", IIC_IntShift, 1779 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>; 1780defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), 1781 "cntlzw", "$rA, $rS", IIC_IntGeneral, 1782 [(set i32:$rA, (ctlz i32:$rS))]>; 1783defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), 1784 "extsb", "$rA, $rS", IIC_IntSimple, 1785 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>; 1786defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), 1787 "extsh", "$rA, $rS", IIC_IntSimple, 1788 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>; 1789} 1790let isCompare = 1, neverHasSideEffects = 1 in { 1791 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 1792 "cmpw $crD, $rA, $rB", IIC_IntCompare>; 1793 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 1794 "cmplw $crD, $rA, $rB", IIC_IntCompare>; 1795} 1796} 1797let PPC970_Unit = 3 in { // FPU Operations. 1798//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 1799// "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 1800let isCompare = 1, neverHasSideEffects = 1 in { 1801 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 1802 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 1803 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1804 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 1805 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 1806} 1807 1808let Uses = [RM] in { 1809 let neverHasSideEffects = 1 in { 1810 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), 1811 "fctiw", "$frD, $frB", IIC_FPGeneral, 1812 []>; 1813 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), 1814 "fctiwz", "$frD, $frB", IIC_FPGeneral, 1815 [(set f64:$frD, (PPCfctiwz f64:$frB))]>; 1816 1817 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), 1818 "frsp", "$frD, $frB", IIC_FPGeneral, 1819 [(set f32:$frD, (fround f64:$frB))]>; 1820 1821 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1822 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), 1823 "frin", "$frD, $frB", IIC_FPGeneral, 1824 [(set f64:$frD, (frnd f64:$frB))]>; 1825 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), 1826 "frin", "$frD, $frB", IIC_FPGeneral, 1827 [(set f32:$frD, (frnd f32:$frB))]>; 1828 } 1829 1830 let neverHasSideEffects = 1 in { 1831 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1832 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), 1833 "frip", "$frD, $frB", IIC_FPGeneral, 1834 [(set f64:$frD, (fceil f64:$frB))]>; 1835 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), 1836 "frip", "$frD, $frB", IIC_FPGeneral, 1837 [(set f32:$frD, (fceil f32:$frB))]>; 1838 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1839 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), 1840 "friz", "$frD, $frB", IIC_FPGeneral, 1841 [(set f64:$frD, (ftrunc f64:$frB))]>; 1842 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), 1843 "friz", "$frD, $frB", IIC_FPGeneral, 1844 [(set f32:$frD, (ftrunc f32:$frB))]>; 1845 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1846 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), 1847 "frim", "$frD, $frB", IIC_FPGeneral, 1848 [(set f64:$frD, (ffloor f64:$frB))]>; 1849 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), 1850 "frim", "$frD, $frB", IIC_FPGeneral, 1851 [(set f32:$frD, (ffloor f32:$frB))]>; 1852 1853 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), 1854 "fsqrt", "$frD, $frB", IIC_FPSqrtD, 1855 [(set f64:$frD, (fsqrt f64:$frB))]>; 1856 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), 1857 "fsqrts", "$frD, $frB", IIC_FPSqrtS, 1858 [(set f32:$frD, (fsqrt f32:$frB))]>; 1859 } 1860 } 1861} 1862 1863/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 1864/// often coalesced away and we don't want the dispatch group builder to think 1865/// that they will fill slots (which could cause the load of a LSU reject to 1866/// sneak into a d-group with a store). 1867let neverHasSideEffects = 1 in 1868defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), 1869 "fmr", "$frD, $frB", IIC_FPGeneral, 1870 []>, // (set f32:$frD, f32:$frB) 1871 PPC970_Unit_Pseudo; 1872 1873let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations. 1874// These are artificially split into two different forms, for 4/8 byte FP. 1875defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), 1876 "fabs", "$frD, $frB", IIC_FPGeneral, 1877 [(set f32:$frD, (fabs f32:$frB))]>; 1878let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1879defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), 1880 "fabs", "$frD, $frB", IIC_FPGeneral, 1881 [(set f64:$frD, (fabs f64:$frB))]>; 1882defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), 1883 "fnabs", "$frD, $frB", IIC_FPGeneral, 1884 [(set f32:$frD, (fneg (fabs f32:$frB)))]>; 1885let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1886defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), 1887 "fnabs", "$frD, $frB", IIC_FPGeneral, 1888 [(set f64:$frD, (fneg (fabs f64:$frB)))]>; 1889defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), 1890 "fneg", "$frD, $frB", IIC_FPGeneral, 1891 [(set f32:$frD, (fneg f32:$frB))]>; 1892let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1893defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), 1894 "fneg", "$frD, $frB", IIC_FPGeneral, 1895 [(set f64:$frD, (fneg f64:$frB))]>; 1896 1897defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB), 1898 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 1899 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>; 1900let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1901defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB), 1902 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 1903 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>; 1904 1905// Reciprocal estimates. 1906defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), 1907 "fre", "$frD, $frB", IIC_FPGeneral, 1908 [(set f64:$frD, (PPCfre f64:$frB))]>; 1909defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), 1910 "fres", "$frD, $frB", IIC_FPGeneral, 1911 [(set f32:$frD, (PPCfre f32:$frB))]>; 1912defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), 1913 "frsqrte", "$frD, $frB", IIC_FPGeneral, 1914 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; 1915defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), 1916 "frsqrtes", "$frD, $frB", IIC_FPGeneral, 1917 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; 1918} 1919 1920// XL-Form instructions. condition register logical ops. 1921// 1922let neverHasSideEffects = 1 in 1923def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 1924 "mcrf $BF, $BFA", IIC_BrMCR>, 1925 PPC970_DGroup_First, PPC970_Unit_CRU; 1926 1927let isCommutable = 1 in { 1928def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 1929 (ins crbitrc:$CRA, crbitrc:$CRB), 1930 "crand $CRD, $CRA, $CRB", IIC_BrCR, 1931 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 1932 1933def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 1934 (ins crbitrc:$CRA, crbitrc:$CRB), 1935 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 1936 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 1937 1938def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 1939 (ins crbitrc:$CRA, crbitrc:$CRB), 1940 "cror $CRD, $CRA, $CRB", IIC_BrCR, 1941 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 1942 1943def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 1944 (ins crbitrc:$CRA, crbitrc:$CRB), 1945 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 1946 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 1947 1948def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 1949 (ins crbitrc:$CRA, crbitrc:$CRB), 1950 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 1951 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 1952 1953def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 1954 (ins crbitrc:$CRA, crbitrc:$CRB), 1955 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 1956 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 1957} // isCommutable 1958 1959def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 1960 (ins crbitrc:$CRA, crbitrc:$CRB), 1961 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 1962 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 1963 1964def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 1965 (ins crbitrc:$CRA, crbitrc:$CRB), 1966 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 1967 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 1968 1969let isCodeGenOnly = 1 in { 1970def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), 1971 "creqv $dst, $dst, $dst", IIC_BrCR, 1972 [(set i1:$dst, 1)]>; 1973 1974def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), 1975 "crxor $dst, $dst, $dst", IIC_BrCR, 1976 [(set i1:$dst, 0)]>; 1977 1978let Defs = [CR1EQ], CRD = 6 in { 1979def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 1980 "creqv 6, 6, 6", IIC_BrCR, 1981 [(PPCcr6set)]>; 1982 1983def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 1984 "crxor 6, 6, 6", IIC_BrCR, 1985 [(PPCcr6unset)]>; 1986} 1987} 1988 1989// XFX-Form instructions. Instructions that deal with SPRs. 1990// 1991 1992def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 1993 "mfspr $RT, $SPR", IIC_SprMFSPR>; 1994def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 1995 "mtspr $SPR, $RT", IIC_SprMTSPR>; 1996 1997def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 1998 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>; 1999 2000let Uses = [CTR] in { 2001def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), 2002 "mfctr $rT", IIC_SprMFSPR>, 2003 PPC970_DGroup_First, PPC970_Unit_FXU; 2004} 2005let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { 2006def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2007 "mtctr $rS", IIC_SprMTSPR>, 2008 PPC970_DGroup_First, PPC970_Unit_FXU; 2009} 2010let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { 2011let Pattern = [(int_ppc_mtctr i32:$rS)] in 2012def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2013 "mtctr $rS", IIC_SprMTSPR>, 2014 PPC970_DGroup_First, PPC970_Unit_FXU; 2015} 2016 2017let Defs = [LR] in { 2018def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), 2019 "mtlr $rS", IIC_SprMTSPR>, 2020 PPC970_DGroup_First, PPC970_Unit_FXU; 2021} 2022let Uses = [LR] in { 2023def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), 2024 "mflr $rT", IIC_SprMFSPR>, 2025 PPC970_DGroup_First, PPC970_Unit_FXU; 2026} 2027 2028let isCodeGenOnly = 1 in { 2029 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2030 // like a GPR on the PPC970. As such, copies in and out have the same 2031 // performance characteristics as an OR instruction. 2032 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), 2033 "mtspr 256, $rS", IIC_IntGeneral>, 2034 PPC970_DGroup_Single, PPC970_Unit_FXU; 2035 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), 2036 "mfspr $rT, 256", IIC_IntGeneral>, 2037 PPC970_DGroup_First, PPC970_Unit_FXU; 2038 2039 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, 2040 (outs VRSAVERC:$reg), (ins gprc:$rS), 2041 "mtspr 256, $rS", IIC_IntGeneral>, 2042 PPC970_DGroup_Single, PPC970_Unit_FXU; 2043 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), 2044 (ins VRSAVERC:$reg), 2045 "mfspr $rT, 256", IIC_IntGeneral>, 2046 PPC970_DGroup_First, PPC970_Unit_FXU; 2047} 2048 2049// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register, 2050// so we'll need to scavenge a register for it. 2051let mayStore = 1 in 2052def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F), 2053 "#SPILL_VRSAVE", []>; 2054 2055// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously 2056// spilled), so we'll need to scavenge a register for it. 2057let mayLoad = 1 in 2058def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F), 2059 "#RESTORE_VRSAVE", []>; 2060 2061let neverHasSideEffects = 1 in { 2062def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), 2063 "mtocrf $FXM, $ST", IIC_BrMCRX>, 2064 PPC970_DGroup_First, PPC970_Unit_CRU; 2065 2066def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), 2067 "mtcrf $FXM, $rS", IIC_BrMCRX>, 2068 PPC970_MicroCode, PPC970_Unit_CRU; 2069 2070let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking. 2071def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), 2072 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 2073 PPC970_DGroup_First, PPC970_Unit_CRU; 2074 2075def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), 2076 "mfcr $rT", IIC_SprMFCR>, 2077 PPC970_MicroCode, PPC970_Unit_CRU; 2078} // neverHasSideEffects = 1 2079 2080// Pseudo instruction to perform FADD in round-to-zero mode. 2081let usesCustomInserter = 1, Uses = [RM] in { 2082 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2083 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>; 2084} 2085 2086// The above pseudo gets expanded to make use of the following instructions 2087// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2088let Uses = [RM], Defs = [RM] in { 2089 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2090 "mtfsb0 $FM", IIC_IntMTFSB0, []>, 2091 PPC970_DGroup_Single, PPC970_Unit_FPU; 2092 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2093 "mtfsb1 $FM", IIC_IntMTFSB0, []>, 2094 PPC970_DGroup_Single, PPC970_Unit_FPU; 2095 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), 2096 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>, 2097 PPC970_DGroup_Single, PPC970_Unit_FPU; 2098} 2099let Uses = [RM] in { 2100 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2101 "mffs $rT", IIC_IntMFFS, 2102 [(set f64:$rT, (PPCmffs))]>, 2103 PPC970_DGroup_Single, PPC970_Unit_FPU; 2104} 2105 2106 2107let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations. 2108// XO-Form instructions. Arithmetic instructions that can set overflow bit 2109let isCommutable = 1 in 2110defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2111 "add", "$rT, $rA, $rB", IIC_IntSimple, 2112 [(set i32:$rT, (add i32:$rA, i32:$rB))]>; 2113let isCodeGenOnly = 1 in 2114def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB), 2115 "add $rT, $rA, $rB", IIC_IntSimple, 2116 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>; 2117let isCommutable = 1 in 2118defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2119 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 2120 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, 2121 PPC970_DGroup_Cracked; 2122 2123defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2124 "divw", "$rT, $rA, $rB", IIC_IntDivW, 2125 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>, 2126 PPC970_DGroup_First, PPC970_DGroup_Cracked; 2127defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2128 "divwu", "$rT, $rA, $rB", IIC_IntDivW, 2129 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>, 2130 PPC970_DGroup_First, PPC970_DGroup_Cracked; 2131let isCommutable = 1 in { 2132defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2133 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW, 2134 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; 2135defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2136 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, 2137 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; 2138defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2139 "mullw", "$rT, $rA, $rB", IIC_IntMulHW, 2140 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; 2141} // isCommutable 2142defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2143 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 2144 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; 2145defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2146 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 2147 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, 2148 PPC970_DGroup_Cracked; 2149defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), 2150 "neg", "$rT, $rA", IIC_IntSimple, 2151 [(set i32:$rT, (ineg i32:$rA))]>; 2152let Uses = [CARRY] in { 2153let isCommutable = 1 in 2154defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2155 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 2156 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; 2157defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), 2158 "addme", "$rT, $rA", IIC_IntGeneral, 2159 [(set i32:$rT, (adde i32:$rA, -1))]>; 2160defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), 2161 "addze", "$rT, $rA", IIC_IntGeneral, 2162 [(set i32:$rT, (adde i32:$rA, 0))]>; 2163defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2164 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 2165 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; 2166defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), 2167 "subfme", "$rT, $rA", IIC_IntGeneral, 2168 [(set i32:$rT, (sube -1, i32:$rA))]>; 2169defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), 2170 "subfze", "$rT, $rA", IIC_IntGeneral, 2171 [(set i32:$rT, (sube 0, i32:$rA))]>; 2172} 2173} 2174 2175// A-Form instructions. Most of the instructions executed in the FPU are of 2176// this type. 2177// 2178let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations. 2179let Uses = [RM] in { 2180let isCommutable = 1 in { 2181 defm FMADD : AForm_1r<63, 29, 2182 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2183 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2184 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 2185 defm FMADDS : AForm_1r<59, 29, 2186 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2187 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2188 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 2189 defm FMSUB : AForm_1r<63, 28, 2190 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2191 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2192 [(set f64:$FRT, 2193 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 2194 defm FMSUBS : AForm_1r<59, 28, 2195 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2196 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2197 [(set f32:$FRT, 2198 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 2199 defm FNMADD : AForm_1r<63, 31, 2200 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2201 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2202 [(set f64:$FRT, 2203 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 2204 defm FNMADDS : AForm_1r<59, 31, 2205 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2206 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2207 [(set f32:$FRT, 2208 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 2209 defm FNMSUB : AForm_1r<63, 30, 2210 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2211 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2212 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC, 2213 (fneg f64:$FRB))))]>; 2214 defm FNMSUBS : AForm_1r<59, 30, 2215 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2216 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2217 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC, 2218 (fneg f32:$FRB))))]>; 2219} // isCommutable 2220} 2221// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 2222// having 4 of these, force the comparison to always be an 8-byte double (code 2223// should use an FMRSD if the input comparison value really wants to be a float) 2224// and 4/8 byte forms for the result and operand type.. 2225let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2226defm FSELD : AForm_1r<63, 23, 2227 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2228 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2229 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 2230defm FSELS : AForm_1r<63, 23, 2231 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2232 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2233 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 2234let Uses = [RM] in { 2235 let isCommutable = 1 in { 2236 defm FADD : AForm_2r<63, 21, 2237 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2238 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 2239 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>; 2240 defm FADDS : AForm_2r<59, 21, 2241 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2242 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 2243 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>; 2244 } // isCommutable 2245 defm FDIV : AForm_2r<63, 18, 2246 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2247 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 2248 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>; 2249 defm FDIVS : AForm_2r<59, 18, 2250 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2251 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 2252 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>; 2253 let isCommutable = 1 in { 2254 defm FMUL : AForm_3r<63, 25, 2255 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 2256 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 2257 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>; 2258 defm FMULS : AForm_3r<59, 25, 2259 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 2260 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 2261 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>; 2262 } // isCommutable 2263 defm FSUB : AForm_2r<63, 20, 2264 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2265 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 2266 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>; 2267 defm FSUBS : AForm_2r<59, 20, 2268 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2269 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 2270 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>; 2271 } 2272} 2273 2274let neverHasSideEffects = 1 in { 2275let PPC970_Unit = 1 in { // FXU Operations. 2276 let isSelect = 1 in 2277 def ISEL : AForm_4<31, 15, 2278 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), 2279 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral, 2280 []>; 2281} 2282 2283let PPC970_Unit = 1 in { // FXU Operations. 2284// M-Form instructions. rotate and mask instructions. 2285// 2286let isCommutable = 1 in { 2287// RLWIMI can be commuted if the rotate amount is zero. 2288defm RLWIMI : MForm_2r<20, (outs gprc:$rA), 2289 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, 2290 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 2291 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 2292 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 2293} 2294let BaseName = "rlwinm" in { 2295def RLWINM : MForm_2<21, 2296 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2297 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 2298 []>, RecFormRel; 2299let Defs = [CR0] in 2300def RLWINMo : MForm_2<21, 2301 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2302 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 2303 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked; 2304} 2305defm RLWNM : MForm_2r<23, (outs gprc:$rA), 2306 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), 2307 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 2308 []>; 2309} 2310} // neverHasSideEffects = 1 2311 2312//===----------------------------------------------------------------------===// 2313// PowerPC Instruction Patterns 2314// 2315 2316// Arbitrary immediate support. Implement in terms of LIS/ORI. 2317def : Pat<(i32 imm:$imm), 2318 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 2319 2320// Implement the 'not' operation with the NOR instruction. 2321def i32not : OutPatFrag<(ops node:$in), 2322 (NOR $in, $in)>; 2323def : Pat<(not i32:$in), 2324 (i32not $in)>; 2325 2326// ADD an arbitrary immediate. 2327def : Pat<(add i32:$in, imm:$imm), 2328 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 2329// OR an arbitrary immediate. 2330def : Pat<(or i32:$in, imm:$imm), 2331 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2332// XOR an arbitrary immediate. 2333def : Pat<(xor i32:$in, imm:$imm), 2334 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2335// SUBFIC 2336def : Pat<(sub imm32SExt16:$imm, i32:$in), 2337 (SUBFIC $in, imm:$imm)>; 2338 2339// SHL/SRL 2340def : Pat<(shl i32:$in, (i32 imm:$imm)), 2341 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 2342def : Pat<(srl i32:$in, (i32 imm:$imm)), 2343 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 2344 2345// ROTL 2346def : Pat<(rotl i32:$in, i32:$sh), 2347 (RLWNM $in, $sh, 0, 31)>; 2348def : Pat<(rotl i32:$in, (i32 imm:$imm)), 2349 (RLWINM $in, imm:$imm, 0, 31)>; 2350 2351// RLWNM 2352def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 2353 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 2354 2355// Calls 2356def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 2357 (BL tglobaladdr:$dst)>; 2358def : Pat<(PPCcall (i32 texternalsym:$dst)), 2359 (BL texternalsym:$dst)>; 2360 2361 2362def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 2363 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 2364 2365def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 2366 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 2367 2368def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 2369 (TCRETURNri CTRRC:$dst, imm:$imm)>; 2370 2371 2372 2373// Hi and Lo for Darwin Global Addresses. 2374def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 2375def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 2376def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 2377def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 2378def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 2379def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 2380def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 2381def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 2382def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 2383 (ADDIS $in, tglobaltlsaddr:$g)>; 2384def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 2385 (ADDI $in, tglobaltlsaddr:$g)>; 2386def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 2387 (ADDIS $in, tglobaladdr:$g)>; 2388def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 2389 (ADDIS $in, tconstpool:$g)>; 2390def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 2391 (ADDIS $in, tjumptable:$g)>; 2392def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 2393 (ADDIS $in, tblockaddress:$g)>; 2394 2395// Support for thread-local storage. 2396def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 2397 [(set i32:$rD, (PPCppc32GOT))]>; 2398 2399def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 2400 "#LDgotTprelL32", 2401 [(set i32:$rD, 2402 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 2403def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 2404 (ADD4TLS $in, tglobaltlsaddr:$g)>; 2405 2406// Standard shifts. These are represented separately from the real shifts above 2407// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 2408// amounts. 2409def : Pat<(sra i32:$rS, i32:$rB), 2410 (SRAW $rS, $rB)>; 2411def : Pat<(srl i32:$rS, i32:$rB), 2412 (SRW $rS, $rB)>; 2413def : Pat<(shl i32:$rS, i32:$rB), 2414 (SLW $rS, $rB)>; 2415 2416def : Pat<(zextloadi1 iaddr:$src), 2417 (LBZ iaddr:$src)>; 2418def : Pat<(zextloadi1 xaddr:$src), 2419 (LBZX xaddr:$src)>; 2420def : Pat<(extloadi1 iaddr:$src), 2421 (LBZ iaddr:$src)>; 2422def : Pat<(extloadi1 xaddr:$src), 2423 (LBZX xaddr:$src)>; 2424def : Pat<(extloadi8 iaddr:$src), 2425 (LBZ iaddr:$src)>; 2426def : Pat<(extloadi8 xaddr:$src), 2427 (LBZX xaddr:$src)>; 2428def : Pat<(extloadi16 iaddr:$src), 2429 (LHZ iaddr:$src)>; 2430def : Pat<(extloadi16 xaddr:$src), 2431 (LHZX xaddr:$src)>; 2432def : Pat<(f64 (extloadf32 iaddr:$src)), 2433 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 2434def : Pat<(f64 (extloadf32 xaddr:$src)), 2435 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 2436 2437def : Pat<(f64 (fextend f32:$src)), 2438 (COPY_TO_REGCLASS $src, F8RC)>; 2439 2440def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>; 2441def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>; 2442 2443// Additional FNMSUB patterns: -a*c + b == -(a*c - b) 2444def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B), 2445 (FNMSUB $A, $C, $B)>; 2446def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B), 2447 (FNMSUB $A, $C, $B)>; 2448def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B), 2449 (FNMSUBS $A, $C, $B)>; 2450def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B), 2451 (FNMSUBS $A, $C, $B)>; 2452 2453// FCOPYSIGN's operand types need not agree. 2454def : Pat<(fcopysign f64:$frB, f32:$frA), 2455 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 2456def : Pat<(fcopysign f32:$frB, f64:$frA), 2457 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 2458 2459include "PPCInstrAltivec.td" 2460include "PPCInstr64Bit.td" 2461include "PPCInstrVSX.td" 2462 2463def crnot : OutPatFrag<(ops node:$in), 2464 (CRNOR $in, $in)>; 2465def : Pat<(not i1:$in), 2466 (crnot $in)>; 2467 2468// Patterns for arithmetic i1 operations. 2469def : Pat<(add i1:$a, i1:$b), 2470 (CRXOR $a, $b)>; 2471def : Pat<(sub i1:$a, i1:$b), 2472 (CRXOR $a, $b)>; 2473def : Pat<(mul i1:$a, i1:$b), 2474 (CRAND $a, $b)>; 2475 2476// We're sometimes asked to materialize i1 -1, which is just 1 in this case 2477// (-1 is used to mean all bits set). 2478def : Pat<(i1 -1), (CRSET)>; 2479 2480// i1 extensions, implemented in terms of isel. 2481def : Pat<(i32 (zext i1:$in)), 2482 (SELECT_I4 $in, (LI 1), (LI 0))>; 2483def : Pat<(i32 (sext i1:$in)), 2484 (SELECT_I4 $in, (LI -1), (LI 0))>; 2485 2486def : Pat<(i64 (zext i1:$in)), 2487 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 2488def : Pat<(i64 (sext i1:$in)), 2489 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 2490 2491// FIXME: We should choose either a zext or a sext based on other constants 2492// already around. 2493def : Pat<(i32 (anyext i1:$in)), 2494 (SELECT_I4 $in, (LI 1), (LI 0))>; 2495def : Pat<(i64 (anyext i1:$in)), 2496 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 2497 2498// match setcc on i1 variables. 2499def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 2500 (CRANDC $s2, $s1)>; 2501def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 2502 (CRANDC $s2, $s1)>; 2503def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 2504 (CRORC $s2, $s1)>; 2505def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 2506 (CRORC $s2, $s1)>; 2507def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 2508 (CREQV $s1, $s2)>; 2509def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 2510 (CRORC $s1, $s2)>; 2511def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 2512 (CRORC $s1, $s2)>; 2513def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 2514 (CRANDC $s1, $s2)>; 2515def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 2516 (CRANDC $s1, $s2)>; 2517def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 2518 (CRXOR $s1, $s2)>; 2519 2520// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 2521// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 2522// floating-point types. 2523 2524multiclass CRNotPat<dag pattern, dag result> { 2525 def : Pat<pattern, (crnot result)>; 2526 def : Pat<(not pattern), result>; 2527 2528 // We can also fold the crnot into an extension: 2529 def : Pat<(i32 (zext pattern)), 2530 (SELECT_I4 result, (LI 0), (LI 1))>; 2531 def : Pat<(i32 (sext pattern)), 2532 (SELECT_I4 result, (LI 0), (LI -1))>; 2533 2534 // We can also fold the crnot into an extension: 2535 def : Pat<(i64 (zext pattern)), 2536 (SELECT_I8 result, (LI8 0), (LI8 1))>; 2537 def : Pat<(i64 (sext pattern)), 2538 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 2539 2540 // FIXME: We should choose either a zext or a sext based on other constants 2541 // already around. 2542 def : Pat<(i32 (anyext pattern)), 2543 (SELECT_I4 result, (LI 0), (LI 1))>; 2544 2545 def : Pat<(i64 (anyext pattern)), 2546 (SELECT_I8 result, (LI8 0), (LI8 1))>; 2547} 2548 2549// FIXME: Because of what seems like a bug in TableGen's type-inference code, 2550// we need to write imm:$imm in the output patterns below, not just $imm, or 2551// else the resulting matcher will not correctly add the immediate operand 2552// (making it a register operand instead). 2553 2554// extended SETCC. 2555multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 2556 OutPatFrag rfrag, OutPatFrag rfrag8> { 2557 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 2558 (rfrag $s1)>; 2559 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 2560 (rfrag8 $s1)>; 2561 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 2562 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 2563 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 2564 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 2565 2566 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 2567 (rfrag $s1)>; 2568 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 2569 (rfrag8 $s1)>; 2570 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 2571 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 2572 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 2573 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 2574} 2575 2576// Note that we do all inversions below with i(32|64)not, instead of using 2577// (xori x, 1) because on the A2 nor has single-cycle latency while xori 2578// has 2-cycle latency. 2579 2580defm : ExtSetCCPat<SETEQ, 2581 PatFrag<(ops node:$in, node:$cc), 2582 (setcc $in, 0, $cc)>, 2583 OutPatFrag<(ops node:$in), 2584 (RLWINM (CNTLZW $in), 27, 31, 31)>, 2585 OutPatFrag<(ops node:$in), 2586 (RLDICL (CNTLZD $in), 58, 63)> >; 2587 2588defm : ExtSetCCPat<SETNE, 2589 PatFrag<(ops node:$in, node:$cc), 2590 (setcc $in, 0, $cc)>, 2591 OutPatFrag<(ops node:$in), 2592 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 2593 OutPatFrag<(ops node:$in), 2594 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 2595 2596defm : ExtSetCCPat<SETLT, 2597 PatFrag<(ops node:$in, node:$cc), 2598 (setcc $in, 0, $cc)>, 2599 OutPatFrag<(ops node:$in), 2600 (RLWINM $in, 1, 31, 31)>, 2601 OutPatFrag<(ops node:$in), 2602 (RLDICL $in, 1, 63)> >; 2603 2604defm : ExtSetCCPat<SETGE, 2605 PatFrag<(ops node:$in, node:$cc), 2606 (setcc $in, 0, $cc)>, 2607 OutPatFrag<(ops node:$in), 2608 (RLWINM (i32not $in), 1, 31, 31)>, 2609 OutPatFrag<(ops node:$in), 2610 (RLDICL (i64not $in), 1, 63)> >; 2611 2612defm : ExtSetCCPat<SETGT, 2613 PatFrag<(ops node:$in, node:$cc), 2614 (setcc $in, 0, $cc)>, 2615 OutPatFrag<(ops node:$in), 2616 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 2617 OutPatFrag<(ops node:$in), 2618 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 2619 2620defm : ExtSetCCPat<SETLE, 2621 PatFrag<(ops node:$in, node:$cc), 2622 (setcc $in, 0, $cc)>, 2623 OutPatFrag<(ops node:$in), 2624 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 2625 OutPatFrag<(ops node:$in), 2626 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 2627 2628defm : ExtSetCCPat<SETLT, 2629 PatFrag<(ops node:$in, node:$cc), 2630 (setcc $in, -1, $cc)>, 2631 OutPatFrag<(ops node:$in), 2632 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 2633 OutPatFrag<(ops node:$in), 2634 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 2635 2636defm : ExtSetCCPat<SETGE, 2637 PatFrag<(ops node:$in, node:$cc), 2638 (setcc $in, -1, $cc)>, 2639 OutPatFrag<(ops node:$in), 2640 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 2641 OutPatFrag<(ops node:$in), 2642 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 2643 2644defm : ExtSetCCPat<SETGT, 2645 PatFrag<(ops node:$in, node:$cc), 2646 (setcc $in, -1, $cc)>, 2647 OutPatFrag<(ops node:$in), 2648 (RLWINM (i32not $in), 1, 31, 31)>, 2649 OutPatFrag<(ops node:$in), 2650 (RLDICL (i64not $in), 1, 63)> >; 2651 2652defm : ExtSetCCPat<SETLE, 2653 PatFrag<(ops node:$in, node:$cc), 2654 (setcc $in, -1, $cc)>, 2655 OutPatFrag<(ops node:$in), 2656 (RLWINM $in, 1, 31, 31)>, 2657 OutPatFrag<(ops node:$in), 2658 (RLDICL $in, 1, 63)> >; 2659 2660// SETCC for i32. 2661def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 2662 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 2663def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 2664 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 2665def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 2666 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 2667def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 2668 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 2669def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 2670 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 2671def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 2672 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 2673 2674// For non-equality comparisons, the default code would materialize the 2675// constant, then compare against it, like this: 2676// lis r2, 4660 2677// ori r2, r2, 22136 2678// cmpw cr0, r3, r2 2679// beq cr0,L6 2680// Since we are just comparing for equality, we can emit this instead: 2681// xoris r0,r3,0x1234 2682// cmplwi cr0,r0,0x5678 2683// beq cr0,L6 2684 2685def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 2686 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 2687 (LO16 imm:$imm)), sub_eq)>; 2688 2689defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 2690 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 2691defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 2692 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 2693defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 2694 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 2695defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 2696 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 2697defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 2698 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 2699defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 2700 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 2701 2702defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 2703 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 2704 (LO16 imm:$imm)), sub_eq)>; 2705 2706def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 2707 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 2708def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 2709 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 2710def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 2711 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 2712def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 2713 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 2714def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 2715 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 2716 2717defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 2718 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 2719defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 2720 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 2721defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 2722 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 2723defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 2724 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 2725defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 2726 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 2727 2728// SETCC for i64. 2729def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 2730 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 2731def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 2732 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 2733def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 2734 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 2735def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 2736 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 2737def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 2738 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 2739def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 2740 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 2741 2742// For non-equality comparisons, the default code would materialize the 2743// constant, then compare against it, like this: 2744// lis r2, 4660 2745// ori r2, r2, 22136 2746// cmpd cr0, r3, r2 2747// beq cr0,L6 2748// Since we are just comparing for equality, we can emit this instead: 2749// xoris r0,r3,0x1234 2750// cmpldi cr0,r0,0x5678 2751// beq cr0,L6 2752 2753def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 2754 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 2755 (LO16 imm:$imm)), sub_eq)>; 2756 2757defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 2758 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 2759defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 2760 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 2761defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 2762 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 2763defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 2764 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 2765defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 2766 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 2767defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 2768 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 2769 2770defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 2771 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 2772 (LO16 imm:$imm)), sub_eq)>; 2773 2774def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 2775 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 2776def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 2777 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 2778def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 2779 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 2780def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 2781 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 2782def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 2783 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 2784 2785defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 2786 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 2787defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 2788 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 2789defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 2790 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 2791defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 2792 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 2793defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 2794 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 2795 2796// SETCC for f32. 2797def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)), 2798 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 2799def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)), 2800 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 2801def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)), 2802 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 2803def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)), 2804 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 2805def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)), 2806 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 2807def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)), 2808 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 2809def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)), 2810 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 2811 2812defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)), 2813 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 2814defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)), 2815 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 2816defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)), 2817 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 2818defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)), 2819 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 2820defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)), 2821 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 2822defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)), 2823 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 2824defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)), 2825 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 2826 2827// SETCC for f64. 2828def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)), 2829 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 2830def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)), 2831 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 2832def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)), 2833 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 2834def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)), 2835 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 2836def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)), 2837 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 2838def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)), 2839 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 2840def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)), 2841 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 2842 2843defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)), 2844 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 2845defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)), 2846 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 2847defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)), 2848 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 2849defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)), 2850 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 2851defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)), 2852 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 2853defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)), 2854 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 2855defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)), 2856 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 2857 2858// match select on i1 variables: 2859def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 2860 (CROR (CRAND $cond , $tval), 2861 (CRAND (crnot $cond), $fval))>; 2862 2863// match selectcc on i1 variables: 2864// select (lhs == rhs), tval, fval is: 2865// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 2866def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 2867 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 2868 (CRAND (CRORC $lhs, $rhs), $fval))>; 2869def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 2870 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 2871 (CRAND (CRANDC $lhs, $rhs), $fval))>; 2872def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 2873 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 2874 (CRAND (CRXOR $lhs, $rhs), $fval))>; 2875def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 2876 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 2877 (CRAND (CRANDC $rhs, $lhs), $fval))>; 2878def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 2879 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 2880 (CRAND (CRORC $rhs, $lhs), $fval))>; 2881def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 2882 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 2883 (CRAND (CRXOR $lhs, $rhs), $tval))>; 2884 2885// match selectcc on i1 variables with non-i1 output. 2886def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 2887 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 2888def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 2889 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 2890def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 2891 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 2892def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 2893 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 2894def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 2895 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 2896def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 2897 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 2898 2899def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 2900 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 2901def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 2902 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 2903def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 2904 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 2905def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 2906 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 2907def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 2908 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 2909def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 2910 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 2911 2912def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 2913 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 2914def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 2915 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 2916def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 2917 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 2918def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 2919 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 2920def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 2921 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 2922def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 2923 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 2924 2925def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 2926 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 2927def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 2928 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 2929def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 2930 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 2931def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 2932 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 2933def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 2934 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 2935def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 2936 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 2937 2938def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 2939 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 2940def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 2941 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 2942def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 2943 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 2944def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 2945 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 2946def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 2947 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 2948def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 2949 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 2950 2951let usesCustomInserter = 1 in { 2952def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in), 2953 "#ANDIo_1_EQ_BIT", 2954 [(set i1:$dst, (trunc (not i32:$in)))]>; 2955def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in), 2956 "#ANDIo_1_GT_BIT", 2957 [(set i1:$dst, (trunc i32:$in))]>; 2958 2959def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in), 2960 "#ANDIo_1_EQ_BIT8", 2961 [(set i1:$dst, (trunc (not i64:$in)))]>; 2962def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in), 2963 "#ANDIo_1_GT_BIT8", 2964 [(set i1:$dst, (trunc i64:$in))]>; 2965} 2966 2967def : Pat<(i1 (not (trunc i32:$in))), 2968 (ANDIo_1_EQ_BIT $in)>; 2969def : Pat<(i1 (not (trunc i64:$in))), 2970 (ANDIo_1_EQ_BIT8 $in)>; 2971 2972//===----------------------------------------------------------------------===// 2973// PowerPC Instructions used for assembler/disassembler only 2974// 2975 2976def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 2977 "isync", IIC_SprISYNC, []>; 2978 2979def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), 2980 "icbi $src", IIC_LdStICBI, []>; 2981 2982def EIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2983 "eieio", IIC_LdStLoad, []>; 2984 2985def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L), 2986 "wait $L", IIC_LdStLoad, []>; 2987 2988def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L), 2989 "mtmsr $RS, $L", IIC_SprMTMSR>; 2990 2991def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), 2992 "mfmsr $RT", IIC_SprMFMSR, []>; 2993 2994def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L), 2995 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 2996 2997def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 2998 "slbie $RB", IIC_SprSLBIE, []>; 2999 3000def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), 3001 "slbmte $RS, $RB", IIC_SprSLBMTE, []>; 3002 3003def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), 3004 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; 3005 3006def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 3007 3008def TLBSYNC : XForm_0<31, 566, (outs), (ins), 3009 "tlbsync", IIC_SprTLBSYNC, []>; 3010 3011def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 3012 "tlbiel $RB", IIC_SprTLBIEL, []>; 3013 3014def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), 3015 "tlbie $RB,$RS", IIC_SprTLBIE, []>; 3016 3017//===----------------------------------------------------------------------===// 3018// PowerPC Assembler Instruction Aliases 3019// 3020 3021// Pseudo-instructions for alternate assembly syntax (never used by codegen). 3022// These are aliases that require C++ handling to convert to the target 3023// instruction, while InstAliases can be handled directly by tblgen. 3024class PPCAsmPseudo<string asm, dag iops> 3025 : Instruction { 3026 let Namespace = "PPC"; 3027 bit PPC64 = 0; // Default value, override with isPPC64 3028 3029 let OutOperandList = (outs); 3030 let InOperandList = iops; 3031 let Pattern = []; 3032 let AsmString = asm; 3033 let isAsmParserOnly = 1; 3034 let isPseudo = 1; 3035} 3036 3037def : InstAlias<"sc", (SC 0)>; 3038 3039def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>; 3040def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>; 3041def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>; 3042def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>; 3043 3044def : InstAlias<"wait", (WAIT 0)>; 3045def : InstAlias<"waitrsv", (WAIT 1)>; 3046def : InstAlias<"waitimpl", (WAIT 2)>; 3047 3048def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 3049def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 3050def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 3051def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 3052 3053def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 3054def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 3055 3056def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 3057def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 3058 3059def : InstAlias<"xnop", (XORI R0, R0, 0)>; 3060 3061def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3062def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3063 3064def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3065def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3066 3067def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 3068 3069def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 3070 3071def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 3072 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3073def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 3074 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3075def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 3076 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3077def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm", 3078 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3079 3080def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3081def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3082def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3083def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3084 3085def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 3086def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 3087 3088def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>; 3089def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>; 3090def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>; 3091def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>; 3092 3093def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>; 3094def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>; 3095def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>; 3096def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>; 3097 3098def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>; 3099def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>; 3100def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>; 3101def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>; 3102 3103def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>; 3104def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>; 3105def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>; 3106def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>; 3107 3108def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>; 3109 3110def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>; 3111def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>; 3112 3113def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 3114 3115def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>; 3116def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>; 3117 3118def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>; 3119def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>; 3120def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>; 3121def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>; 3122 3123def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 3124 3125def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 3126 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3127def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 3128 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3129def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 3130 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3131def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 3132 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3133def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 3134 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3135def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 3136 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3137def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 3138 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3139def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 3140 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3141def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 3142 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3143def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 3144 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3145def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 3146 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3147def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n", 3148 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3149def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 3150 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3151def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n", 3152 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3153def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 3154 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3155def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 3156 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3157def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 3158 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 3159def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 3160 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 3161 3162def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 3163def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 3164def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 3165def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 3166def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 3167def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 3168 3169def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 3170 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3171def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 3172 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3173def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 3174 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3175def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 3176 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3177def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 3178 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3179def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 3180 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3181def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 3182 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3183def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 3184 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3185def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 3186 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3187def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n", 3188 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3189def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 3190 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3191def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n", 3192 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3193def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 3194 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3195def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 3196 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3197def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 3198 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 3199def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 3200 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 3201 3202def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 3203def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 3204def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 3205def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 3206def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 3207def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 3208 3209// These generic branch instruction forms are used for the assembler parser only. 3210// Defs and Uses are conservative, since we don't know the BO value. 3211let PPC970_Unit = 7 in { 3212 let Defs = [CTR], Uses = [CTR, RM] in { 3213 def gBC : BForm_3<16, 0, 0, (outs), 3214 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 3215 "bc $bo, $bi, $dst">; 3216 def gBCA : BForm_3<16, 1, 0, (outs), 3217 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 3218 "bca $bo, $bi, $dst">; 3219 } 3220 let Defs = [LR, CTR], Uses = [CTR, RM] in { 3221 def gBCL : BForm_3<16, 0, 1, (outs), 3222 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 3223 "bcl $bo, $bi, $dst">; 3224 def gBCLA : BForm_3<16, 1, 1, (outs), 3225 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 3226 "bcla $bo, $bi, $dst">; 3227 } 3228 let Defs = [CTR], Uses = [CTR, LR, RM] in 3229 def gBCLR : XLForm_2<19, 16, 0, (outs), 3230 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 3231 "bclr $bo, $bi, $bh", IIC_BrB, []>; 3232 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 3233 def gBCLRL : XLForm_2<19, 16, 1, (outs), 3234 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 3235 "bclrl $bo, $bi, $bh", IIC_BrB, []>; 3236 let Defs = [CTR], Uses = [CTR, LR, RM] in 3237 def gBCCTR : XLForm_2<19, 528, 0, (outs), 3238 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 3239 "bcctr $bo, $bi, $bh", IIC_BrB, []>; 3240 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 3241 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 3242 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 3243 "bcctrl $bo, $bi, $bh", IIC_BrB, []>; 3244} 3245def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 3246def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 3247def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 3248def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 3249 3250multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 3251 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 3252 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 3253 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 3254 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 3255 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 3256 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 3257} 3258multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 3259 : BranchSimpleMnemonic1<name, pm, bo> { 3260 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 3261 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 3262} 3263defm : BranchSimpleMnemonic2<"t", "", 12>; 3264defm : BranchSimpleMnemonic2<"f", "", 4>; 3265defm : BranchSimpleMnemonic2<"t", "-", 14>; 3266defm : BranchSimpleMnemonic2<"f", "-", 6>; 3267defm : BranchSimpleMnemonic2<"t", "+", 15>; 3268defm : BranchSimpleMnemonic2<"f", "+", 7>; 3269defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 3270defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 3271defm : BranchSimpleMnemonic1<"dzt", "", 10>; 3272defm : BranchSimpleMnemonic1<"dzf", "", 2>; 3273 3274multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 3275 def : InstAlias<"b"#name#pm#" $cc, $dst", 3276 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 3277 def : InstAlias<"b"#name#pm#" $dst", 3278 (BCC bibo, CR0, condbrtarget:$dst)>; 3279 3280 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 3281 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 3282 def : InstAlias<"b"#name#"a"#pm#" $dst", 3283 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 3284 3285 def : InstAlias<"b"#name#"lr"#pm#" $cc", 3286 (BCCLR bibo, crrc:$cc)>; 3287 def : InstAlias<"b"#name#"lr"#pm, 3288 (BCCLR bibo, CR0)>; 3289 3290 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 3291 (BCCCTR bibo, crrc:$cc)>; 3292 def : InstAlias<"b"#name#"ctr"#pm, 3293 (BCCCTR bibo, CR0)>; 3294 3295 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 3296 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 3297 def : InstAlias<"b"#name#"l"#pm#" $dst", 3298 (BCCL bibo, CR0, condbrtarget:$dst)>; 3299 3300 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 3301 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 3302 def : InstAlias<"b"#name#"la"#pm#" $dst", 3303 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 3304 3305 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 3306 (BCCLRL bibo, crrc:$cc)>; 3307 def : InstAlias<"b"#name#"lrl"#pm, 3308 (BCCLRL bibo, CR0)>; 3309 3310 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 3311 (BCCCTRL bibo, crrc:$cc)>; 3312 def : InstAlias<"b"#name#"ctrl"#pm, 3313 (BCCCTRL bibo, CR0)>; 3314} 3315multiclass BranchExtendedMnemonic<string name, int bibo> { 3316 defm : BranchExtendedMnemonicPM<name, "", bibo>; 3317 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 3318 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 3319} 3320defm : BranchExtendedMnemonic<"lt", 12>; 3321defm : BranchExtendedMnemonic<"gt", 44>; 3322defm : BranchExtendedMnemonic<"eq", 76>; 3323defm : BranchExtendedMnemonic<"un", 108>; 3324defm : BranchExtendedMnemonic<"so", 108>; 3325defm : BranchExtendedMnemonic<"ge", 4>; 3326defm : BranchExtendedMnemonic<"nl", 4>; 3327defm : BranchExtendedMnemonic<"le", 36>; 3328defm : BranchExtendedMnemonic<"ng", 36>; 3329defm : BranchExtendedMnemonic<"ne", 68>; 3330defm : BranchExtendedMnemonic<"nu", 100>; 3331defm : BranchExtendedMnemonic<"ns", 100>; 3332 3333def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 3334def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 3335def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 3336def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 3337def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 3338def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 3339def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 3340def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 3341 3342def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 3343def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 3344def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 3345def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 3346def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 3347def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 3348def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 3349def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 3350 3351multiclass TrapExtendedMnemonic<string name, int to> { 3352 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 3353 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 3354 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 3355 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 3356} 3357defm : TrapExtendedMnemonic<"lt", 16>; 3358defm : TrapExtendedMnemonic<"le", 20>; 3359defm : TrapExtendedMnemonic<"eq", 4>; 3360defm : TrapExtendedMnemonic<"ge", 12>; 3361defm : TrapExtendedMnemonic<"gt", 8>; 3362defm : TrapExtendedMnemonic<"nl", 12>; 3363defm : TrapExtendedMnemonic<"ne", 24>; 3364defm : TrapExtendedMnemonic<"ng", 20>; 3365defm : TrapExtendedMnemonic<"llt", 2>; 3366defm : TrapExtendedMnemonic<"lle", 6>; 3367defm : TrapExtendedMnemonic<"lge", 5>; 3368defm : TrapExtendedMnemonic<"lgt", 1>; 3369defm : TrapExtendedMnemonic<"lnl", 5>; 3370defm : TrapExtendedMnemonic<"lng", 6>; 3371defm : TrapExtendedMnemonic<"u", 31>; 3372 3373