PPCInstrInfo.td revision dd41527a7dc6e2dacfad02ca8d4cbcb803b017da
1//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl 24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32> 25]>; 26def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 27def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 28 SDTCisVT<1, i32> ]>; 29def SDT_PPCvperm : SDTypeProfile<1, 3, [ 30 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 31]>; 32 33def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 34 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 35]>; 36 37def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 38 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 39]>; 40 41def SDT_PPClbrx : SDTypeProfile<1, 3, [ 42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> 43]>; 44def SDT_PPCstbrx : SDTypeProfile<0, 4, [ 45 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> 46]>; 47 48//===----------------------------------------------------------------------===// 49// PowerPC specific DAG Nodes. 50// 51 52def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 53def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 54def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 55def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 56 [SDNPHasChain, SDNPMayStore]>; 57 58// This sequence is used for long double->int conversions. It changes the 59// bits in the FPSCR which is not modelled. 60def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 61 [SDNPOutFlag]>; 62def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 63 [SDNPInFlag, SDNPOutFlag]>; 64def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 65 [SDNPInFlag, SDNPOutFlag]>; 66def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, 67 [SDNPInFlag, SDNPOutFlag]>; 68def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3, 69 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>, 70 SDTCisVT<3, f64>]>, 71 [SDNPInFlag]>; 72 73def PPCfsel : SDNode<"PPCISD::FSEL", 74 // Type constraint for fsel. 75 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 76 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 77 78def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 79def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 80def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 81def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 82 83def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 84 85// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 86// amounts. These nodes are generated by the multi-precision shift code. 87def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>; 88def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>; 89def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>; 90 91def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 92def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, 93 [SDNPHasChain, SDNPMayStore]>; 94 95// These are target-independent nodes, but have target-specific formats. 96def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 97 [SDNPHasChain, SDNPOutFlag]>; 98def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 99 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 100 101def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 102def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall, 103 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 104def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall, 105 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 106def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 107 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 108def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTRet, 109 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 110 111def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTRet, 112 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 113 114def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet, 115 [SDNPHasChain, SDNPOptInFlag]>; 116 117def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 118def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>; 119 120def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 121 [SDNPHasChain, SDNPOptInFlag]>; 122 123def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 124 [SDNPHasChain, SDNPMayLoad]>; 125def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 126 [SDNPHasChain, SDNPMayStore]>; 127 128// Instructions to support dynamic alloca. 129def SDTDynOp : SDTypeProfile<1, 2, []>; 130def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 131 132//===----------------------------------------------------------------------===// 133// PowerPC specific transformation functions and pattern fragments. 134// 135 136def SHL32 : SDNodeXForm<imm, [{ 137 // Transformation function: 31 - imm 138 return getI32Imm(31 - N->getValue()); 139}]>; 140 141def SRL32 : SDNodeXForm<imm, [{ 142 // Transformation function: 32 - imm 143 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0); 144}]>; 145 146def LO16 : SDNodeXForm<imm, [{ 147 // Transformation function: get the low 16 bits. 148 return getI32Imm((unsigned short)N->getValue()); 149}]>; 150 151def HI16 : SDNodeXForm<imm, [{ 152 // Transformation function: shift the immediate value down into the low bits. 153 return getI32Imm((unsigned)N->getValue() >> 16); 154}]>; 155 156def HA16 : SDNodeXForm<imm, [{ 157 // Transformation function: shift the immediate value down into the low bits. 158 signed int Val = N->getValue(); 159 return getI32Imm((Val - (signed short)Val) >> 16); 160}]>; 161def MB : SDNodeXForm<imm, [{ 162 // Transformation function: get the start bit of a mask 163 unsigned mb, me; 164 (void)isRunOfOnes((unsigned)N->getValue(), mb, me); 165 return getI32Imm(mb); 166}]>; 167 168def ME : SDNodeXForm<imm, [{ 169 // Transformation function: get the end bit of a mask 170 unsigned mb, me; 171 (void)isRunOfOnes((unsigned)N->getValue(), mb, me); 172 return getI32Imm(me); 173}]>; 174def maskimm32 : PatLeaf<(imm), [{ 175 // maskImm predicate - True if immediate is a run of ones. 176 unsigned mb, me; 177 if (N->getValueType(0) == MVT::i32) 178 return isRunOfOnes((unsigned)N->getValue(), mb, me); 179 else 180 return false; 181}]>; 182 183def immSExt16 : PatLeaf<(imm), [{ 184 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 185 // field. Used by instructions like 'addi'. 186 if (N->getValueType(0) == MVT::i32) 187 return (int32_t)N->getValue() == (short)N->getValue(); 188 else 189 return (int64_t)N->getValue() == (short)N->getValue(); 190}]>; 191def immZExt16 : PatLeaf<(imm), [{ 192 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 193 // field. Used by instructions like 'ori'. 194 return (uint64_t)N->getValue() == (unsigned short)N->getValue(); 195}], LO16>; 196 197// imm16Shifted* - These match immediates where the low 16-bits are zero. There 198// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 199// identical in 32-bit mode, but in 64-bit mode, they return true if the 200// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 201// clear). 202def imm16ShiftedZExt : PatLeaf<(imm), [{ 203 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 204 // immediate are set. Used by instructions like 'xoris'. 205 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0; 206}], HI16>; 207 208def imm16ShiftedSExt : PatLeaf<(imm), [{ 209 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 210 // immediate are set. Used by instructions like 'addis'. Identical to 211 // imm16ShiftedZExt in 32-bit mode. 212 if (N->getValue() & 0xFFFF) return false; 213 if (N->getValueType(0) == MVT::i32) 214 return true; 215 // For 64-bit, make sure it is sext right. 216 return N->getValue() == (uint64_t)(int)N->getValue(); 217}], HI16>; 218 219 220//===----------------------------------------------------------------------===// 221// PowerPC Flag Definitions. 222 223class isPPC64 { bit PPC64 = 1; } 224class isDOT { 225 list<Register> Defs = [CR0]; 226 bit RC = 1; 227} 228 229class RegConstraint<string C> { 230 string Constraints = C; 231} 232class NoEncode<string E> { 233 string DisableEncoding = E; 234} 235 236 237//===----------------------------------------------------------------------===// 238// PowerPC Operand Definitions. 239 240def s5imm : Operand<i32> { 241 let PrintMethod = "printS5ImmOperand"; 242} 243def u5imm : Operand<i32> { 244 let PrintMethod = "printU5ImmOperand"; 245} 246def u6imm : Operand<i32> { 247 let PrintMethod = "printU6ImmOperand"; 248} 249def s16imm : Operand<i32> { 250 let PrintMethod = "printS16ImmOperand"; 251} 252def u16imm : Operand<i32> { 253 let PrintMethod = "printU16ImmOperand"; 254} 255def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 256 let PrintMethod = "printS16X4ImmOperand"; 257} 258def target : Operand<OtherVT> { 259 let PrintMethod = "printBranchOperand"; 260} 261def calltarget : Operand<iPTR> { 262 let PrintMethod = "printCallOperand"; 263} 264def aaddr : Operand<iPTR> { 265 let PrintMethod = "printAbsAddrOperand"; 266} 267def piclabel: Operand<iPTR> { 268 let PrintMethod = "printPICLabel"; 269} 270def symbolHi: Operand<i32> { 271 let PrintMethod = "printSymbolHi"; 272} 273def symbolLo: Operand<i32> { 274 let PrintMethod = "printSymbolLo"; 275} 276def crbitm: Operand<i8> { 277 let PrintMethod = "printcrbitm"; 278} 279// Address operands 280def memri : Operand<iPTR> { 281 let PrintMethod = "printMemRegImm"; 282 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 283} 284def memrr : Operand<iPTR> { 285 let PrintMethod = "printMemRegReg"; 286 let MIOperandInfo = (ops ptr_rc, ptr_rc); 287} 288def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 289 let PrintMethod = "printMemRegImmShifted"; 290 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 291} 292 293// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg 294// that doesn't matter. 295def pred : PredicateOperand<OtherVT, (ops imm, CRRC), 296 (ops (i32 20), CR0)> { 297 let PrintMethod = "printPredicateOperand"; 298} 299 300// Define PowerPC specific addressing mode. 301def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 302def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 303def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 304def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 305 306/// This is just the offset part of iaddr, used for preinc. 307def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 308 309//===----------------------------------------------------------------------===// 310// PowerPC Instruction Predicate Definitions. 311def FPContractions : Predicate<"!NoExcessFPPrecision">; 312def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">; 313def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">; 314 315 316//===----------------------------------------------------------------------===// 317// PowerPC Instruction Definitions. 318 319// Pseudo-instructions: 320 321let hasCtrlDep = 1 in { 322let Defs = [R1], Uses = [R1] in { 323def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), 324 "${:comment} ADJCALLSTACKDOWN", 325 [(callseq_start imm:$amt)]>; 326def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 327 "${:comment} ADJCALLSTACKUP", 328 [(callseq_end imm:$amt1, imm:$amt2)]>; 329} 330 331def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), 332 "UPDATE_VRSAVE $rD, $rS", []>; 333} 334 335let Defs = [R1], Uses = [R1] in 336def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), 337 "${:comment} DYNALLOC $result, $negsize, $fpsi", 338 [(set GPRC:$result, 339 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>; 340 341let isImplicitDef = 1 in { 342def IMPLICIT_DEF_GPRC: Pseudo<(outs GPRC:$rD), (ins), 343 "${:comment}IMPLICIT_DEF_GPRC $rD", 344 [(set GPRC:$rD, (undef))]>; 345def IMPLICIT_DEF_F8 : Pseudo<(outs F8RC:$rD), (ins), 346 "${:comment} IMPLICIT_DEF_F8 $rD", 347 [(set F8RC:$rD, (undef))]>; 348def IMPLICIT_DEF_F4 : Pseudo<(outs F4RC:$rD), (ins), 349 "${:comment} IMPLICIT_DEF_F4 $rD", 350 [(set F4RC:$rD, (undef))]>; 351} 352 353// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 354// scheduler into a branch sequence. 355let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler. 356 PPC970_Single = 1 in { 357 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F, 358 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 359 []>; 360 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F, 361 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 362 []>; 363 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F, 364 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 365 []>; 366 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F, 367 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 368 []>; 369 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F, 370 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 371 []>; 372} 373 374let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 375 let isReturn = 1 in 376 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), 377 "b${p:cc}lr ${p:reg}", BrB, 378 [(retflag)]>; 379 let isBranch = 1, isIndirectBranch = 1 in 380 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; 381} 382 383 384 385let Defs = [LR] in 386 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>, 387 PPC970_Unit_BRU; 388 389let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 390 let isBarrier = 1 in { 391 def B : IForm<18, 0, 0, (outs), (ins target:$dst), 392 "b $dst", BrB, 393 [(br bb:$dst)]>; 394 } 395 396 // BCC represents an arbitrary conditional branch on a predicate. 397 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 398 // a two-value operand where a dag node expects two operands. :( 399 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst), 400 "b${cond:cc} ${cond:reg}, $dst" 401 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; 402} 403 404// Macho ABI Calls. 405let isCall = 1, PPC970_Unit = 7, 406 // All calls clobber the non-callee saved registers... 407 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 408 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 409 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 410 LR,CTR, 411 CR0,CR1,CR5,CR6,CR7] in { 412 // Convenient aliases for call instructions 413 def BL_Macho : IForm<18, 0, 1, 414 (outs), (ins calltarget:$func, variable_ops), 415 "bl $func", BrB, []>; // See Pat patterns below. 416 def BLA_Macho : IForm<18, 1, 1, 417 (outs), (ins aaddr:$func, variable_ops), 418 "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>; 419 def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1, 420 (outs), (ins variable_ops), 421 "bctrl", BrB, 422 [(PPCbctrl_Macho)]>, Requires<[In32BitMode]>; 423} 424 425// ELF ABI Calls. 426let isCall = 1, PPC970_Unit = 7, 427 // All calls clobber the non-callee saved registers... 428 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 429 F0,F1,F2,F3,F4,F5,F6,F7,F8, 430 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 431 LR,CTR, 432 CR0,CR1,CR5,CR6,CR7] in { 433 // Convenient aliases for call instructions 434 def BL_ELF : IForm<18, 0, 1, 435 (outs), (ins calltarget:$func, variable_ops), 436 "bl $func", BrB, []>; // See Pat patterns below. 437 def BLA_ELF : IForm<18, 1, 1, 438 (outs), (ins aaddr:$func, variable_ops), 439 "bla $func", BrB, 440 [(PPCcall_ELF (i32 imm:$func))]>; 441 def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 442 (outs), (ins variable_ops), 443 "bctrl", BrB, 444 [(PPCbctrl_ELF)]>, Requires<[In32BitMode]>; 445} 446 447// DCB* instructions. 448def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), 449 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 450 PPC970_DGroup_Single; 451def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), 452 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 453 PPC970_DGroup_Single; 454def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), 455 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 456 PPC970_DGroup_Single; 457def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), 458 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 459 PPC970_DGroup_Single; 460def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), 461 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 462 PPC970_DGroup_Single; 463def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), 464 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 465 PPC970_DGroup_Single; 466def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), 467 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 468 PPC970_DGroup_Single; 469def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), 470 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 471 PPC970_DGroup_Single; 472 473//===----------------------------------------------------------------------===// 474// PPC32 Load Instructions. 475// 476 477// Unindexed (r+i) Loads. 478let isSimpleLoad = 1, PPC970_Unit = 2 in { 479def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), 480 "lbz $rD, $src", LdStGeneral, 481 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 482def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), 483 "lha $rD, $src", LdStLHA, 484 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, 485 PPC970_DGroup_Cracked; 486def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src), 487 "lhz $rD, $src", LdStGeneral, 488 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; 489def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src), 490 "lwz $rD, $src", LdStGeneral, 491 [(set GPRC:$rD, (load iaddr:$src))]>; 492 493def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src), 494 "lfs $rD, $src", LdStLFDU, 495 [(set F4RC:$rD, (load iaddr:$src))]>; 496def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), 497 "lfd $rD, $src", LdStLFD, 498 [(set F8RC:$rD, (load iaddr:$src))]>; 499 500 501// Unindexed (r+i) Loads with Update (preinc). 502def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 503 "lbzu $rD, $addr", LdStGeneral, 504 []>, RegConstraint<"$addr.reg = $ea_result">, 505 NoEncode<"$ea_result">; 506 507def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 508 "lhau $rD, $addr", LdStGeneral, 509 []>, RegConstraint<"$addr.reg = $ea_result">, 510 NoEncode<"$ea_result">; 511 512def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 513 "lhzu $rD, $addr", LdStGeneral, 514 []>, RegConstraint<"$addr.reg = $ea_result">, 515 NoEncode<"$ea_result">; 516 517def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 518 "lwzu $rD, $addr", LdStGeneral, 519 []>, RegConstraint<"$addr.reg = $ea_result">, 520 NoEncode<"$ea_result">; 521 522def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 523 "lfs $rD, $addr", LdStLFDU, 524 []>, RegConstraint<"$addr.reg = $ea_result">, 525 NoEncode<"$ea_result">; 526 527def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 528 "lfd $rD, $addr", LdStLFD, 529 []>, RegConstraint<"$addr.reg = $ea_result">, 530 NoEncode<"$ea_result">; 531} 532 533// Indexed (r+r) Loads. 534// 535let isSimpleLoad = 1, PPC970_Unit = 2 in { 536def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), 537 "lbzx $rD, $src", LdStGeneral, 538 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; 539def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src), 540 "lhax $rD, $src", LdStLHA, 541 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, 542 PPC970_DGroup_Cracked; 543def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src), 544 "lhzx $rD, $src", LdStGeneral, 545 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; 546def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src), 547 "lwzx $rD, $src", LdStGeneral, 548 [(set GPRC:$rD, (load xaddr:$src))]>; 549 550 551def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src), 552 "lhbrx $rD, $src", LdStGeneral, 553 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>; 554def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src), 555 "lwbrx $rD, $src", LdStGeneral, 556 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>; 557 558def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src), 559 "lfsx $frD, $src", LdStLFDU, 560 [(set F4RC:$frD, (load xaddr:$src))]>; 561def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src), 562 "lfdx $frD, $src", LdStLFDU, 563 [(set F8RC:$frD, (load xaddr:$src))]>; 564} 565 566//===----------------------------------------------------------------------===// 567// PPC32 Store Instructions. 568// 569 570// Unindexed (r+i) Stores. 571let PPC970_Unit = 2 in { 572def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src), 573 "stb $rS, $src", LdStGeneral, 574 [(truncstorei8 GPRC:$rS, iaddr:$src)]>; 575def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src), 576 "sth $rS, $src", LdStGeneral, 577 [(truncstorei16 GPRC:$rS, iaddr:$src)]>; 578def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src), 579 "stw $rS, $src", LdStGeneral, 580 [(store GPRC:$rS, iaddr:$src)]>; 581def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst), 582 "stfs $rS, $dst", LdStUX, 583 [(store F4RC:$rS, iaddr:$dst)]>; 584def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst), 585 "stfd $rS, $dst", LdStUX, 586 [(store F8RC:$rS, iaddr:$dst)]>; 587} 588 589// Unindexed (r+i) Stores with Update (preinc). 590let PPC970_Unit = 2 in { 591def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 592 symbolLo:$ptroff, ptr_rc:$ptrreg), 593 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 594 [(set ptr_rc:$ea_res, 595 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, 596 iaddroff:$ptroff))]>, 597 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 598def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 599 symbolLo:$ptroff, ptr_rc:$ptrreg), 600 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 601 [(set ptr_rc:$ea_res, 602 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, 603 iaddroff:$ptroff))]>, 604 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 605def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 606 symbolLo:$ptroff, ptr_rc:$ptrreg), 607 "stwu $rS, $ptroff($ptrreg)", LdStGeneral, 608 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg, 609 iaddroff:$ptroff))]>, 610 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 611def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS, 612 symbolLo:$ptroff, ptr_rc:$ptrreg), 613 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral, 614 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg, 615 iaddroff:$ptroff))]>, 616 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 617def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS, 618 symbolLo:$ptroff, ptr_rc:$ptrreg), 619 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral, 620 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg, 621 iaddroff:$ptroff))]>, 622 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 623} 624 625 626// Indexed (r+r) Stores. 627// 628let PPC970_Unit = 2 in { 629def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst), 630 "stbx $rS, $dst", LdStGeneral, 631 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, 632 PPC970_DGroup_Cracked; 633def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst), 634 "sthx $rS, $dst", LdStGeneral, 635 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, 636 PPC970_DGroup_Cracked; 637def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst), 638 "stwx $rS, $dst", LdStGeneral, 639 [(store GPRC:$rS, xaddr:$dst)]>, 640 PPC970_DGroup_Cracked; 641 642let mayStore = 1 in { 643def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB), 644 "stwux $rS, $rA, $rB", LdStGeneral, 645 []>; 646} 647def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), 648 "sthbrx $rS, $dst", LdStGeneral, 649 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>, 650 PPC970_DGroup_Cracked; 651def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst), 652 "stwbrx $rS, $dst", LdStGeneral, 653 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>, 654 PPC970_DGroup_Cracked; 655 656def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), 657 "stfiwx $frS, $dst", LdStUX, 658 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 659 660def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), 661 "stfsx $frS, $dst", LdStUX, 662 [(store F4RC:$frS, xaddr:$dst)]>; 663def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst), 664 "stfdx $frS, $dst", LdStUX, 665 [(store F8RC:$frS, xaddr:$dst)]>; 666} 667 668 669//===----------------------------------------------------------------------===// 670// PPC32 Arithmetic Instructions. 671// 672 673let PPC970_Unit = 1 in { // FXU Operations. 674def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 675 "addi $rD, $rA, $imm", IntGeneral, 676 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 677def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 678 "addic $rD, $rA, $imm", IntGeneral, 679 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 680 PPC970_DGroup_Cracked; 681def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 682 "addic. $rD, $rA, $imm", IntGeneral, 683 []>; 684def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm), 685 "addis $rD, $rA, $imm", IntGeneral, 686 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; 687def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym), 688 "la $rD, $sym($rA)", IntGeneral, 689 [(set GPRC:$rD, (add GPRC:$rA, 690 (PPClo tglobaladdr:$sym, 0)))]>; 691def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 692 "mulli $rD, $rA, $imm", IntMulLI, 693 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 694def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 695 "subfic $rD, $rA, $imm", IntGeneral, 696 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 697 698let isReMaterializable = 1 in { 699 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), 700 "li $rD, $imm", IntGeneral, 701 [(set GPRC:$rD, immSExt16:$imm)]>; 702 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), 703 "lis $rD, $imm", IntGeneral, 704 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; 705} 706} 707 708let PPC970_Unit = 1 in { // FXU Operations. 709def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 710 "andi. $dst, $src1, $src2", IntGeneral, 711 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 712 isDOT; 713def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 714 "andis. $dst, $src1, $src2", IntGeneral, 715 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, 716 isDOT; 717def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 718 "ori $dst, $src1, $src2", IntGeneral, 719 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 720def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 721 "oris $dst, $src1, $src2", IntGeneral, 722 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; 723def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 724 "xori $dst, $src1, $src2", IntGeneral, 725 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 726def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 727 "xoris $dst, $src1, $src2", IntGeneral, 728 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; 729def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral, 730 []>; 731def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm), 732 "cmpwi $crD, $rA, $imm", IntCompare>; 733def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2), 734 "cmplwi $dst, $src1, $src2", IntCompare>; 735} 736 737 738let PPC970_Unit = 1 in { // FXU Operations. 739def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 740 "nand $rA, $rS, $rB", IntGeneral, 741 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 742def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 743 "and $rA, $rS, $rB", IntGeneral, 744 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 745def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 746 "andc $rA, $rS, $rB", IntGeneral, 747 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 748def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 749 "or $rA, $rS, $rB", IntGeneral, 750 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 751def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 752 "nor $rA, $rS, $rB", IntGeneral, 753 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 754def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 755 "orc $rA, $rS, $rB", IntGeneral, 756 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 757def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 758 "eqv $rA, $rS, $rB", IntGeneral, 759 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 760def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 761 "xor $rA, $rS, $rB", IntGeneral, 762 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 763def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 764 "slw $rA, $rS, $rB", IntGeneral, 765 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 766def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 767 "srw $rA, $rS, $rB", IntGeneral, 768 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 769def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 770 "sraw $rA, $rS, $rB", IntShift, 771 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 772} 773 774let PPC970_Unit = 1 in { // FXU Operations. 775def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH), 776 "srawi $rA, $rS, $SH", IntShift, 777 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 778def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS), 779 "cntlzw $rA, $rS", IntGeneral, 780 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 781def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS), 782 "extsb $rA, $rS", IntGeneral, 783 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 784def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS), 785 "extsh $rA, $rS", IntGeneral, 786 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 787 788def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 789 "cmpw $crD, $rA, $rB", IntCompare>; 790def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 791 "cmplw $crD, $rA, $rB", IntCompare>; 792} 793let PPC970_Unit = 3 in { // FPU Operations. 794//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 795// "fcmpo $crD, $fA, $fB", FPCompare>; 796def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB), 797 "fcmpu $crD, $fA, $fB", FPCompare>; 798def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB), 799 "fcmpu $crD, $fA, $fB", FPCompare>; 800 801def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB), 802 "fctiwz $frD, $frB", FPGeneral, 803 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 804def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB), 805 "frsp $frD, $frB", FPGeneral, 806 [(set F4RC:$frD, (fround F8RC:$frB))]>; 807def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB), 808 "fsqrt $frD, $frB", FPSqrt, 809 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 810def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB), 811 "fsqrts $frD, $frB", FPSqrt, 812 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 813} 814 815/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending. 816/// 817/// Note that these are defined as pseudo-ops on the PPC970 because they are 818/// often coalesced away and we don't want the dispatch group builder to think 819/// that they will fill slots (which could cause the load of a LSU reject to 820/// sneak into a d-group with a store). 821def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB), 822 "fmr $frD, $frB", FPGeneral, 823 []>, // (set F4RC:$frD, F4RC:$frB) 824 PPC970_Unit_Pseudo; 825def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB), 826 "fmr $frD, $frB", FPGeneral, 827 []>, // (set F8RC:$frD, F8RC:$frB) 828 PPC970_Unit_Pseudo; 829def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB), 830 "fmr $frD, $frB", FPGeneral, 831 [(set F8RC:$frD, (fextend F4RC:$frB))]>, 832 PPC970_Unit_Pseudo; 833 834let PPC970_Unit = 3 in { // FPU Operations. 835// These are artificially split into two different forms, for 4/8 byte FP. 836def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB), 837 "fabs $frD, $frB", FPGeneral, 838 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 839def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB), 840 "fabs $frD, $frB", FPGeneral, 841 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 842def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB), 843 "fnabs $frD, $frB", FPGeneral, 844 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 845def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB), 846 "fnabs $frD, $frB", FPGeneral, 847 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 848def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB), 849 "fneg $frD, $frB", FPGeneral, 850 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 851def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB), 852 "fneg $frD, $frB", FPGeneral, 853 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 854} 855 856 857// XL-Form instructions. condition register logical ops. 858// 859def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA), 860 "mcrf $BF, $BFA", BrMCR>, 861 PPC970_DGroup_First, PPC970_Unit_CRU; 862 863def CREQV : XLForm_1<19, 289, (outs CRRC:$CRD), (ins CRRC:$CRA, CRRC:$CRB), 864 "creqv $CRD, $CRA, $CRB", BrCR, 865 []>; 866 867def SETCR : XLForm_1_ext<19, 289, (outs CRRC:$dst), (ins), 868 "creqv $dst, $dst, $dst", BrCR, 869 []>; 870 871// XFX-Form instructions. Instructions that deal with SPRs. 872// 873def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins), 874 "mfctr $rT", SprMFSPR>, 875 PPC970_DGroup_First, PPC970_Unit_FXU; 876let Pattern = [(PPCmtctr GPRC:$rS)] in { 877def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS), 878 "mtctr $rS", SprMTSPR>, 879 PPC970_DGroup_First, PPC970_Unit_FXU; 880} 881 882def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS), 883 "mtlr $rS", SprMTSPR>, 884 PPC970_DGroup_First, PPC970_Unit_FXU; 885def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins), 886 "mflr $rT", SprMFSPR>, 887 PPC970_DGroup_First, PPC970_Unit_FXU; 888 889// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 890// a GPR on the PPC970. As such, copies in and out have the same performance 891// characteristics as an OR instruction. 892def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS), 893 "mtspr 256, $rS", IntGeneral>, 894 PPC970_DGroup_Single, PPC970_Unit_FXU; 895def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins), 896 "mfspr $rT, 256", IntGeneral>, 897 PPC970_DGroup_First, PPC970_Unit_FXU; 898 899def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS), 900 "mtcrf $FXM, $rS", BrMCRX>, 901 PPC970_MicroCode, PPC970_Unit_CRU; 902def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>, 903 PPC970_MicroCode, PPC970_Unit_CRU; 904def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 905 "mfcr $rT, $FXM", SprMFCR>, 906 PPC970_DGroup_First, PPC970_Unit_CRU; 907 908// Instructions to manipulate FPSCR. Only long double handling uses these. 909// FPSCR is not modelled; we use the SDNode Flag to keep things in order. 910 911def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins), 912 "mffs $rT", IntMFFS, 913 [(set F8RC:$rT, (PPCmffs))]>, 914 PPC970_DGroup_Single, PPC970_Unit_FPU; 915def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 916 "mtfsb0 $FM", IntMTFSB0, 917 [(PPCmtfsb0 (i32 imm:$FM))]>, 918 PPC970_DGroup_Single, PPC970_Unit_FPU; 919def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 920 "mtfsb1 $FM", IntMTFSB0, 921 [(PPCmtfsb1 (i32 imm:$FM))]>, 922 PPC970_DGroup_Single, PPC970_Unit_FPU; 923def FADDrtz: AForm_2<63, 21, 924 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 925 "fadd $FRT, $FRA, $FRB", FPGeneral, 926 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>, 927 PPC970_DGroup_Single, PPC970_Unit_FPU; 928// MTFSF does not actually produce an FP result. We pretend it copies 929// input reg B to the output. If we didn't do this it would look like the 930// instruction had no outputs (because we aren't modelling the FPSCR) and 931// it would be deleted. 932def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA), 933 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB), 934 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0, 935 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM), 936 F8RC:$rT, F8RC:$FRB))]>, 937 PPC970_DGroup_Single, PPC970_Unit_FPU; 938 939let PPC970_Unit = 1 in { // FXU Operations. 940 941// XO-Form instructions. Arithmetic instructions that can set overflow bit 942// 943def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 944 "add $rT, $rA, $rB", IntGeneral, 945 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 946def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 947 "addc $rT, $rA, $rB", IntGeneral, 948 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 949 PPC970_DGroup_Cracked; 950def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 951 "adde $rT, $rA, $rB", IntGeneral, 952 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 953def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 954 "divw $rT, $rA, $rB", IntDivW, 955 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 956 PPC970_DGroup_First, PPC970_DGroup_Cracked; 957def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 958 "divwu $rT, $rA, $rB", IntDivW, 959 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 960 PPC970_DGroup_First, PPC970_DGroup_Cracked; 961def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 962 "mulhw $rT, $rA, $rB", IntMulHW, 963 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 964def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 965 "mulhwu $rT, $rA, $rB", IntMulHWU, 966 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 967def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 968 "mullw $rT, $rA, $rB", IntMulHW, 969 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 970def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 971 "subf $rT, $rA, $rB", IntGeneral, 972 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 973def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 974 "subfc $rT, $rA, $rB", IntGeneral, 975 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 976 PPC970_DGroup_Cracked; 977def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 978 "subfe $rT, $rA, $rB", IntGeneral, 979 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 980def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA), 981 "addme $rT, $rA", IntGeneral, 982 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>; 983def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA), 984 "addze $rT, $rA", IntGeneral, 985 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 986def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA), 987 "neg $rT, $rA", IntGeneral, 988 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 989def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA), 990 "subfme $rT, $rA", IntGeneral, 991 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>; 992def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA), 993 "subfze $rT, $rA", IntGeneral, 994 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 995} 996 997// A-Form instructions. Most of the instructions executed in the FPU are of 998// this type. 999// 1000let PPC970_Unit = 3 in { // FPU Operations. 1001def FMADD : AForm_1<63, 29, 1002 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1003 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1004 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), 1005 F8RC:$FRB))]>, 1006 Requires<[FPContractions]>; 1007def FMADDS : AForm_1<59, 29, 1008 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1009 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1010 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), 1011 F4RC:$FRB))]>, 1012 Requires<[FPContractions]>; 1013def FMSUB : AForm_1<63, 28, 1014 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1015 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1016 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), 1017 F8RC:$FRB))]>, 1018 Requires<[FPContractions]>; 1019def FMSUBS : AForm_1<59, 28, 1020 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1021 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1022 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), 1023 F4RC:$FRB))]>, 1024 Requires<[FPContractions]>; 1025def FNMADD : AForm_1<63, 31, 1026 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1027 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1028 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), 1029 F8RC:$FRB)))]>, 1030 Requires<[FPContractions]>; 1031def FNMADDS : AForm_1<59, 31, 1032 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1033 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1034 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), 1035 F4RC:$FRB)))]>, 1036 Requires<[FPContractions]>; 1037def FNMSUB : AForm_1<63, 30, 1038 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1039 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1040 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), 1041 F8RC:$FRB)))]>, 1042 Requires<[FPContractions]>; 1043def FNMSUBS : AForm_1<59, 30, 1044 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1045 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1046 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), 1047 F4RC:$FRB)))]>, 1048 Requires<[FPContractions]>; 1049// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 1050// having 4 of these, force the comparison to always be an 8-byte double (code 1051// should use an FMRSD if the input comparison value really wants to be a float) 1052// and 4/8 byte forms for the result and operand type.. 1053def FSELD : AForm_1<63, 23, 1054 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1055 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1056 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 1057def FSELS : AForm_1<63, 23, 1058 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1059 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1060 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 1061def FADD : AForm_2<63, 21, 1062 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1063 "fadd $FRT, $FRA, $FRB", FPGeneral, 1064 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 1065def FADDS : AForm_2<59, 21, 1066 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1067 "fadds $FRT, $FRA, $FRB", FPGeneral, 1068 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 1069def FDIV : AForm_2<63, 18, 1070 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1071 "fdiv $FRT, $FRA, $FRB", FPDivD, 1072 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 1073def FDIVS : AForm_2<59, 18, 1074 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1075 "fdivs $FRT, $FRA, $FRB", FPDivS, 1076 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 1077def FMUL : AForm_3<63, 25, 1078 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1079 "fmul $FRT, $FRA, $FRB", FPFused, 1080 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 1081def FMULS : AForm_3<59, 25, 1082 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1083 "fmuls $FRT, $FRA, $FRB", FPGeneral, 1084 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 1085def FSUB : AForm_2<63, 20, 1086 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1087 "fsub $FRT, $FRA, $FRB", FPGeneral, 1088 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 1089def FSUBS : AForm_2<59, 20, 1090 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1091 "fsubs $FRT, $FRA, $FRB", FPGeneral, 1092 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 1093} 1094 1095let PPC970_Unit = 1 in { // FXU Operations. 1096// M-Form instructions. rotate and mask instructions. 1097// 1098let isCommutable = 1 in { 1099// RLWIMI can be commuted if the rotate amount is zero. 1100def RLWIMI : MForm_2<20, 1101 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 1102 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 1103 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 1104 NoEncode<"$rSi">; 1105} 1106def RLWINM : MForm_2<21, 1107 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1108 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 1109 []>; 1110def RLWINMo : MForm_2<21, 1111 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1112 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 1113 []>, isDOT, PPC970_DGroup_Cracked; 1114def RLWNM : MForm_2<23, 1115 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 1116 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 1117 []>; 1118} 1119 1120 1121//===----------------------------------------------------------------------===// 1122// DWARF Pseudo Instructions 1123// 1124 1125def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), 1126 "${:comment} .loc $file, $line, $col", 1127 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), 1128 (i32 imm:$file))]>; 1129 1130//===----------------------------------------------------------------------===// 1131// PowerPC Instruction Patterns 1132// 1133 1134// Arbitrary immediate support. Implement in terms of LIS/ORI. 1135def : Pat<(i32 imm:$imm), 1136 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1137 1138// Implement the 'not' operation with the NOR instruction. 1139def NOT : Pat<(not GPRC:$in), 1140 (NOR GPRC:$in, GPRC:$in)>; 1141 1142// ADD an arbitrary immediate. 1143def : Pat<(add GPRC:$in, imm:$imm), 1144 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1145// OR an arbitrary immediate. 1146def : Pat<(or GPRC:$in, imm:$imm), 1147 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1148// XOR an arbitrary immediate. 1149def : Pat<(xor GPRC:$in, imm:$imm), 1150 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1151// SUBFIC 1152def : Pat<(sub immSExt16:$imm, GPRC:$in), 1153 (SUBFIC GPRC:$in, imm:$imm)>; 1154 1155// SHL/SRL 1156def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1157 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1158def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1159 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1160 1161// ROTL 1162def : Pat<(rotl GPRC:$in, GPRC:$sh), 1163 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1164def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1165 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1166 1167// RLWNM 1168def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm), 1169 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 1170 1171// Calls 1172def : Pat<(PPCcall_Macho (i32 tglobaladdr:$dst)), 1173 (BL_Macho tglobaladdr:$dst)>; 1174def : Pat<(PPCcall_Macho (i32 texternalsym:$dst)), 1175 (BL_Macho texternalsym:$dst)>; 1176def : Pat<(PPCcall_ELF (i32 tglobaladdr:$dst)), 1177 (BL_ELF tglobaladdr:$dst)>; 1178def : Pat<(PPCcall_ELF (i32 texternalsym:$dst)), 1179 (BL_ELF texternalsym:$dst)>; 1180 1181// Hi and Lo for Darwin Global Addresses. 1182def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1183def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1184def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1185def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1186def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1187def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1188def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1189 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1190def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1191 (ADDIS GPRC:$in, tconstpool:$g)>; 1192def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 1193 (ADDIS GPRC:$in, tjumptable:$g)>; 1194 1195// Fused negative multiply subtract, alternate pattern 1196def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), 1197 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>, 1198 Requires<[FPContractions]>; 1199def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)), 1200 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>, 1201 Requires<[FPContractions]>; 1202 1203// Standard shifts. These are represented separately from the real shifts above 1204// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1205// amounts. 1206def : Pat<(sra GPRC:$rS, GPRC:$rB), 1207 (SRAW GPRC:$rS, GPRC:$rB)>; 1208def : Pat<(srl GPRC:$rS, GPRC:$rB), 1209 (SRW GPRC:$rS, GPRC:$rB)>; 1210def : Pat<(shl GPRC:$rS, GPRC:$rB), 1211 (SLW GPRC:$rS, GPRC:$rB)>; 1212 1213def : Pat<(zextloadi1 iaddr:$src), 1214 (LBZ iaddr:$src)>; 1215def : Pat<(zextloadi1 xaddr:$src), 1216 (LBZX xaddr:$src)>; 1217def : Pat<(extloadi1 iaddr:$src), 1218 (LBZ iaddr:$src)>; 1219def : Pat<(extloadi1 xaddr:$src), 1220 (LBZX xaddr:$src)>; 1221def : Pat<(extloadi8 iaddr:$src), 1222 (LBZ iaddr:$src)>; 1223def : Pat<(extloadi8 xaddr:$src), 1224 (LBZX xaddr:$src)>; 1225def : Pat<(extloadi16 iaddr:$src), 1226 (LHZ iaddr:$src)>; 1227def : Pat<(extloadi16 xaddr:$src), 1228 (LHZX xaddr:$src)>; 1229def : Pat<(extloadf32 iaddr:$src), 1230 (FMRSD (LFS iaddr:$src))>; 1231def : Pat<(extloadf32 xaddr:$src), 1232 (FMRSD (LFSX xaddr:$src))>; 1233 1234include "PPCInstrAltivec.td" 1235include "PPCInstr64Bit.td" 1236