PPCInstrInfo.td revision f6cd147471fb9a89661e2093731d6d40d4f41c7c
1//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17 18//===----------------------------------------------------------------------===// 19// PowerPC specific transformation functions and pattern fragments. 20// 21 22def LO16 : SDNodeXForm<imm, [{ 23 // Transformation function: get the low 16 bits. 24 return getI32Imm((unsigned short)N->getValue()); 25}]>; 26 27def HI16 : SDNodeXForm<imm, [{ 28 // Transformation function: shift the immediate value down into the low bits. 29 return getI32Imm((unsigned)N->getValue() >> 16); 30}]>; 31 32def HA16 : SDNodeXForm<imm, [{ 33 // Transformation function: shift the immediate value down into the low bits. 34 signed int Val = N->getValue(); 35 return getI32Imm((Val - (signed short)Val) >> 16); 36}]>; 37 38 39def immSExt16 : PatLeaf<(imm), [{ 40 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 41 // field. Used by instructions like 'addi'. 42 return (int)N->getValue() == (short)N->getValue(); 43}]>; 44def immZExt16 : PatLeaf<(imm), [{ 45 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 46 // field. Used by instructions like 'ori'. 47 return (unsigned)N->getValue() == (unsigned short)N->getValue(); 48}], LO16>; 49 50def imm16Shifted : PatLeaf<(imm), [{ 51 // imm16Shifted predicate - True if only bits in the top 16-bits of the 52 // immediate are set. Used by instructions like 'addis'. 53 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue(); 54}], HI16>; 55 56/* 57// Example of a legalize expander: Only for PPC64. 58def : Expander<(set i64:$dst, (fp_to_sint f64:$src)), 59 [(set f64:$tmp , (FCTIDZ f64:$src)), 60 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)), 61 (store f64:$tmp, i32:$tmpFI), 62 (set i64:$dst, (load i32:$tmpFI))], 63 Subtarget_PPC64>; 64*/ 65 66//===----------------------------------------------------------------------===// 67// PowerPC Flag Definitions. 68 69class isPPC64 { bit PPC64 = 1; } 70class isVMX { bit VMX = 1; } 71class isDOT { 72 list<Register> Defs = [CR0]; 73 bit RC = 1; 74} 75 76 77 78//===----------------------------------------------------------------------===// 79// PowerPC Operand Definitions. 80 81def u5imm : Operand<i32> { 82 let PrintMethod = "printU5ImmOperand"; 83} 84def u6imm : Operand<i32> { 85 let PrintMethod = "printU6ImmOperand"; 86} 87def s16imm : Operand<i32> { 88 let PrintMethod = "printS16ImmOperand"; 89} 90def u16imm : Operand<i32> { 91 let PrintMethod = "printU16ImmOperand"; 92} 93def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 94 let PrintMethod = "printS16X4ImmOperand"; 95} 96def target : Operand<i32> { 97 let PrintMethod = "printBranchOperand"; 98} 99def piclabel: Operand<i32> { 100 let PrintMethod = "printPICLabel"; 101} 102def symbolHi: Operand<i32> { 103 let PrintMethod = "printSymbolHi"; 104} 105def symbolLo: Operand<i32> { 106 let PrintMethod = "printSymbolLo"; 107} 108def crbitm: Operand<i8> { 109 let PrintMethod = "printcrbitm"; 110} 111 112 113 114//===----------------------------------------------------------------------===// 115// PowerPC Instruction Definitions. 116 117// Pseudo-instructions: 118def PHI : Pseudo<(ops variable_ops), "; PHI">; 119 120let isLoad = 1 in { 121def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">; 122def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">; 123} 124def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">; 125def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8">; 126def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4">; 127 128// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 129// scheduler into a branch sequence. 130let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 131 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F, 132 i32imm:$BROPC), "; SELECT_CC PSEUDO!">; 133 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F, 134 i32imm:$BROPC), "; SELECT_CC PSEUDO!">; 135 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F, 136 i32imm:$BROPC), "; SELECT_CC PSEUDO!">; 137} 138 139 140let isTerminator = 1 in { 141 let isReturn = 1 in 142 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">; 143 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">; 144} 145 146let Defs = [LR] in 147 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">; 148 149let isBranch = 1, isTerminator = 1 in { 150 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, 151 target:$true, target:$false), 152 "; COND_BRANCH">; 153 def B : IForm<18, 0, 0, (ops target:$func), "b $func">; 154//def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">; 155 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">; 156//def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">; 157 158 // FIXME: 4*CR# needs to be added to the BI field! 159 // This will only work for CR0 as it stands now 160 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block), 161 "blt $crS, $block">; 162 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block), 163 "ble $crS, $block">; 164 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block), 165 "beq $crS, $block">; 166 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block), 167 "bge $crS, $block">; 168 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block), 169 "bgt $crS, $block">; 170 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block), 171 "bne $crS, $block">; 172} 173 174let isCall = 1, 175 // All calls clobber the non-callee saved registers... 176 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 177 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 178 LR,CTR, 179 CR0,CR1,CR5,CR6,CR7] in { 180 // Convenient aliases for call instructions 181 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">; 182 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, 183 (ops variable_ops), "bctrl">; 184} 185 186// D-Form instructions. Most instructions that perform an operation on a 187// register and an immediate are of this type. 188// 189let isLoad = 1 in { 190def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA), 191 "lbz $rD, $disp($rA)">; 192def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA), 193 "lha $rD, $disp($rA)">; 194def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA), 195 "lhz $rD, $disp($rA)">; 196def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA), 197 "lmw $rD, $disp($rA)">; 198def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA), 199 "lwz $rD, $disp($rA)">; 200def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA), 201 "lwzu $rD, $disp($rA)">; 202} 203def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 204 "addi $rD, $rA, $imm", 205 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 206def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 207 "addic $rD, $rA, $imm", 208 []>; 209def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 210 "addic. $rD, $rA, $imm", 211 []>; 212def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm), 213 "addis $rD, $rA, $imm", 214 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>; 215def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym), 216 "la $rD, $sym($rA)", 217 []>; 218def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 219 "mulli $rD, $rA, $imm", 220 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 221def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), 222 "subfic $rD, $rA, $imm", 223 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>; 224def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm), 225 "li $rD, $imm", 226 [(set GPRC:$rD, immSExt16:$imm)]>; 227def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm), 228 "lis $rD, $imm", 229 [(set GPRC:$rD, imm16Shifted:$imm)]>; 230let isStore = 1 in { 231def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 232 "stmw $rS, $disp($rA)">; 233def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA), 234 "stb $rS, $disp($rA)">; 235def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA), 236 "sth $rS, $disp($rA)">; 237def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA), 238 "stw $rS, $disp($rA)">; 239def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), 240 "stwu $rS, $disp($rA)">; 241} 242def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 243 "andi. $dst, $src1, $src2", 244 []>, isDOT; 245def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 246 "andis. $dst, $src1, $src2", 247 []>, isDOT; 248def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 249 "ori $dst, $src1, $src2", 250 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 251def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 252 "oris $dst, $src1, $src2", 253 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>; 254def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 255 "xori $dst, $src1, $src2", 256 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 257def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), 258 "xoris $dst, $src1, $src2", 259 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>; 260def NOP : DForm_4_zero<24, (ops), "nop">; 261def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm), 262 "cmpi $crD, $L, $rA, $imm">; 263def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 264 "cmpwi $crD, $rA, $imm">; 265def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 266 "cmpdi $crD, $rA, $imm">, isPPC64; 267def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2), 268 "cmpli $dst, $size, $src1, $src2">; 269def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 270 "cmplwi $dst, $src1, $src2">; 271def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 272 "cmpldi $dst, $src1, $src2">, isPPC64; 273let isLoad = 1 in { 274def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA), 275 "lfs $rD, $disp($rA)">; 276def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA), 277 "lfd $rD, $disp($rA)">; 278} 279let isStore = 1 in { 280def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA), 281 "stfs $rS, $disp($rA)">; 282def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA), 283 "stfd $rS, $disp($rA)">; 284} 285 286// DS-Form instructions. Load/Store instructions available in PPC-64 287// 288let isLoad = 1 in { 289def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 290 "lwa $rT, $DS($rA)">, isPPC64; 291def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 292 "ld $rT, $DS($rA)">, isPPC64; 293} 294let isStore = 1 in { 295def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 296 "std $rT, $DS($rA)">, isPPC64; 297def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), 298 "stdu $rT, $DS($rA)">, isPPC64; 299} 300 301// X-Form instructions. Most instructions that perform an operation on a 302// register and another register are of this type. 303// 304let isLoad = 1 in { 305def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index), 306 "lbzx $dst, $base, $index">; 307def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index), 308 "lhax $dst, $base, $index">; 309def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index), 310 "lhzx $dst, $base, $index">; 311def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index), 312 "lwax $dst, $base, $index">, isPPC64; 313def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index), 314 "lwzx $dst, $base, $index">; 315def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index), 316 "ldx $dst, $base, $index">, isPPC64; 317} 318def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 319 "nand $rA, $rS, $rB", 320 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 321def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 322 "and $rA, $rS, $rB", 323 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 324def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 325 "and. $rA, $rS, $rB", 326 []>, isDOT; 327def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 328 "andc $rA, $rS, $rB", 329 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 330def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 331 "or $rA, $rS, $rB", 332 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 333def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 334 "or $rA, $rS, $rB", 335 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 336def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB), 337 "or $rA, $rS, $rB", 338 []>; 339def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB), 340 "or $rA, $rS, $rB", 341 []>; 342def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 343 "nor $rA, $rS, $rB", 344 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 345def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 346 "or. $rA, $rS, $rB", 347 []>, isDOT; 348def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 349 "orc $rA, $rS, $rB", 350 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 351def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 352 "eqv $rA, $rS, $rB", 353 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 354def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 355 "xor $rA, $rS, $rB", 356 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 357def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 358 "sld $rA, $rS, $rB", 359 []>, isPPC64; 360def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 361 "slw $rA, $rS, $rB", 362 [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>; 363def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 364 "srd $rA, $rS, $rB", 365 []>, isPPC64; 366def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 367 "srw $rA, $rS, $rB", 368 [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>; 369def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 370 "srad $rA, $rS, $rB", 371 []>, isPPC64; 372def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), 373 "sraw $rA, $rS, $rB", 374 [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>; 375let isStore = 1 in { 376def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 377 "stbx $rS, $rA, $rB">; 378def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 379 "sthx $rS, $rA, $rB">; 380def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 381 "stwx $rS, $rA, $rB">; 382def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 383 "stwux $rS, $rA, $rB">; 384def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 385 "stdx $rS, $rA, $rB">, isPPC64; 386def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), 387 "stdux $rS, $rA, $rB">, isPPC64; 388} 389def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), 390 "srawi $rA, $rS, $SH", 391 [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>; 392def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS), 393 "cntlzw $rA, $rS", 394 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 395def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS), 396 "extsb $rA, $rS", 397 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 398def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS), 399 "extsh $rA, $rS", 400 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 401def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS), 402 "extsw $rA, $rS", 403 []>, isPPC64; 404def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB), 405 "cmp $crD, $long, $rA, $rB">; 406def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB), 407 "cmpl $crD, $long, $rA, $rB">; 408def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 409 "cmpw $crD, $rA, $rB">; 410def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 411 "cmpd $crD, $rA, $rB">, isPPC64; 412def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 413 "cmplw $crD, $rA, $rB">; 414def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 415 "cmpld $crD, $rA, $rB">, isPPC64; 416//def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB), 417// "fcmpo $crD, $fA, $fB">; 418def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB), 419 "fcmpu $crD, $fA, $fB">; 420def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB), 421 "fcmpu $crD, $fA, $fB">; 422 423let isLoad = 1 in { 424def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index), 425 "lfsx $dst, $base, $index">; 426def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index), 427 "lfdx $dst, $base, $index">; 428} 429def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB), 430 "fcfid $frD, $frB", 431 []>, isPPC64; 432def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB), 433 "fctidz $frD, $frB", 434 []>, isPPC64; 435def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB), 436 "fctiwz $frD, $frB", 437 []>; 438def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB), 439 "frsp $frD, $frB", 440 [(set F4RC:$frD, (fround F8RC:$frB))]>; 441def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB), 442 "fsqrt $frD, $frB", 443 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 444def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB), 445 "fsqrts $frD, $frB", 446 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 447 448/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending. 449def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB), 450 "fmr $frD, $frB", 451 []>; // (set F4RC:$frD, F4RC:$frB) 452def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB), 453 "fmr $frD, $frB", 454 []>; // (set F8RC:$frD, F8RC:$frB) 455def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB), 456 "fmr $frD, $frB", 457 [(set F8RC:$frD, (fextend F4RC:$frB))]>; 458 459// These are artificially split into two different forms, for 4/8 byte FP. 460def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB), 461 "fabs $frD, $frB", 462 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 463def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB), 464 "fabs $frD, $frB", 465 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 466def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB), 467 "fnabs $frD, $frB", 468 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 469def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB), 470 "fnabs $frD, $frB", 471 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 472def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB), 473 "fneg $frD, $frB", 474 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 475def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB), 476 "fneg $frD, $frB", 477 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 478 479 480let isStore = 1 in { 481def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB), 482 "stfsx $frS, $rA, $rB">; 483def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB), 484 "stfdx $frS, $rA, $rB">; 485} 486 487// XL-Form instructions. condition register logical ops. 488// 489def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA), 490 "mcrf $BF, $BFA">; 491 492// XFX-Form instructions. Instructions that deal with SPRs 493// 494// Note that although LR should be listed as `8' and CTR as `9' in the SPR 495// field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9 496// which means the SPR value needs to be multiplied by a factor of 32. 497def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">; 498def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">; 499def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">; 500def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS), 501 "mtcrf $FXM, $rS">; 502def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM), 503 "mfcr $rT, $FXM">; 504def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">; 505def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">; 506 507// XS-Form instructions. Just 'sradi' 508// 509def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH), 510 "sradi $rA, $rS, $SH">, isPPC64; 511 512// XO-Form instructions. Arithmetic instructions that can set overflow bit 513// 514def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 515 "add $rT, $rA, $rB", 516 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 517def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 518 "add $rT, $rA, $rB", 519 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 520def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 521 "addc $rT, $rA, $rB", 522 []>; 523def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 524 "adde $rT, $rA, $rB", 525 []>; 526def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 527 "divd $rT, $rA, $rB", 528 []>, isPPC64; 529def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 530 "divdu $rT, $rA, $rB", 531 []>, isPPC64; 532def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 533 "divw $rT, $rA, $rB", 534 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>; 535def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 536 "divwu $rT, $rA, $rB", 537 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>; 538def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 539 "mulhw $rT, $rA, $rB", 540 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 541def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 542 "mulhwu $rT, $rA, $rB", 543 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 544def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 545 "mulld $rT, $rA, $rB", 546 []>, isPPC64; 547def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 548 "mullw $rT, $rA, $rB", 549 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 550def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 551 "subf $rT, $rA, $rB", 552 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 553def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 554 "subfc $rT, $rA, $rB", 555 []>; 556def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), 557 "subfe $rT, $rA, $rB", 558 []>; 559def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA), 560 "addme $rT, $rA", 561 []>; 562def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA), 563 "addze $rT, $rA", 564 []>; 565def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA), 566 "neg $rT, $rA", 567 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 568def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA), 569 "subfze $rT, $rA", 570 []>; 571 572// A-Form instructions. Most of the instructions executed in the FPU are of 573// this type. 574// 575def FMADD : AForm_1<63, 29, 576 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 577 "fmadd $FRT, $FRA, $FRC, $FRB", 578 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), 579 F8RC:$FRB))]>; 580def FMADDS : AForm_1<59, 29, 581 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 582 "fmadds $FRT, $FRA, $FRC, $FRB", 583 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), 584 F4RC:$FRB))]>; 585def FMSUB : AForm_1<63, 28, 586 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 587 "fmsub $FRT, $FRA, $FRC, $FRB", 588 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), 589 F8RC:$FRB))]>; 590def FMSUBS : AForm_1<59, 28, 591 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 592 "fmsubs $FRT, $FRA, $FRC, $FRB", 593 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), 594 F4RC:$FRB))]>; 595def FNMADD : AForm_1<63, 31, 596 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 597 "fnmadd $FRT, $FRA, $FRC, $FRB", 598 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), 599 F8RC:$FRB)))]>; 600def FNMADDS : AForm_1<59, 31, 601 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 602 "fnmadds $FRT, $FRA, $FRC, $FRB", 603 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), 604 F4RC:$FRB)))]>; 605def FNMSUB : AForm_1<63, 30, 606 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 607 "fnmsub $FRT, $FRA, $FRC, $FRB", 608 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), 609 F8RC:$FRB)))]>; 610def FNMSUBS : AForm_1<59, 30, 611 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 612 "fnmsubs $FRT, $FRA, $FRC, $FRB", 613 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), 614 F4RC:$FRB)))]>; 615// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 616// having 4 of these, force the comparison to always be an 8-byte double (code 617// should use an FMRSD if the input comparison value really wants to be a float) 618// and 4/8 byte forms for the result and operand type.. 619def FSELD : AForm_1<63, 23, 620 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 621 "fsel $FRT, $FRA, $FRC, $FRB", 622 []>; 623def FSELS : AForm_1<63, 23, 624 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 625 "fsel $FRT, $FRA, $FRC, $FRB", 626 []>; 627def FADD : AForm_2<63, 21, 628 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 629 "fadd $FRT, $FRA, $FRB", 630 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 631def FADDS : AForm_2<59, 21, 632 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 633 "fadds $FRT, $FRA, $FRB", 634 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 635def FDIV : AForm_2<63, 18, 636 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 637 "fdiv $FRT, $FRA, $FRB", 638 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 639def FDIVS : AForm_2<59, 18, 640 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 641 "fdivs $FRT, $FRA, $FRB", 642 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 643def FMUL : AForm_3<63, 25, 644 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 645 "fmul $FRT, $FRA, $FRB", 646 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 647def FMULS : AForm_3<59, 25, 648 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 649 "fmuls $FRT, $FRA, $FRB", 650 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 651def FSUB : AForm_2<63, 20, 652 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), 653 "fsub $FRT, $FRA, $FRB", 654 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 655def FSUBS : AForm_2<59, 20, 656 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), 657 "fsubs $FRT, $FRA, $FRB", 658 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 659 660// M-Form instructions. rotate and mask instructions. 661// 662let isTwoAddress = 1, isCommutable = 1 in { 663// RLWIMI can be commuted if the rotate amount is zero. 664def RLWIMI : MForm_2<20, 665 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 666 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">; 667def RLDIMI : MDForm_1<30, 3, 668 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 669 "rldimi $rA, $rS, $SH, $MB">, isPPC64; 670} 671def RLWINM : MForm_2<21, 672 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 673 "rlwinm $rA, $rS, $SH, $MB, $ME">; 674def RLWINMo : MForm_2<21, 675 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 676 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT; 677def RLWNM : MForm_2<23, 678 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 679 "rlwnm $rA, $rS, $rB, $MB, $ME">; 680 681// MD-Form instructions. 64 bit rotate instructions. 682// 683def RLDICL : MDForm_1<30, 0, 684 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB), 685 "rldicl $rA, $rS, $SH, $MB">, isPPC64; 686def RLDICR : MDForm_1<30, 1, 687 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME), 688 "rldicr $rA, $rS, $SH, $ME">, isPPC64; 689 690//===----------------------------------------------------------------------===// 691// PowerPC Instruction Patterns 692// 693 694// Arbitrary immediate support. Implement in terms of LIS/ORI. 695def : Pat<(i32 imm:$imm), 696 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 697 698// Implement the 'not' operation with the NOR instruction. 699def NOT : Pat<(not GPRC:$in), 700 (NOR GPRC:$in, GPRC:$in)>; 701 702// ADD an arbitrary immediate. 703def : Pat<(add GPRC:$in, imm:$imm), 704 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 705// OR an arbitrary immediate. 706def : Pat<(or GPRC:$in, imm:$imm), 707 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 708// XOR an arbitrary immediate. 709def : Pat<(xor GPRC:$in, imm:$imm), 710 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 711 712def : Pat<(zext GPRC:$in), 713 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; 714def : Pat<(anyext GPRC:$in), 715 (OR4To8 GPRC:$in, GPRC:$in)>; 716def : Pat<(trunc G8RC:$in), 717 (OR8To4 G8RC:$in, G8RC:$in)>; 718 719// Same as above, but using a temporary. FIXME: implement temporaries :) 720/* 721def : Pattern<(xor GPRC:$in, imm:$imm), 722 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))), 723 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>; 724*/ 725 726 727//===----------------------------------------------------------------------===// 728// PowerPCInstrInfo Definition 729// 730def PowerPCInstrInfo : InstrInfo { 731 let PHIInst = PHI; 732 733 let TSFlagsFields = [ "VMX", "PPC64" ]; 734 let TSFlagsShifts = [ 0, 1 ]; 735 736 let isLittleEndianEncoding = 1; 737} 738 739