PPCJITInfo.cpp revision e7a83dfac62eb01a1dcc71b98363d3bf3a893a6c
1//===-- PPCJITInfo.cpp - Implement the JIT interfaces for the PowerPC -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the JIT interfaces for the 32-bit PowerPC target. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "jit" 15#include "PPCJITInfo.h" 16#include "PPCRelocations.h" 17#include "PPCTargetMachine.h" 18#include "llvm/Function.h" 19#include "llvm/CodeGen/MachineCodeEmitter.h" 20#include "llvm/Config/alloca.h" 21#include "llvm/Support/Debug.h" 22#include <set> 23using namespace llvm; 24 25static TargetJITInfo::JITCompilerFn JITCompilerFunction; 26 27#define BUILD_ADDIS(RD,RS,IMM16) \ 28 ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535)) 29#define BUILD_ORI(RD,RS,UIMM16) \ 30 ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535)) 31#define BUILD_ORIS(RD,RS,UIMM16) \ 32 ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535)) 33#define BUILD_RLDICR(RD,RS,SH,ME) \ 34 ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \ 35 (((ME) & 63) << 6) | (1 << 2) | ((((SH) >> 5) & 1) << 1)) 36#define BUILD_MTSPR(RS,SPR) \ 37 ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1)) 38#define BUILD_BCCTRx(BO,BI,LINK) \ 39 ((19 << 26) | ((BO) << 21) | ((BI) << 16) | (528 << 1) | ((LINK) & 1)) 40#define BUILD_B(TARGET, LINK) \ 41 ((18 << 26) | (((TARGET) & 0x00FFFFFF) << 2) | ((LINK) & 1)) 42 43// Pseudo-ops 44#define BUILD_LIS(RD,IMM16) BUILD_ADDIS(RD,0,IMM16) 45#define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6) 46#define BUILD_MTCTR(RS) BUILD_MTSPR(RS,9) 47#define BUILD_BCTR(LINK) BUILD_BCCTRx(20,0,LINK) 48 49static void EmitBranchToAt(uint64_t At, uint64_t To, bool isCall, bool is64Bit){ 50 intptr_t Offset = ((intptr_t)To - (intptr_t)At) >> 2; 51 unsigned *AtI = (unsigned*)(intptr_t)At; 52 53 if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range? 54 AtI[0] = BUILD_B(Offset, isCall); // b/bl target 55 } else if (!is64Bit) { 56 AtI[0] = BUILD_LIS(12, To >> 16); // lis r12, hi16(address) 57 AtI[1] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address) 58 AtI[2] = BUILD_MTCTR(12); // mtctr r12 59 AtI[3] = BUILD_BCTR(isCall); // bctr/bctrl 60 } else { 61 AtI[0] = BUILD_LIS(12, To >> 48); // lis r12, hi16(address) 62 AtI[1] = BUILD_ORI(12, 12, To >> 32); // ori r12, r12, lo16(address) 63 AtI[2] = BUILD_SLDI(12, 12, 32); // sldi r12, r12, 32 64 AtI[3] = BUILD_ORIS(12, 12, To >> 16); // oris r12, r12, hi16(address) 65 AtI[4] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address) 66 AtI[5] = BUILD_MTCTR(12); // mtctr r12 67 AtI[6] = BUILD_BCTR(isCall); // bctr/bctrl 68 } 69} 70 71extern "C" void PPC32CompilationCallback(); 72extern "C" void PPC64CompilationCallback(); 73 74#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \ 75 !(defined(__ppc64__) || defined(__FreeBSD__)) 76// CompilationCallback stub - We can't use a C function with inline assembly in 77// it, because we the prolog/epilog inserted by GCC won't work for us. Instead, 78// write our own wrapper, which does things our way, so we have complete control 79// over register saving and restoring. 80asm( 81 ".text\n" 82 ".align 2\n" 83 ".globl _PPC32CompilationCallback\n" 84"_PPC32CompilationCallback:\n" 85 // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 86 // FIXME: need to save v[0-19] for altivec? 87 // FIXME: could shrink frame 88 // Set up a proper stack frame 89 // FIXME Layout 90 // PowerPC64 ABI linkage - 24 bytes 91 // parameters - 32 bytes 92 // 13 double registers - 104 bytes 93 // 8 int registers - 32 bytes 94 "mflr r0\n" 95 "stw r0, 8(r1)\n" 96 "stwu r1, -208(r1)\n" 97 // Save all int arg registers 98 "stw r10, 204(r1)\n" "stw r9, 200(r1)\n" 99 "stw r8, 196(r1)\n" "stw r7, 192(r1)\n" 100 "stw r6, 188(r1)\n" "stw r5, 184(r1)\n" 101 "stw r4, 180(r1)\n" "stw r3, 176(r1)\n" 102 // Save all call-clobbered FP regs. 103 "stfd f13, 168(r1)\n" "stfd f12, 160(r1)\n" 104 "stfd f11, 152(r1)\n" "stfd f10, 144(r1)\n" 105 "stfd f9, 136(r1)\n" "stfd f8, 128(r1)\n" 106 "stfd f7, 120(r1)\n" "stfd f6, 112(r1)\n" 107 "stfd f5, 104(r1)\n" "stfd f4, 96(r1)\n" 108 "stfd f3, 88(r1)\n" "stfd f2, 80(r1)\n" 109 "stfd f1, 72(r1)\n" 110 // Arguments to Compilation Callback: 111 // r3 - our lr (address of the call instruction in stub plus 4) 112 // r4 - stub's lr (address of instruction that called the stub plus 4) 113 // r5 - is64Bit - always 0. 114 "mr r3, r0\n" 115 "lwz r2, 208(r1)\n" // stub's frame 116 "lwz r4, 8(r2)\n" // stub's lr 117 "li r5, 0\n" // 0 == 32 bit 118 "bl _PPCCompilationCallbackC\n" 119 "mtctr r3\n" 120 // Restore all int arg registers 121 "lwz r10, 204(r1)\n" "lwz r9, 200(r1)\n" 122 "lwz r8, 196(r1)\n" "lwz r7, 192(r1)\n" 123 "lwz r6, 188(r1)\n" "lwz r5, 184(r1)\n" 124 "lwz r4, 180(r1)\n" "lwz r3, 176(r1)\n" 125 // Restore all FP arg registers 126 "lfd f13, 168(r1)\n" "lfd f12, 160(r1)\n" 127 "lfd f11, 152(r1)\n" "lfd f10, 144(r1)\n" 128 "lfd f9, 136(r1)\n" "lfd f8, 128(r1)\n" 129 "lfd f7, 120(r1)\n" "lfd f6, 112(r1)\n" 130 "lfd f5, 104(r1)\n" "lfd f4, 96(r1)\n" 131 "lfd f3, 88(r1)\n" "lfd f2, 80(r1)\n" 132 "lfd f1, 72(r1)\n" 133 // Pop 3 frames off the stack and branch to target 134 "lwz r1, 208(r1)\n" 135 "lwz r2, 8(r1)\n" 136 "mtlr r2\n" 137 "bctr\n" 138 ); 139 140#elif defined(__PPC__) && !defined(__ppc64__) 141// Linux & FreeBSD / PPC 32 support 142 143// CompilationCallback stub - We can't use a C function with inline assembly in 144// it, because we the prolog/epilog inserted by GCC won't work for us. Instead, 145// write our own wrapper, which does things our way, so we have complete control 146// over register saving and restoring. 147asm( 148 ".text\n" 149 ".align 2\n" 150 ".globl PPC32CompilationCallback\n" 151"PPC32CompilationCallback:\n" 152 // Make space for 8 ints r[3-10] and 8 doubles f[1-8] and the 153 // FIXME: need to save v[0-19] for altivec? 154 // FIXME: could shrink frame 155 // Set up a proper stack frame 156 // FIXME Layout 157 // 8 double registers - 64 bytes 158 // 8 int registers - 32 bytes 159 "mflr 0\n" 160 "stw 0, 4(1)\n" 161 "stwu 1, -104(1)\n" 162 // Save all int arg registers 163 "stw 10, 100(1)\n" "stw 9, 96(1)\n" 164 "stw 8, 92(1)\n" "stw 7, 88(1)\n" 165 "stw 6, 84(1)\n" "stw 5, 80(1)\n" 166 "stw 4, 76(1)\n" "stw 3, 72(1)\n" 167 // Save all call-clobbered FP regs. 168 "stfd 8, 64(1)\n" 169 "stfd 7, 56(1)\n" "stfd 6, 48(1)\n" 170 "stfd 5, 40(1)\n" "stfd 4, 32(1)\n" 171 "stfd 3, 24(1)\n" "stfd 2, 16(1)\n" 172 "stfd 1, 8(1)\n" 173 // Arguments to Compilation Callback: 174 // r3 - our lr (address of the call instruction in stub plus 4) 175 // r4 - stub's lr (address of instruction that called the stub plus 4) 176 // r5 - is64Bit - always 0. 177 "mr 3, 0\n" 178 "lwz 5, 104(1)\n" // stub's frame 179 "lwz 4, 4(5)\n" // stub's lr 180 "li 5, 0\n" // 0 == 32 bit 181 "bl PPCCompilationCallbackC\n" 182 "mtctr 3\n" 183 // Restore all int arg registers 184 "lwz 10, 100(1)\n" "lwz 9, 96(1)\n" 185 "lwz 8, 92(1)\n" "lwz 7, 88(1)\n" 186 "lwz 6, 84(1)\n" "lwz 5, 80(1)\n" 187 "lwz 4, 76(1)\n" "lwz 3, 72(1)\n" 188 // Restore all FP arg registers 189 "lfd 8, 64(1)\n" 190 "lfd 7, 56(1)\n" "lfd 6, 48(1)\n" 191 "lfd 5, 40(1)\n" "lfd 4, 32(1)\n" 192 "lfd 3, 24(1)\n" "lfd 2, 16(1)\n" 193 "lfd 1, 8(1)\n" 194 // Pop 3 frames off the stack and branch to target 195 "lwz 1, 104(1)\n" 196 "lwz 0, 4(1)\n" 197 "mtlr 0\n" 198 "bctr\n" 199 ); 200#else 201void PPC32CompilationCallback() { 202 assert(0 && "This is not a power pc, you can't execute this!"); 203 abort(); 204} 205#endif 206 207#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \ 208 defined(__ppc64__) 209asm( 210 ".text\n" 211 ".align 2\n" 212 ".globl _PPC64CompilationCallback\n" 213"_PPC64CompilationCallback:\n" 214 // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 215 // FIXME: need to save v[0-19] for altivec? 216 // Set up a proper stack frame 217 // Layout 218 // PowerPC64 ABI linkage - 48 bytes 219 // parameters - 64 bytes 220 // 13 double registers - 104 bytes 221 // 8 int registers - 64 bytes 222 "mflr r0\n" 223 "std r0, 16(r1)\n" 224 "stdu r1, -280(r1)\n" 225 // Save all int arg registers 226 "std r10, 272(r1)\n" "std r9, 264(r1)\n" 227 "std r8, 256(r1)\n" "std r7, 248(r1)\n" 228 "std r6, 240(r1)\n" "std r5, 232(r1)\n" 229 "std r4, 224(r1)\n" "std r3, 216(r1)\n" 230 // Save all call-clobbered FP regs. 231 "stfd f13, 208(r1)\n" "stfd f12, 200(r1)\n" 232 "stfd f11, 192(r1)\n" "stfd f10, 184(r1)\n" 233 "stfd f9, 176(r1)\n" "stfd f8, 168(r1)\n" 234 "stfd f7, 160(r1)\n" "stfd f6, 152(r1)\n" 235 "stfd f5, 144(r1)\n" "stfd f4, 136(r1)\n" 236 "stfd f3, 128(r1)\n" "stfd f2, 120(r1)\n" 237 "stfd f1, 112(r1)\n" 238 // Arguments to Compilation Callback: 239 // r3 - our lr (address of the call instruction in stub plus 4) 240 // r4 - stub's lr (address of instruction that called the stub plus 4) 241 // r5 - is64Bit - always 1. 242 "mr r3, r0\n" 243 "ld r2, 280(r1)\n" // stub's frame 244 "ld r4, 16(r2)\n" // stub's lr 245 "li r5, 1\n" // 1 == 64 bit 246 "bl _PPCCompilationCallbackC\n" 247 "mtctr r3\n" 248 // Restore all int arg registers 249 "ld r10, 272(r1)\n" "ld r9, 264(r1)\n" 250 "ld r8, 256(r1)\n" "ld r7, 248(r1)\n" 251 "ld r6, 240(r1)\n" "ld r5, 232(r1)\n" 252 "ld r4, 224(r1)\n" "ld r3, 216(r1)\n" 253 // Restore all FP arg registers 254 "lfd f13, 208(r1)\n" "lfd f12, 200(r1)\n" 255 "lfd f11, 192(r1)\n" "lfd f10, 184(r1)\n" 256 "lfd f9, 176(r1)\n" "lfd f8, 168(r1)\n" 257 "lfd f7, 160(r1)\n" "lfd f6, 152(r1)\n" 258 "lfd f5, 144(r1)\n" "lfd f4, 136(r1)\n" 259 "lfd f3, 128(r1)\n" "lfd f2, 120(r1)\n" 260 "lfd f1, 112(r1)\n" 261 // Pop 3 frames off the stack and branch to target 262 "ld r1, 280(r1)\n" 263 "ld r2, 16(r1)\n" 264 "mtlr r2\n" 265 "bctr\n" 266 ); 267#else 268void PPC64CompilationCallback() { 269 assert(0 && "This is not a power pc, you can't execute this!"); 270 abort(); 271} 272#endif 273 274extern "C" void *PPCCompilationCallbackC(unsigned *StubCallAddrPlus4, 275 unsigned *OrigCallAddrPlus4, 276 bool is64Bit) { 277 // Adjust the pointer to the address of the call instruction in the stub 278 // emitted by emitFunctionStub, rather than the instruction after it. 279 unsigned *StubCallAddr = StubCallAddrPlus4 - 1; 280 unsigned *OrigCallAddr = OrigCallAddrPlus4 - 1; 281 282 void *Target = JITCompilerFunction(StubCallAddr); 283 284 // Check to see if *OrigCallAddr is a 'bl' instruction, and if we can rewrite 285 // it to branch directly to the destination. If so, rewrite it so it does not 286 // need to go through the stub anymore. 287 unsigned OrigCallInst = *OrigCallAddr; 288 if ((OrigCallInst >> 26) == 18) { // Direct call. 289 intptr_t Offset = ((intptr_t)Target - (intptr_t)OrigCallAddr) >> 2; 290 291 if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range? 292 // Clear the original target out. 293 OrigCallInst &= (63 << 26) | 3; 294 // Fill in the new target. 295 OrigCallInst |= (Offset & ((1 << 24)-1)) << 2; 296 // Replace the call. 297 *OrigCallAddr = OrigCallInst; 298 } 299 } 300 301 // Assert that we are coming from a stub that was created with our 302 // emitFunctionStub. 303 if ((*StubCallAddr >> 26) == 18) 304 StubCallAddr -= 3; 305 else { 306 assert((*StubCallAddr >> 26) == 19 && "Call in stub is not indirect!"); 307 StubCallAddr -= is64Bit ? 9 : 6; 308 } 309 310 // Rewrite the stub with an unconditional branch to the target, for any users 311 // who took the address of the stub. 312 EmitBranchToAt((intptr_t)StubCallAddr, (intptr_t)Target, false, is64Bit); 313 314 // Put the address of the target function to call and the address to return to 315 // after calling the target function in a place that is easy to get on the 316 // stack after we restore all regs. 317 return Target; 318} 319 320 321 322TargetJITInfo::LazyResolverFn 323PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) { 324 JITCompilerFunction = Fn; 325 return is64Bit ? PPC64CompilationCallback : PPC32CompilationCallback; 326} 327 328#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \ 329defined(__APPLE__) 330extern "C" void sys_icache_invalidate(const void *Addr, size_t len); 331#endif 332 333/// SyncICache - On PPC, the JIT emitted code must be explicitly refetched to 334/// ensure correct execution. 335static void SyncICache(const void *Addr, size_t len) { 336#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \ 337defined(__APPLE__) 338 sys_icache_invalidate(Addr, len); 339#endif 340} 341 342void *PPCJITInfo::emitFunctionStub(const Function* F, void *Fn, 343 MachineCodeEmitter &MCE) { 344 // If this is just a call to an external function, emit a branch instead of a 345 // call. The code is the same except for one bit of the last instruction. 346 if (Fn != (void*)(intptr_t)PPC32CompilationCallback && 347 Fn != (void*)(intptr_t)PPC64CompilationCallback) { 348 MCE.startFunctionStub(F, 7*4); 349 intptr_t Addr = (intptr_t)MCE.getCurrentPCValue(); 350 MCE.emitWordBE(0); 351 MCE.emitWordBE(0); 352 MCE.emitWordBE(0); 353 MCE.emitWordBE(0); 354 MCE.emitWordBE(0); 355 MCE.emitWordBE(0); 356 MCE.emitWordBE(0); 357 EmitBranchToAt(Addr, (intptr_t)Fn, false, is64Bit); 358 SyncICache((void*)Addr, 7*4); 359 return MCE.finishFunctionStub(F); 360 } 361 362 MCE.startFunctionStub(F, 10*4); 363 intptr_t Addr = (intptr_t)MCE.getCurrentPCValue(); 364 if (is64Bit) { 365 MCE.emitWordBE(0xf821ffb1); // stdu r1,-80(r1) 366 MCE.emitWordBE(0x7d6802a6); // mflr r11 367 MCE.emitWordBE(0xf9610060); // std r11, 96(r1) 368 } else if (TM.getSubtargetImpl()->isMachoABI()){ 369 MCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1) 370 MCE.emitWordBE(0x7d6802a6); // mflr r11 371 MCE.emitWordBE(0x91610028); // stw r11, 40(r1) 372 } else { 373 MCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1) 374 MCE.emitWordBE(0x7d6802a6); // mflr r11 375 MCE.emitWordBE(0x91610024); // stw r11, 36(r1) 376 } 377 intptr_t BranchAddr = (intptr_t)MCE.getCurrentPCValue(); 378 MCE.emitWordBE(0); 379 MCE.emitWordBE(0); 380 MCE.emitWordBE(0); 381 MCE.emitWordBE(0); 382 MCE.emitWordBE(0); 383 MCE.emitWordBE(0); 384 MCE.emitWordBE(0); 385 EmitBranchToAt(BranchAddr, (intptr_t)Fn, true, is64Bit); 386 SyncICache((void*)Addr, 10*4); 387 return MCE.finishFunctionStub(F); 388} 389 390 391void PPCJITInfo::relocate(void *Function, MachineRelocation *MR, 392 unsigned NumRelocs, unsigned char* GOTBase) { 393 for (unsigned i = 0; i != NumRelocs; ++i, ++MR) { 394 unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4; 395 intptr_t ResultPtr = (intptr_t)MR->getResultPointer(); 396 switch ((PPC::RelocationType)MR->getRelocationType()) { 397 default: assert(0 && "Unknown relocation type!"); 398 case PPC::reloc_pcrel_bx: 399 // PC-relative relocation for b and bl instructions. 400 ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2; 401 assert(ResultPtr >= -(1 << 23) && ResultPtr < (1 << 23) && 402 "Relocation out of range!"); 403 *RelocPos |= (ResultPtr & ((1 << 24)-1)) << 2; 404 break; 405 case PPC::reloc_pcrel_bcx: 406 // PC-relative relocation for BLT,BLE,BEQ,BGE,BGT,BNE, or other 407 // bcx instructions. 408 ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2; 409 assert(ResultPtr >= -(1 << 13) && ResultPtr < (1 << 13) && 410 "Relocation out of range!"); 411 *RelocPos |= (ResultPtr & ((1 << 14)-1)) << 2; 412 break; 413 case PPC::reloc_absolute_high: // high bits of ref -> low 16 of instr 414 case PPC::reloc_absolute_low: { // low bits of ref -> low 16 of instr 415 ResultPtr += MR->getConstantVal(); 416 417 // If this is a high-part access, get the high-part. 418 if (MR->getRelocationType() == PPC::reloc_absolute_high) { 419 // If the low part will have a carry (really a borrow) from the low 420 // 16-bits into the high 16, add a bit to borrow from. 421 if (((int)ResultPtr << 16) < 0) 422 ResultPtr += 1 << 16; 423 ResultPtr >>= 16; 424 } 425 426 // Do the addition then mask, so the addition does not overflow the 16-bit 427 // immediate section of the instruction. 428 unsigned LowBits = (*RelocPos + ResultPtr) & 65535; 429 unsigned HighBits = *RelocPos & ~65535; 430 *RelocPos = LowBits | HighBits; // Slam into low 16-bits 431 break; 432 } 433 case PPC::reloc_absolute_low_ix: { // low bits of ref -> low 14 of instr 434 ResultPtr += MR->getConstantVal(); 435 // Do the addition then mask, so the addition does not overflow the 16-bit 436 // immediate section of the instruction. 437 unsigned LowBits = (*RelocPos + ResultPtr) & 0xFFFC; 438 unsigned HighBits = *RelocPos & 0xFFFF0003; 439 *RelocPos = LowBits | HighBits; // Slam into low 14-bits. 440 break; 441 } 442 } 443 } 444} 445 446void PPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { 447 EmitBranchToAt((intptr_t)Old, (intptr_t)New, false, is64Bit); 448} 449