1//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#include "PPCRegisterInfo.h"
16#include "PPC.h"
17#include "PPCFrameLowering.h"
18#include "PPCInstrBuilder.h"
19#include "PPCMachineFunctionInfo.h"
20#include "PPCSubtarget.h"
21#include "llvm/ADT/BitVector.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineModuleInfo.h"
27#include "llvm/CodeGen/MachineRegisterInfo.h"
28#include "llvm/CodeGen/RegisterScavenging.h"
29#include "llvm/IR/CallingConv.h"
30#include "llvm/IR/Constants.h"
31#include "llvm/IR/Function.h"
32#include "llvm/IR/Type.h"
33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/MathExtras.h"
37#include "llvm/Support/raw_ostream.h"
38#include "llvm/Target/TargetFrameLowering.h"
39#include "llvm/Target/TargetInstrInfo.h"
40#include "llvm/Target/TargetMachine.h"
41#include "llvm/Target/TargetOptions.h"
42#include <cstdlib>
43
44using namespace llvm;
45
46#define DEBUG_TYPE "reginfo"
47
48#define GET_REGINFO_TARGET_DESC
49#include "PPCGenRegisterInfo.inc"
50
51static cl::opt<bool>
52EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
53         cl::desc("Enable use of a base pointer for complex stack frames"));
54
55static cl::opt<bool>
56AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
57         cl::desc("Force the use of a base pointer in every function"));
58
59PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST)
60  : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
61                       ST.isPPC64() ? 0 : 1,
62                       ST.isPPC64() ? 0 : 1),
63    Subtarget(ST) {
64  ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
65  ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
66  ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
67  ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
68  ImmToIdxMap[PPC::LFS]  = PPC::LFSX;   ImmToIdxMap[PPC::LFD]  = PPC::LFDX;
69  ImmToIdxMap[PPC::STH]  = PPC::STHX;   ImmToIdxMap[PPC::STW]  = PPC::STWX;
70  ImmToIdxMap[PPC::STFS] = PPC::STFSX;  ImmToIdxMap[PPC::STFD] = PPC::STFDX;
71  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
72  ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
73
74  // 64-bit
75  ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
76  ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
77  ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
78  ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
79  ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
80}
81
82/// getPointerRegClass - Return the register class to use to hold pointers.
83/// This is used for addressing modes.
84const TargetRegisterClass *
85PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
86                                                                       const {
87  // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
88  // when it checks for ZERO folding.
89  if (Kind == 1) {
90    if (Subtarget.isPPC64())
91      return &PPC::G8RC_NOX0RegClass;
92    return &PPC::GPRC_NOR0RegClass;
93  }
94
95  if (Subtarget.isPPC64())
96    return &PPC::G8RCRegClass;
97  return &PPC::GPRCRegClass;
98}
99
100const MCPhysReg*
101PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
102  if (Subtarget.isDarwinABI())
103    return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
104                                  CSR_Darwin64_Altivec_SaveList :
105                                  CSR_Darwin64_SaveList) :
106                                 (Subtarget.hasAltivec() ?
107                                  CSR_Darwin32_Altivec_SaveList :
108                                  CSR_Darwin32_SaveList);
109
110  return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
111                                CSR_SVR464_Altivec_SaveList :
112                                CSR_SVR464_SaveList) :
113                               (Subtarget.hasAltivec() ?
114                                CSR_SVR432_Altivec_SaveList :
115                                CSR_SVR432_SaveList);
116}
117
118const uint32_t*
119PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
120  if (Subtarget.isDarwinABI())
121    return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
122                                  CSR_Darwin64_Altivec_RegMask :
123                                  CSR_Darwin64_RegMask) :
124                                 (Subtarget.hasAltivec() ?
125                                  CSR_Darwin32_Altivec_RegMask :
126                                  CSR_Darwin32_RegMask);
127
128  return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
129                                CSR_SVR464_Altivec_RegMask :
130                                CSR_SVR464_RegMask) :
131                               (Subtarget.hasAltivec() ?
132                                CSR_SVR432_Altivec_RegMask :
133                                CSR_SVR432_RegMask);
134}
135
136const uint32_t*
137PPCRegisterInfo::getNoPreservedMask() const {
138  return CSR_NoRegs_RegMask;
139}
140
141BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
142  BitVector Reserved(getNumRegs());
143  const PPCFrameLowering *PPCFI =
144    static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
145
146  // The ZERO register is not really a register, but the representation of r0
147  // when used in instructions that treat r0 as the constant 0.
148  Reserved.set(PPC::ZERO);
149  Reserved.set(PPC::ZERO8);
150
151  // The FP register is also not really a register, but is the representation
152  // of the frame pointer register used by ISD::FRAMEADDR.
153  Reserved.set(PPC::FP);
154  Reserved.set(PPC::FP8);
155
156  // The BP register is also not really a register, but is the representation
157  // of the base pointer register used by setjmp.
158  Reserved.set(PPC::BP);
159  Reserved.set(PPC::BP8);
160
161  // The counter registers must be reserved so that counter-based loops can
162  // be correctly formed (and the mtctr instructions are not DCE'd).
163  Reserved.set(PPC::CTR);
164  Reserved.set(PPC::CTR8);
165
166  Reserved.set(PPC::R1);
167  Reserved.set(PPC::LR);
168  Reserved.set(PPC::LR8);
169  Reserved.set(PPC::RM);
170
171  if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
172    Reserved.set(PPC::VRSAVE);
173
174  // The SVR4 ABI reserves r2 and r13
175  if (Subtarget.isSVR4ABI()) {
176    Reserved.set(PPC::R2);  // System-reserved register
177    Reserved.set(PPC::R13); // Small Data Area pointer register
178  }
179
180  // On PPC64, r13 is the thread pointer. Never allocate this register.
181  if (Subtarget.isPPC64()) {
182    Reserved.set(PPC::R13);
183
184    Reserved.set(PPC::X1);
185    Reserved.set(PPC::X13);
186
187    if (PPCFI->needsFP(MF))
188      Reserved.set(PPC::X31);
189
190    if (hasBasePointer(MF))
191      Reserved.set(PPC::X30);
192
193    // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
194    if (Subtarget.isSVR4ABI()) {
195      Reserved.set(PPC::X2);
196    }
197  }
198
199  if (PPCFI->needsFP(MF))
200    Reserved.set(PPC::R31);
201
202  if (hasBasePointer(MF))
203    Reserved.set(PPC::R30);
204
205  // Reserve Altivec registers when Altivec is unavailable.
206  if (!Subtarget.hasAltivec())
207    for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
208         IE = PPC::VRRCRegClass.end(); I != IE; ++I)
209      Reserved.set(*I);
210
211  return Reserved;
212}
213
214unsigned
215PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
216                                         MachineFunction &MF) const {
217  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
218  const unsigned DefaultSafety = 1;
219
220  switch (RC->getID()) {
221  default:
222    return 0;
223  case PPC::G8RC_NOX0RegClassID:
224  case PPC::GPRC_NOR0RegClassID:
225  case PPC::G8RCRegClassID:
226  case PPC::GPRCRegClassID: {
227    unsigned FP = TFI->hasFP(MF) ? 1 : 0;
228    return 32 - FP - DefaultSafety;
229  }
230  case PPC::F8RCRegClassID:
231  case PPC::F4RCRegClassID:
232  case PPC::VRRCRegClassID:
233  case PPC::VFRCRegClassID:
234  case PPC::VSLRCRegClassID:
235  case PPC::VSHRCRegClassID:
236    return 32 - DefaultSafety;
237  case PPC::VSRCRegClassID:
238  case PPC::VSFRCRegClassID:
239    return 64 - DefaultSafety;
240  case PPC::CRRCRegClassID:
241    return 8 - DefaultSafety;
242  }
243}
244
245const TargetRegisterClass*
246PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)const {
247  if (Subtarget.hasVSX()) {
248    // With VSX, we can inflate various sub-register classes to the full VSX
249    // register set.
250
251    if (RC == &PPC::F8RCRegClass)
252      return &PPC::VSFRCRegClass;
253    else if (RC == &PPC::VRRCRegClass)
254      return &PPC::VSRCRegClass;
255  }
256
257  return TargetRegisterInfo::getLargestLegalSuperClass(RC);
258}
259
260//===----------------------------------------------------------------------===//
261// Stack Frame Processing methods
262//===----------------------------------------------------------------------===//
263
264/// lowerDynamicAlloc - Generate the code for allocating an object in the
265/// current frame.  The sequence of code with be in the general form
266///
267///   addi   R0, SP, \#frameSize ; get the address of the previous frame
268///   stwxu  R0, SP, Rnegsize   ; add and update the SP with the negated size
269///   addi   Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
270///
271void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
272  // Get the instruction.
273  MachineInstr &MI = *II;
274  // Get the instruction's basic block.
275  MachineBasicBlock &MBB = *MI.getParent();
276  // Get the basic block's function.
277  MachineFunction &MF = *MBB.getParent();
278  // Get the frame info.
279  MachineFrameInfo *MFI = MF.getFrameInfo();
280  // Get the instruction info.
281  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
282  // Determine whether 64-bit pointers are used.
283  bool LP64 = Subtarget.isPPC64();
284  DebugLoc dl = MI.getDebugLoc();
285
286  // Get the maximum call stack size.
287  unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
288  // Get the total frame size.
289  unsigned FrameSize = MFI->getStackSize();
290
291  // Get stack alignments.
292  unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
293  unsigned MaxAlign = MFI->getMaxAlignment();
294  assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
295         "Maximum call-frame size not sufficiently aligned");
296
297  // Determine the previous frame's address.  If FrameSize can't be
298  // represented as 16 bits or we need special alignment, then we load the
299  // previous frame's address from 0(SP).  Why not do an addis of the hi?
300  // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
301  // Constructing the constant and adding would take 3 instructions.
302  // Fortunately, a frame greater than 32K is rare.
303  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
304  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
305  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
306
307  if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
308    BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
309      .addReg(PPC::R31)
310      .addImm(FrameSize);
311  } else if (LP64) {
312    BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
313      .addImm(0)
314      .addReg(PPC::X1);
315  } else {
316    BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
317      .addImm(0)
318      .addReg(PPC::R1);
319  }
320
321  bool KillNegSizeReg = MI.getOperand(1).isKill();
322  unsigned NegSizeReg = MI.getOperand(1).getReg();
323
324  // Grow the stack and update the stack pointer link, then determine the
325  // address of new allocated space.
326  if (LP64) {
327    if (MaxAlign > TargetAlign) {
328      unsigned UnalNegSizeReg = NegSizeReg;
329      NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
330
331      // Unfortunately, there is no andi, only andi., and we can't insert that
332      // here because we might clobber cr0 while it is live.
333      BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
334        .addImm(~(MaxAlign-1));
335
336      unsigned NegSizeReg1 = NegSizeReg;
337      NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
338      BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
339        .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
340        .addReg(NegSizeReg1, RegState::Kill);
341      KillNegSizeReg = true;
342    }
343
344    BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
345      .addReg(Reg, RegState::Kill)
346      .addReg(PPC::X1)
347      .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
348    BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
349      .addReg(PPC::X1)
350      .addImm(maxCallFrameSize);
351  } else {
352    if (MaxAlign > TargetAlign) {
353      unsigned UnalNegSizeReg = NegSizeReg;
354      NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
355
356      // Unfortunately, there is no andi, only andi., and we can't insert that
357      // here because we might clobber cr0 while it is live.
358      BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
359        .addImm(~(MaxAlign-1));
360
361      unsigned NegSizeReg1 = NegSizeReg;
362      NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
363      BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
364        .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
365        .addReg(NegSizeReg1, RegState::Kill);
366      KillNegSizeReg = true;
367    }
368
369    BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
370      .addReg(Reg, RegState::Kill)
371      .addReg(PPC::R1)
372      .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
373    BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
374      .addReg(PPC::R1)
375      .addImm(maxCallFrameSize);
376  }
377
378  // Discard the DYNALLOC instruction.
379  MBB.erase(II);
380}
381
382/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
383/// reserving a whole register (R0), we scrounge for one here. This generates
384/// code like this:
385///
386///   mfcr rA                  ; Move the conditional register into GPR rA.
387///   rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
388///   stw rA, FI               ; Store rA to the frame.
389///
390void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
391                                      unsigned FrameIndex) const {
392  // Get the instruction.
393  MachineInstr &MI = *II;       // ; SPILL_CR <SrcReg>, <offset>
394  // Get the instruction's basic block.
395  MachineBasicBlock &MBB = *MI.getParent();
396  MachineFunction &MF = *MBB.getParent();
397  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
398  DebugLoc dl = MI.getDebugLoc();
399
400  bool LP64 = Subtarget.isPPC64();
401  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
402  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
403
404  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
405  unsigned SrcReg = MI.getOperand(0).getReg();
406
407  // We need to store the CR in the low 4-bits of the saved value. First, issue
408  // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
409  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
410          .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
411
412  // If the saved register wasn't CR0, shift the bits left so that they are in
413  // CR0's slot.
414  if (SrcReg != PPC::CR0) {
415    unsigned Reg1 = Reg;
416    Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
417
418    // rlwinm rA, rA, ShiftBits, 0, 31.
419    BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
420      .addReg(Reg1, RegState::Kill)
421      .addImm(getEncodingValue(SrcReg) * 4)
422      .addImm(0)
423      .addImm(31);
424  }
425
426  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
427                    .addReg(Reg, RegState::Kill),
428                    FrameIndex);
429
430  // Discard the pseudo instruction.
431  MBB.erase(II);
432}
433
434void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
435                                      unsigned FrameIndex) const {
436  // Get the instruction.
437  MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_CR <offset>
438  // Get the instruction's basic block.
439  MachineBasicBlock &MBB = *MI.getParent();
440  MachineFunction &MF = *MBB.getParent();
441  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
442  DebugLoc dl = MI.getDebugLoc();
443
444  bool LP64 = Subtarget.isPPC64();
445  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
446  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
447
448  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
449  unsigned DestReg = MI.getOperand(0).getReg();
450  assert(MI.definesRegister(DestReg) &&
451    "RESTORE_CR does not define its destination");
452
453  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
454                              Reg), FrameIndex);
455
456  // If the reloaded register isn't CR0, shift the bits right so that they are
457  // in the right CR's slot.
458  if (DestReg != PPC::CR0) {
459    unsigned Reg1 = Reg;
460    Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
461
462    unsigned ShiftBits = getEncodingValue(DestReg)*4;
463    // rlwinm r11, r11, 32-ShiftBits, 0, 31.
464    BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
465             .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
466             .addImm(31);
467  }
468
469  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
470             .addReg(Reg, RegState::Kill);
471
472  // Discard the pseudo instruction.
473  MBB.erase(II);
474}
475
476static unsigned getCRFromCRBit(unsigned SrcReg) {
477  unsigned Reg = 0;
478  if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
479      SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
480    Reg = PPC::CR0;
481  else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
482           SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
483    Reg = PPC::CR1;
484  else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
485           SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
486    Reg = PPC::CR2;
487  else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
488           SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
489    Reg = PPC::CR3;
490  else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
491           SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
492    Reg = PPC::CR4;
493  else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
494           SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
495    Reg = PPC::CR5;
496  else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
497           SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
498    Reg = PPC::CR6;
499  else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
500           SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
501    Reg = PPC::CR7;
502
503  assert(Reg != 0 && "Invalid CR bit register");
504  return Reg;
505}
506
507void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
508                                         unsigned FrameIndex) const {
509  // Get the instruction.
510  MachineInstr &MI = *II;       // ; SPILL_CRBIT <SrcReg>, <offset>
511  // Get the instruction's basic block.
512  MachineBasicBlock &MBB = *MI.getParent();
513  MachineFunction &MF = *MBB.getParent();
514  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
515  DebugLoc dl = MI.getDebugLoc();
516
517  bool LP64 = Subtarget.isPPC64();
518  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
519  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
520
521  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
522  unsigned SrcReg = MI.getOperand(0).getReg();
523
524  BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
525          getCRFromCRBit(SrcReg))
526          .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
527
528  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
529          .addReg(getCRFromCRBit(SrcReg));
530
531  // If the saved register wasn't CR0LT, shift the bits left so that the bit to
532  // store is the first one. Mask all but that bit.
533  unsigned Reg1 = Reg;
534  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
535
536  // rlwinm rA, rA, ShiftBits, 0, 0.
537  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
538    .addReg(Reg1, RegState::Kill)
539    .addImm(getEncodingValue(SrcReg))
540    .addImm(0).addImm(0);
541
542  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
543                    .addReg(Reg, RegState::Kill),
544                    FrameIndex);
545
546  // Discard the pseudo instruction.
547  MBB.erase(II);
548}
549
550void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
551                                      unsigned FrameIndex) const {
552  // Get the instruction.
553  MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_CRBIT <offset>
554  // Get the instruction's basic block.
555  MachineBasicBlock &MBB = *MI.getParent();
556  MachineFunction &MF = *MBB.getParent();
557  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
558  DebugLoc dl = MI.getDebugLoc();
559
560  bool LP64 = Subtarget.isPPC64();
561  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
562  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
563
564  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
565  unsigned DestReg = MI.getOperand(0).getReg();
566  assert(MI.definesRegister(DestReg) &&
567    "RESTORE_CRBIT does not define its destination");
568
569  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
570                              Reg), FrameIndex);
571
572  BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
573
574  unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
575  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
576          .addReg(getCRFromCRBit(DestReg));
577
578  unsigned ShiftBits = getEncodingValue(DestReg);
579  // rlwimi r11, r10, 32-ShiftBits, ..., ...
580  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
581           .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill)
582           .addImm(ShiftBits ? 32-ShiftBits : 0)
583           .addImm(ShiftBits).addImm(ShiftBits);
584
585  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
586          getCRFromCRBit(DestReg))
587            .addReg(RegO, RegState::Kill)
588	    // Make sure we have a use dependency all the way through this
589	    // sequence of instructions. We can't have the other bits in the CR
590	    // modified in between the mfocrf and the mtocrf.
591            .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
592
593  // Discard the pseudo instruction.
594  MBB.erase(II);
595}
596
597void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
598                                          unsigned FrameIndex) const {
599  // Get the instruction.
600  MachineInstr &MI = *II;       // ; SPILL_VRSAVE <SrcReg>, <offset>
601  // Get the instruction's basic block.
602  MachineBasicBlock &MBB = *MI.getParent();
603  MachineFunction &MF = *MBB.getParent();
604  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
605  DebugLoc dl = MI.getDebugLoc();
606
607  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
608  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
609  unsigned SrcReg = MI.getOperand(0).getReg();
610
611  BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
612          .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
613
614  addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
615                    .addReg(Reg, RegState::Kill),
616                    FrameIndex);
617
618  // Discard the pseudo instruction.
619  MBB.erase(II);
620}
621
622void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
623                                         unsigned FrameIndex) const {
624  // Get the instruction.
625  MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_VRSAVE <offset>
626  // Get the instruction's basic block.
627  MachineBasicBlock &MBB = *MI.getParent();
628  MachineFunction &MF = *MBB.getParent();
629  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
630  DebugLoc dl = MI.getDebugLoc();
631
632  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
633  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
634  unsigned DestReg = MI.getOperand(0).getReg();
635  assert(MI.definesRegister(DestReg) &&
636    "RESTORE_VRSAVE does not define its destination");
637
638  addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
639                              Reg), FrameIndex);
640
641  BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
642             .addReg(Reg, RegState::Kill);
643
644  // Discard the pseudo instruction.
645  MBB.erase(II);
646}
647
648bool
649PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
650				      unsigned Reg, int &FrameIdx) const {
651
652  // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
653  // ABI, return true to prevent allocating an additional frame slot.
654  // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
655  // is arbitrary and will be subsequently ignored.  For 32-bit, we have
656  // previously created the stack slot if needed, so return its FrameIdx.
657  if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
658    if (Subtarget.isPPC64())
659      FrameIdx = 0;
660    else {
661      const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
662      FrameIdx = FI->getCRSpillFrameIndex();
663    }
664    return true;
665  }
666  return false;
667}
668
669// Figure out if the offset in the instruction must be a multiple of 4.
670// This is true for instructions like "STD".
671static bool usesIXAddr(const MachineInstr &MI) {
672  unsigned OpC = MI.getOpcode();
673
674  switch (OpC) {
675  default:
676    return false;
677  case PPC::LWA:
678  case PPC::LWA_32:
679  case PPC::LD:
680  case PPC::STD:
681    return true;
682  }
683}
684
685// Return the OffsetOperandNo given the FIOperandNum (and the instruction).
686static unsigned getOffsetONFromFION(const MachineInstr &MI,
687                                    unsigned FIOperandNum) {
688  // Take into account whether it's an add or mem instruction
689  unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
690  if (MI.isInlineAsm())
691    OffsetOperandNo = FIOperandNum-1;
692
693  return OffsetOperandNo;
694}
695
696void
697PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
698                                     int SPAdj, unsigned FIOperandNum,
699                                     RegScavenger *RS) const {
700  assert(SPAdj == 0 && "Unexpected");
701
702  // Get the instruction.
703  MachineInstr &MI = *II;
704  // Get the instruction's basic block.
705  MachineBasicBlock &MBB = *MI.getParent();
706  // Get the basic block's function.
707  MachineFunction &MF = *MBB.getParent();
708  // Get the instruction info.
709  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
710  // Get the frame info.
711  MachineFrameInfo *MFI = MF.getFrameInfo();
712  DebugLoc dl = MI.getDebugLoc();
713
714  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
715
716  // Get the frame index.
717  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
718
719  // Get the frame pointer save index.  Users of this index are primarily
720  // DYNALLOC instructions.
721  PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
722  int FPSI = FI->getFramePointerSaveIndex();
723  // Get the instruction opcode.
724  unsigned OpC = MI.getOpcode();
725
726  // Special case for dynamic alloca.
727  if (FPSI && FrameIndex == FPSI &&
728      (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
729    lowerDynamicAlloc(II);
730    return;
731  }
732
733  // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
734  if (OpC == PPC::SPILL_CR) {
735    lowerCRSpilling(II, FrameIndex);
736    return;
737  } else if (OpC == PPC::RESTORE_CR) {
738    lowerCRRestore(II, FrameIndex);
739    return;
740  } else if (OpC == PPC::SPILL_CRBIT) {
741    lowerCRBitSpilling(II, FrameIndex);
742    return;
743  } else if (OpC == PPC::RESTORE_CRBIT) {
744    lowerCRBitRestore(II, FrameIndex);
745    return;
746  } else if (OpC == PPC::SPILL_VRSAVE) {
747    lowerVRSAVESpilling(II, FrameIndex);
748    return;
749  } else if (OpC == PPC::RESTORE_VRSAVE) {
750    lowerVRSAVERestore(II, FrameIndex);
751    return;
752  }
753
754  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
755  MI.getOperand(FIOperandNum).ChangeToRegister(
756    FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
757
758  // Figure out if the offset in the instruction is shifted right two bits.
759  bool isIXAddr = usesIXAddr(MI);
760
761  // If the instruction is not present in ImmToIdxMap, then it has no immediate
762  // form (and must be r+r).
763  bool noImmForm = !MI.isInlineAsm() && !ImmToIdxMap.count(OpC);
764
765  // Now add the frame object offset to the offset from r1.
766  int Offset = MFI->getObjectOffset(FrameIndex);
767  Offset += MI.getOperand(OffsetOperandNo).getImm();
768
769  // If we're not using a Frame Pointer that has been set to the value of the
770  // SP before having the stack size subtracted from it, then add the stack size
771  // to Offset to get the correct offset.
772  // Naked functions have stack size 0, although getStackSize may not reflect that
773  // because we didn't call all the pieces that compute it for naked functions.
774  if (!MF.getFunction()->getAttributes().
775        hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) {
776    if (!(hasBasePointer(MF) && FrameIndex < 0))
777      Offset += MFI->getStackSize();
778  }
779
780  // If we can, encode the offset directly into the instruction.  If this is a
781  // normal PPC "ri" instruction, any 16-bit value can be safely encoded.  If
782  // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
783  // clear can be encoded.  This is extremely uncommon, because normally you
784  // only "std" to a stack slot that is at least 4-byte aligned, but it can
785  // happen in invalid code.
786  assert(OpC != PPC::DBG_VALUE &&
787         "This should be handle in a target independent way");
788  if (!noImmForm && isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
789    MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
790    return;
791  }
792
793  // The offset doesn't fit into a single register, scavenge one to build the
794  // offset in.
795
796  bool is64Bit = Subtarget.isPPC64();
797  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
798  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
799  const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
800  unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
801           SReg = MF.getRegInfo().createVirtualRegister(RC);
802
803  // Insert a set of rA with the full offset value before the ld, st, or add
804  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
805    .addImm(Offset >> 16);
806  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
807    .addReg(SRegHi, RegState::Kill)
808    .addImm(Offset);
809
810  // Convert into indexed form of the instruction:
811  //
812  //   sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
813  //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
814  unsigned OperandBase;
815
816  if (noImmForm)
817    OperandBase = 1;
818  else if (OpC != TargetOpcode::INLINEASM) {
819    assert(ImmToIdxMap.count(OpC) &&
820           "No indexed form of load or store available!");
821    unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
822    MI.setDesc(TII.get(NewOpcode));
823    OperandBase = 1;
824  } else {
825    OperandBase = OffsetOperandNo;
826  }
827
828  unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
829  MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
830  MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
831}
832
833unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
834  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
835
836  if (!Subtarget.isPPC64())
837    return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
838  else
839    return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
840}
841
842unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
843  if (!hasBasePointer(MF))
844    return getFrameRegister(MF);
845
846  return Subtarget.isPPC64() ? PPC::X30 : PPC::R30;
847}
848
849bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
850  if (!EnableBasePointer)
851    return false;
852  if (AlwaysBasePointer)
853    return true;
854
855  // If we need to realign the stack, then the stack pointer can no longer
856  // serve as an offset into the caller's stack space. As a result, we need a
857  // base pointer.
858  return needsStackRealignment(MF);
859}
860
861bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const {
862  if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
863    return false;
864
865  return true;
866}
867
868bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
869  const MachineFrameInfo *MFI = MF.getFrameInfo();
870  const Function *F = MF.getFunction();
871  unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
872  bool requiresRealignment =
873    ((MFI->getMaxAlignment() > StackAlign) ||
874     F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
875                                     Attribute::StackAlignment));
876
877  return requiresRealignment && canRealignStack(MF);
878}
879
880/// Returns true if the instruction's frame index
881/// reference would be better served by a base register other than FP
882/// or SP. Used by LocalStackFrameAllocation to determine which frame index
883/// references it should create new base registers for.
884bool PPCRegisterInfo::
885needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
886  assert(Offset < 0 && "Local offset must be negative");
887
888  unsigned FIOperandNum = 0;
889  while (!MI->getOperand(FIOperandNum).isFI()) {
890    ++FIOperandNum;
891    assert(FIOperandNum < MI->getNumOperands() &&
892           "Instr doesn't have FrameIndex operand!");
893  }
894
895  unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
896  Offset += MI->getOperand(OffsetOperandNo).getImm();
897
898  // It's the load/store FI references that cause issues, as it can be difficult
899  // to materialize the offset if it won't fit in the literal field. Estimate
900  // based on the size of the local frame and some conservative assumptions
901  // about the rest of the stack frame (note, this is pre-regalloc, so
902  // we don't know everything for certain yet) whether this offset is likely
903  // to be out of range of the immediate. Return true if so.
904
905  // We only generate virtual base registers for loads and stores that have
906  // an r+i form. Return false for everything else.
907  unsigned OpC = MI->getOpcode();
908  if (!ImmToIdxMap.count(OpC))
909    return false;
910
911  // Don't generate a new virtual base register just to add zero to it.
912  if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
913      MI->getOperand(2).getImm() == 0)
914    return false;
915
916  MachineBasicBlock &MBB = *MI->getParent();
917  MachineFunction &MF = *MBB.getParent();
918
919  const PPCFrameLowering *PPCFI =
920    static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
921  unsigned StackEst =
922    PPCFI->determineFrameLayout(MF, false, true);
923
924  // If we likely don't need a stack frame, then we probably don't need a
925  // virtual base register either.
926  if (!StackEst)
927    return false;
928
929  // Estimate an offset from the stack pointer.
930  // The incoming offset is relating to the SP at the start of the function,
931  // but when we access the local it'll be relative to the SP after local
932  // allocation, so adjust our SP-relative offset by that allocation size.
933  Offset += StackEst;
934
935  // The frame pointer will point to the end of the stack, so estimate the
936  // offset as the difference between the object offset and the FP location.
937  return !isFrameOffsetLegal(MI, Offset);
938}
939
940/// Insert defining instruction(s) for BaseReg to
941/// be a pointer to FrameIdx at the beginning of the basic block.
942void PPCRegisterInfo::
943materializeFrameBaseRegister(MachineBasicBlock *MBB,
944                             unsigned BaseReg, int FrameIdx,
945                             int64_t Offset) const {
946  unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
947
948  MachineBasicBlock::iterator Ins = MBB->begin();
949  DebugLoc DL;                  // Defaults to "unknown"
950  if (Ins != MBB->end())
951    DL = Ins->getDebugLoc();
952
953  const MachineFunction &MF = *MBB->getParent();
954  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
955  const MCInstrDesc &MCID = TII.get(ADDriOpc);
956  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
957  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
958
959  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
960    .addFrameIndex(FrameIdx).addImm(Offset);
961}
962
963void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
964                                        int64_t Offset) const {
965  unsigned FIOperandNum = 0;
966  while (!MI.getOperand(FIOperandNum).isFI()) {
967    ++FIOperandNum;
968    assert(FIOperandNum < MI.getNumOperands() &&
969           "Instr doesn't have FrameIndex operand!");
970  }
971
972  MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
973  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
974  Offset += MI.getOperand(OffsetOperandNo).getImm();
975  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
976
977  MachineBasicBlock &MBB = *MI.getParent();
978  MachineFunction &MF = *MBB.getParent();
979  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
980  const MCInstrDesc &MCID = MI.getDesc();
981  MachineRegisterInfo &MRI = MF.getRegInfo();
982  MRI.constrainRegClass(BaseReg,
983                        TII.getRegClass(MCID, FIOperandNum, this, MF));
984}
985
986bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
987                                         int64_t Offset) const {
988  return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
989         (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));
990}
991
992