131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// The LLVM Compiler Infrastructure 4f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 9f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 106f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman// This file contains the PowerPC implementation of the TargetRegisterInfo 116f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman// class. 12f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 13f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 14f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 15f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#ifndef POWERPC32_REGISTERINFO_H 16f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#define POWERPC32_REGISTERINFO_H 17f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 182668959b8879097db368aec7d76c455260abc75bChris Lattner#include "PPC.h" 1936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines#include "llvm/ADT/DenseMap.h" 20f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 2173f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng#define GET_REGINFO_HEADER 2273f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng#include "PPCGenRegisterInfo.inc" 2373f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng 24f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukmannamespace llvm { 25804e06704261f233111913a047ef7f7dec1b8725Chris Lattnerclass PPCSubtarget; 26c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Chengclass TargetInstrInfo; 27f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukmanclass Type; 28f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 2921e463b2bf864671a87ebe386cb100ef9349a540Nate Begemanclass PPCRegisterInfo : public PPCGenRegisterInfo { 304345e8040f14781d20fd5fa2f7ee3c75fa611fa1Hal Finkel DenseMap<unsigned, unsigned> ImmToIdxMap; 31804e06704261f233111913a047ef7f7dec1b8725Chris Lattner const PPCSubtarget &Subtarget; 32f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukmanpublic: 3380ada583f3b40ffb201e54cd57c42f9518039c9eBill Wendling PPCRegisterInfo(const PPCSubtarget &SubTarget); 34369503f8412bba4a0138074c97107c09cc4513e0Chris Lattner 35770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng /// getPointerRegClass - Return the register class to use to hold pointers. 36770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng /// This is used for addressing modes. 37dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterClass * 38dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override; 39770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng 40768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel unsigned getRegPressureLimit(const TargetRegisterClass *RC, 41dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineFunction &MF) const override; 42768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel 4336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const TargetRegisterClass* 44dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines getLargestLegalSuperClass(const TargetRegisterClass *RC) const override; 4536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 46f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman /// Code Generation virtual methods... 47dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const MCPhysReg * 48dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines getCalleeSavedRegs(const MachineFunction* MF =nullptr) const override; 49dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const uint32_t *getCallPreservedMask(CallingConv::ID CC) const override; 507ee74a663a3b4d4ee6b55d23362f347ed1d390c2Hal Finkel const uint32_t *getNoPreservedMask() const; 510f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 52dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines BitVector getReservedRegs(const MachineFunction &MF) const override; 53b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 541c6c61a6089fb2bef47de5ee9a5f4acc34047600Hal Finkel /// We require the register scavenger. 55dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool requiresRegisterScavenging(const MachineFunction &MF) const override { 567285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel return true; 577285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel } 587194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 59dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { 601c6c61a6089fb2bef47de5ee9a5f4acc34047600Hal Finkel return true; 611c6c61a6089fb2bef47de5ee9a5f4acc34047600Hal Finkel } 621c6c61a6089fb2bef47de5ee9a5f4acc34047600Hal Finkel 63dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override { 641c6c61a6089fb2bef47de5ee9a5f4acc34047600Hal Finkel return true; 651c6c61a6089fb2bef47de5ee9a5f4acc34047600Hal Finkel } 666a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd 67dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override { 68f6f8198d85f278ff03aaf32c9db6ae0b3826395cHal Finkel return true; 69f6f8198d85f278ff03aaf32c9db6ae0b3826395cHal Finkel } 70f6f8198d85f278ff03aaf32c9db6ae0b3826395cHal Finkel 7102327fefd8a4b7d9f4dc90e066ba70b1d6253c27Hal Finkel void lowerDynamicAlloc(MachineBasicBlock::iterator II) const; 7202327fefd8a4b7d9f4dc90e066ba70b1d6253c27Hal Finkel void lowerCRSpilling(MachineBasicBlock::iterator II, 7302327fefd8a4b7d9f4dc90e066ba70b1d6253c27Hal Finkel unsigned FrameIndex) const; 7402327fefd8a4b7d9f4dc90e066ba70b1d6253c27Hal Finkel void lowerCRRestore(MachineBasicBlock::iterator II, 7502327fefd8a4b7d9f4dc90e066ba70b1d6253c27Hal Finkel unsigned FrameIndex) const; 7636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines void lowerCRBitSpilling(MachineBasicBlock::iterator II, 7736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned FrameIndex) const; 7836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines void lowerCRBitRestore(MachineBasicBlock::iterator II, 7936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned FrameIndex) const; 8002327fefd8a4b7d9f4dc90e066ba70b1d6253c27Hal Finkel void lowerVRSAVESpilling(MachineBasicBlock::iterator II, 8102327fefd8a4b7d9f4dc90e066ba70b1d6253c27Hal Finkel unsigned FrameIndex) const; 8202327fefd8a4b7d9f4dc90e066ba70b1d6253c27Hal Finkel void lowerVRSAVERestore(MachineBasicBlock::iterator II, 8302327fefd8a4b7d9f4dc90e066ba70b1d6253c27Hal Finkel unsigned FrameIndex) const; 8410f7f2a222d0e83dc0c33ad506a7686190c2f7a2Hal Finkel 859d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 86dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines int &FrameIdx) const override; 87fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach void eliminateFrameIndex(MachineBasicBlock::iterator II, 88108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier int SPAdj, unsigned FIOperandNum, 89dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines RegScavenger *RS = nullptr) const override; 90f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 91f6f8198d85f278ff03aaf32c9db6ae0b3826395cHal Finkel // Support for virtual base registers. 92dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; 93f6f8198d85f278ff03aaf32c9db6ae0b3826395cHal Finkel void materializeFrameBaseRegister(MachineBasicBlock *MBB, 94f6f8198d85f278ff03aaf32c9db6ae0b3826395cHal Finkel unsigned BaseReg, int FrameIdx, 95dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines int64_t Offset) const override; 9636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 97dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines int64_t Offset) const override; 98dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool isFrameOffsetLegal(const MachineInstr *MI, 99dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines int64_t Offset) const override; 100f6f8198d85f278ff03aaf32c9db6ae0b3826395cHal Finkel 101a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey // Debug information queries. 102dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned getFrameRegister(const MachineFunction &MF) const override; 10362819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 104fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel // Base pointer (stack realignment) support. 105fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel unsigned getBaseRegister(const MachineFunction &MF) const; 106fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel bool hasBasePointer(const MachineFunction &MF) const; 107fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel bool canRealignStack(const MachineFunction &MF) const; 108dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool needsStackRealignment(const MachineFunction &MF) const override; 109f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman}; 110f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 111f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman} // end namespace llvm 112f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 113f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#endif 114