PPCRegisterInfo.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PowerPC implementation of the TargetRegisterInfo 11// class. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef POWERPC32_REGISTERINFO_H 16#define POWERPC32_REGISTERINFO_H 17 18#include "PPC.h" 19#include "llvm/ADT/DenseMap.h" 20 21#define GET_REGINFO_HEADER 22#include "PPCGenRegisterInfo.inc" 23 24namespace llvm { 25class PPCSubtarget; 26class TargetInstrInfo; 27class Type; 28 29class PPCRegisterInfo : public PPCGenRegisterInfo { 30 DenseMap<unsigned, unsigned> ImmToIdxMap; 31 const PPCSubtarget &Subtarget; 32public: 33 PPCRegisterInfo(const PPCSubtarget &SubTarget); 34 35 /// getPointerRegClass - Return the register class to use to hold pointers. 36 /// This is used for addressing modes. 37 virtual const TargetRegisterClass * 38 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const; 39 40 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 41 MachineFunction &MF) const; 42 43 const TargetRegisterClass* 44 getLargestLegalSuperClass(const TargetRegisterClass *RC) const; 45 46 /// Code Generation virtual methods... 47 const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const; 48 const uint32_t *getCallPreservedMask(CallingConv::ID CC) const; 49 const uint32_t *getNoPreservedMask() const; 50 51 BitVector getReservedRegs(const MachineFunction &MF) const; 52 53 /// We require the register scavenger. 54 bool requiresRegisterScavenging(const MachineFunction &MF) const { 55 return true; 56 } 57 58 bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 59 return true; 60 } 61 62 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 63 return true; 64 } 65 66 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 67 return true; 68 } 69 70 void lowerDynamicAlloc(MachineBasicBlock::iterator II) const; 71 void lowerCRSpilling(MachineBasicBlock::iterator II, 72 unsigned FrameIndex) const; 73 void lowerCRRestore(MachineBasicBlock::iterator II, 74 unsigned FrameIndex) const; 75 void lowerCRBitSpilling(MachineBasicBlock::iterator II, 76 unsigned FrameIndex) const; 77 void lowerCRBitRestore(MachineBasicBlock::iterator II, 78 unsigned FrameIndex) const; 79 void lowerVRSAVESpilling(MachineBasicBlock::iterator II, 80 unsigned FrameIndex) const; 81 void lowerVRSAVERestore(MachineBasicBlock::iterator II, 82 unsigned FrameIndex) const; 83 84 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 85 int &FrameIdx) const; 86 void eliminateFrameIndex(MachineBasicBlock::iterator II, 87 int SPAdj, unsigned FIOperandNum, 88 RegScavenger *RS = NULL) const; 89 90 // Support for virtual base registers. 91 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const; 92 void materializeFrameBaseRegister(MachineBasicBlock *MBB, 93 unsigned BaseReg, int FrameIdx, 94 int64_t Offset) const; 95 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 96 int64_t Offset) const; 97 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const; 98 99 // Debug information queries. 100 unsigned getFrameRegister(const MachineFunction &MF) const; 101 102 // Base pointer (stack realignment) support. 103 unsigned getBaseRegister(const MachineFunction &MF) const; 104 bool hasBasePointer(const MachineFunction &MF) const; 105 bool canRealignStack(const MachineFunction &MF) const; 106 bool needsStackRealignment(const MachineFunction &MF) const; 107}; 108 109} // end namespace llvm 110 111#endif 112