PPCRegisterInfo.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13let Namespace = "PPC" in { 14def sub_lt : SubRegIndex<1>; 15def sub_gt : SubRegIndex<1, 1>; 16def sub_eq : SubRegIndex<1, 2>; 17def sub_un : SubRegIndex<1, 3>; 18def sub_32 : SubRegIndex<32>; 19def sub_64 : SubRegIndex<64>; 20def sub_128 : SubRegIndex<128>; 21} 22 23 24class PPCReg<string n> : Register<n> { 25 let Namespace = "PPC"; 26} 27 28// We identify all our registers with a 5-bit ID, for consistency's sake. 29 30// GPR - One of the 32 32-bit general-purpose registers 31class GPR<bits<5> num, string n> : PPCReg<n> { 32 let HWEncoding{4-0} = num; 33} 34 35// GP8 - One of the 32 64-bit general-purpose registers 36class GP8<GPR SubReg, string n> : PPCReg<n> { 37 let HWEncoding = SubReg.HWEncoding; 38 let SubRegs = [SubReg]; 39 let SubRegIndices = [sub_32]; 40} 41 42// SPR - One of the 32-bit special-purpose registers 43class SPR<bits<10> num, string n> : PPCReg<n> { 44 let HWEncoding{9-0} = num; 45} 46 47// FPR - One of the 32 64-bit floating-point registers 48class FPR<bits<5> num, string n> : PPCReg<n> { 49 let HWEncoding{4-0} = num; 50} 51 52// VF - One of the 32 64-bit floating-point subregisters of the vector 53// registers (used by VSX). 54class VF<bits<5> num, string n> : PPCReg<n> { 55 let HWEncoding{4-0} = num; 56 let HWEncoding{5} = 1; 57} 58 59// VR - One of the 32 128-bit vector registers 60class VR<VF SubReg, string n> : PPCReg<n> { 61 let HWEncoding{4-0} = SubReg.HWEncoding{4-0}; 62 let HWEncoding{5} = 0; 63 let SubRegs = [SubReg]; 64 let SubRegIndices = [sub_64]; 65} 66 67// VSRL - One of the 32 128-bit VSX registers that overlap with the scalar 68// floating-point registers. 69class VSRL<FPR SubReg, string n> : PPCReg<n> { 70 let HWEncoding = SubReg.HWEncoding; 71 let SubRegs = [SubReg]; 72 let SubRegIndices = [sub_64]; 73} 74 75// VSRH - One of the 32 128-bit VSX registers that overlap with the vector 76// registers. 77class VSRH<VR SubReg, string n> : PPCReg<n> { 78 let HWEncoding{4-0} = SubReg.HWEncoding{4-0}; 79 let HWEncoding{5} = 1; 80 let SubRegs = [SubReg]; 81 let SubRegIndices = [sub_128]; 82} 83 84// CR - One of the 8 4-bit condition registers 85class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> { 86 let HWEncoding{2-0} = num; 87 let SubRegs = subregs; 88} 89 90// CRBIT - One of the 32 1-bit condition register fields 91class CRBIT<bits<5> num, string n> : PPCReg<n> { 92 let HWEncoding{4-0} = num; 93} 94 95// General-purpose registers 96foreach Index = 0-31 in { 97 def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>; 98} 99 100// 64-bit General-purpose registers 101foreach Index = 0-31 in { 102 def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>, 103 DwarfRegNum<[Index, -2]>; 104} 105 106// Floating-point registers 107foreach Index = 0-31 in { 108 def F#Index : FPR<Index, "f"#Index>, 109 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>; 110} 111 112// Floating-point vector subregisters (for VSX) 113foreach Index = 0-31 in { 114 def VF#Index : VF<Index, "vs" # !add(Index, 32)>; 115} 116 117// Vector registers 118foreach Index = 0-31 in { 119 def V#Index : VR<!cast<VF>("VF"#Index), "v"#Index>, 120 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>; 121} 122 123// VSX registers 124foreach Index = 0-31 in { 125 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>, 126 DwarfRegAlias<!cast<FPR>("F"#Index)>; 127} 128foreach Index = 0-31 in { 129 def VSH#Index : VSRH<!cast<VR>("V"#Index), "vs" # !add(Index, 32)>, 130 DwarfRegAlias<!cast<VR>("V"#Index)>; 131} 132 133// The reprsentation of r0 when treated as the constant 0. 134def ZERO : GPR<0, "0">; 135def ZERO8 : GP8<ZERO, "0">; 136 137// Representations of the frame pointer used by ISD::FRAMEADDR. 138def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">; 139def FP8 : GP8<FP, "**FRAME POINTER**">; 140 141// Representations of the base pointer used by setjmp. 142def BP : GPR<0 /* arbitrary */, "**BASE POINTER**">; 143def BP8 : GP8<BP, "**BASE POINTER**">; 144 145// Condition register bits 146def CR0LT : CRBIT< 0, "0">; 147def CR0GT : CRBIT< 1, "1">; 148def CR0EQ : CRBIT< 2, "2">; 149def CR0UN : CRBIT< 3, "3">; 150def CR1LT : CRBIT< 4, "4">; 151def CR1GT : CRBIT< 5, "5">; 152def CR1EQ : CRBIT< 6, "6">; 153def CR1UN : CRBIT< 7, "7">; 154def CR2LT : CRBIT< 8, "8">; 155def CR2GT : CRBIT< 9, "9">; 156def CR2EQ : CRBIT<10, "10">; 157def CR2UN : CRBIT<11, "11">; 158def CR3LT : CRBIT<12, "12">; 159def CR3GT : CRBIT<13, "13">; 160def CR3EQ : CRBIT<14, "14">; 161def CR3UN : CRBIT<15, "15">; 162def CR4LT : CRBIT<16, "16">; 163def CR4GT : CRBIT<17, "17">; 164def CR4EQ : CRBIT<18, "18">; 165def CR4UN : CRBIT<19, "19">; 166def CR5LT : CRBIT<20, "20">; 167def CR5GT : CRBIT<21, "21">; 168def CR5EQ : CRBIT<22, "22">; 169def CR5UN : CRBIT<23, "23">; 170def CR6LT : CRBIT<24, "24">; 171def CR6GT : CRBIT<25, "25">; 172def CR6EQ : CRBIT<26, "26">; 173def CR6UN : CRBIT<27, "27">; 174def CR7LT : CRBIT<28, "28">; 175def CR7GT : CRBIT<29, "29">; 176def CR7EQ : CRBIT<30, "30">; 177def CR7UN : CRBIT<31, "31">; 178 179// Condition registers 180let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in { 181def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>; 182def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>; 183def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>; 184def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>; 185def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>; 186def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>; 187def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; 188def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; 189} 190 191// Link register 192def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 193//let Aliases = [LR] in 194def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 195 196// Count register 197def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 198def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 199 200// VRsave register 201def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 202 203// Carry bit. In the architecture this is really bit 0 of the XER register 204// (which really is SPR register 1); this is the only bit interesting to a 205// compiler. 206def CARRY: SPR<1, "ca">; 207 208// FP rounding mode: bits 30 and 31 of the FP status and control register 209// This is not allocated as a normal register; it appears only in 210// Uses and Defs. The ABI says it needs to be preserved by a function, 211// but this is not achieved by saving and restoring it as with 212// most registers, it has to be done in code; to make this work all the 213// return and call instructions are described as Uses of RM, so instructions 214// that do nothing but change RM will not get deleted. 215// Also, in the architecture it is not really a SPR; 512 is arbitrary. 216def RM: SPR<512, "**ROUNDING MODE**">; 217 218/// Register classes 219// Allocate volatiles first 220// then nonvolatiles in reverse order since stmw/lmw save from rN to r31 221def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12), 222 (sequence "R%u", 30, 13), 223 R31, R0, R1, FP, BP)>; 224 225def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12), 226 (sequence "X%u", 30, 14), 227 X31, X13, X0, X1, FP8, BP8)>; 228 229// For some instructions r0 is special (representing the value 0 instead of 230// the value in the r0 register), and we use these register subclasses to 231// prevent r0 from being allocated for use by those instructions. 232def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)>; 233def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)>; 234 235// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4 236// ABI the size of the Floating-point register save area is determined by the 237// allocated non-volatile register with the lowest register number, as FP 238// register N is spilled to offset 8 * (32 - N) below the back chain word of the 239// previous stack frame. By allocating non-volatiles in reverse order we make 240// sure that the Floating-point register save area is always as small as 241// possible because there aren't any unused spill slots. 242def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13), 243 (sequence "F%u", 31, 14))>; 244def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>; 245 246def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128, 247 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11, 248 V12, V13, V14, V15, V16, V17, V18, V19, V31, V30, 249 V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>; 250 251// VSX register classes (the allocation order mirrors that of the corresponding 252// subregister classes). 253def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128, 254 (add (sequence "VSL%u", 0, 13), 255 (sequence "VSL%u", 31, 14))>; 256def VSHRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128, 257 (add VSH2, VSH3, VSH4, VSH5, VSH0, VSH1, VSH6, VSH7, 258 VSH8, VSH9, VSH10, VSH11, VSH12, VSH13, VSH14, 259 VSH15, VSH16, VSH17, VSH18, VSH19, VSH31, VSH30, 260 VSH29, VSH28, VSH27, VSH26, VSH25, VSH24, VSH23, 261 VSH22, VSH21, VSH20)>; 262def VSRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128, 263 (add VSLRC, VSHRC)>; 264 265// Register classes for the 64-bit "scalar" VSX subregisters. 266def VFRC : RegisterClass<"PPC", [f64], 64, 267 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7, 268 VF8, VF9, VF10, VF11, VF12, VF13, VF14, 269 VF15, VF16, VF17, VF18, VF19, VF31, VF30, 270 VF29, VF28, VF27, VF26, VF25, VF24, VF23, 271 VF22, VF21, VF20)>; 272def VSFRC : RegisterClass<"PPC", [f64], 64, (add F8RC, VFRC)>; 273 274def CRBITRC : RegisterClass<"PPC", [i1], 32, 275 (add CR2LT, CR2GT, CR2EQ, CR2UN, 276 CR3LT, CR3GT, CR3EQ, CR3UN, 277 CR4LT, CR4GT, CR4EQ, CR4UN, 278 CR5LT, CR5GT, CR5EQ, CR5UN, 279 CR6LT, CR6GT, CR6EQ, CR6UN, 280 CR7LT, CR7GT, CR7EQ, CR7UN, 281 CR1LT, CR1GT, CR1EQ, CR1UN, 282 CR0LT, CR0GT, CR0EQ, CR0UN)> { 283 let Size = 32; 284} 285 286def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6, 287 CR7, CR2, CR3, CR4)>; 288 289// The CTR registers are not allocatable because they're used by the 290// decrement-and-branch instructions, and thus need to stay live across 291// multiple basic blocks. 292def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> { 293 let isAllocatable = 0; 294} 295def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> { 296 let isAllocatable = 0; 297} 298 299def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>; 300def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> { 301 let CopyCost = -1; 302} 303