PPCScheduleE5500.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- PPCScheduleE500mc.td - e5500 Scheduling Defs -------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the Freescale e5500 64-bit 
11// Power processor.
12// 
13// All information is derived from the "e5500 Core Reference Manual",
14// Freescale Document Number e5500RM, Rev. 1, 03/2012.
15//
16//===----------------------------------------------------------------------===//
17// Relevant functional units in the Freescale e5500 core
18// (These are the same as for the e500mc)
19//
20//  * Decode & Dispatch
21//    Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
22//    queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
23def E5500_DIS0 : FuncUnit;
24def E5500_DIS1 : FuncUnit;
25
26//  * Execute
27//    6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
28//    The CFX has a bypass path, allowing non-divide instructions to execute 
29//    while a divide instruction is being executed.
30def E5500_SFX0  : FuncUnit; // Simple unit 0
31def E5500_SFX1  : FuncUnit; // Simple unit 1
32def E5500_BU    : FuncUnit; // Branch unit
33def E5500_CFX_DivBypass 
34                : FuncUnit; // CFX divide bypass path
35def E5500_CFX_0 : FuncUnit; // CFX pipeline stage 0
36
37def E5500_CFX_1 : FuncUnit; // CFX pipeline stage 1 
38
39def E5500_LSU_0 : FuncUnit; // LSU pipeline
40def E5500_FPU_0 : FuncUnit; // FPU pipeline
41
42def E5500_GPR_Bypass : Bypass;
43def E5500_FPR_Bypass : Bypass;
44def E5500_CR_Bypass  : Bypass;
45
46def PPCE5500Itineraries : ProcessorItineraries<
47  [E5500_DIS0, E5500_DIS1, E5500_SFX0, E5500_SFX1, E5500_BU,
48   E5500_CFX_DivBypass, E5500_CFX_0, E5500_CFX_1,
49   E5500_LSU_0, E5500_FPU_0],
50  [E5500_CR_Bypass, E5500_GPR_Bypass, E5500_FPR_Bypass], [
51  InstrItinData<IIC_IntSimple,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
52                                  InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
53                                 [5, 2, 2], // Latency = 1
54                                 [E5500_GPR_Bypass,
55                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
56  InstrItinData<IIC_IntGeneral,  [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
57                                  InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
58                                 [5, 2, 2], // Latency = 1
59                                 [E5500_GPR_Bypass,
60                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
61  InstrItinData<IIC_IntCompare,  [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
62                                  InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
63                                 [6, 2, 2], // Latency = 1 or 2
64                                 [E5500_CR_Bypass,
65                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
66  InstrItinData<IIC_IntDivD,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
67                                  InstrStage<1, [E5500_CFX_0], 0>,
68                                  InstrStage<26, [E5500_CFX_DivBypass]>],
69                                 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
70                                 [E5500_GPR_Bypass,
71                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
72  InstrItinData<IIC_IntDivW,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
73                                  InstrStage<1, [E5500_CFX_0], 0>,
74                                  InstrStage<16, [E5500_CFX_DivBypass]>],
75                                 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
76                                 [E5500_GPR_Bypass,
77                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
78  InstrItinData<IIC_IntMFFS,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
79                                  InstrStage<1, [E5500_FPU_0]>],
80                                 [11], // Latency = 7, Repeat rate = 1
81                                 [E5500_FPR_Bypass]>,
82  InstrItinData<IIC_IntMTFSB0,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
83                                  InstrStage<7, [E5500_FPU_0]>],
84                                 [11, 2, 2], // Latency = 7, Repeat rate = 7
85                                 [NoBypass, NoBypass, NoBypass]>,
86  InstrItinData<IIC_IntMulHD,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
87                                  InstrStage<1, [E5500_CFX_0], 0>,
88                                  InstrStage<2, [E5500_CFX_1]>],
89                                 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
90                                 [E5500_GPR_Bypass,
91                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
92  InstrItinData<IIC_IntMulHW,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
93                                  InstrStage<1, [E5500_CFX_0], 0>,
94                                  InstrStage<1, [E5500_CFX_1]>],
95                                 [8, 2, 2], // Latency = 4, Repeat rate = 1
96                                 [E5500_GPR_Bypass,
97                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
98  InstrItinData<IIC_IntMulHWU,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
99                                  InstrStage<1, [E5500_CFX_0], 0>,
100                                  InstrStage<1, [E5500_CFX_1]>],
101                                 [8, 2, 2], // Latency = 4, Repeat rate = 1
102                                 [E5500_GPR_Bypass,
103                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
104  InstrItinData<IIC_IntMulLI,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
105                                  InstrStage<1, [E5500_CFX_0], 0>,
106                                  InstrStage<2, [E5500_CFX_1]>],
107                                 [8, 2, 2], // Latency = 4 or 5, Repeat = 2
108                                 [E5500_GPR_Bypass,
109                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
110  InstrItinData<IIC_IntRotate,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
111                                  InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
112                                 [5, 2, 2], // Latency = 1
113                                 [E5500_GPR_Bypass,
114                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
115  InstrItinData<IIC_IntRotateD,  [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
116                                  InstrStage<2, [E5500_SFX0, E5500_SFX1]>],
117                                 [6, 2, 2], // Latency = 2, Repeat rate = 2
118                                 [E5500_GPR_Bypass,
119                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
120  InstrItinData<IIC_IntRotateDI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
121                                  InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
122                                 [5, 2, 2], // Latency = 1, Repeat rate = 1
123                                 [E5500_GPR_Bypass,
124                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
125  InstrItinData<IIC_IntShift,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
126                                  InstrStage<2, [E5500_SFX0, E5500_SFX1]>],
127                                 [6, 2, 2], // Latency = 2, Repeat rate = 2
128                                 [E5500_GPR_Bypass,
129                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
130  InstrItinData<IIC_IntTrapW,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
131                                  InstrStage<2, [E5500_SFX0]>],
132                                 [6, 2], // Latency = 2, Repeat rate = 2
133                                 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
134  InstrItinData<IIC_BrB,         [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
135                                  InstrStage<1, [E5500_BU]>],
136                                 [5, 2], // Latency = 1
137                                 [NoBypass, E5500_GPR_Bypass]>,
138  InstrItinData<IIC_BrCR,        [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
139                                  InstrStage<1, [E5500_BU]>],
140                                 [5, 2, 2], // Latency = 1
141                                 [E5500_CR_Bypass,
142                                  E5500_CR_Bypass, E5500_CR_Bypass]>,
143  InstrItinData<IIC_BrMCR,       [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
144                                  InstrStage<1, [E5500_BU]>],
145                                 [5, 2], // Latency = 1
146                                 [E5500_CR_Bypass, E5500_CR_Bypass]>,
147  InstrItinData<IIC_BrMCRX,      [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
148                                  InstrStage<1, [E5500_CFX_0]>],
149                                 [5, 2, 2], // Latency = 1
150                                 [E5500_CR_Bypass, E5500_GPR_Bypass]>,
151  InstrItinData<IIC_LdStDCBA,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
152                                  InstrStage<1, [E5500_LSU_0]>],
153                                 [7, 2], // Latency = 3, Repeat rate = 1
154                                 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
155  InstrItinData<IIC_LdStDCBF,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
156                                  InstrStage<1, [E5500_LSU_0]>],
157                                 [7, 2], // Latency = 3, Repeat rate = 1
158                                 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
159  InstrItinData<IIC_LdStDCBI,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
160                                  InstrStage<1, [E5500_LSU_0]>],
161                                 [7, 2], // Latency = 3, Repeat rate = 1
162                                 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
163  InstrItinData<IIC_LdStLoad,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
164                                  InstrStage<1, [E5500_LSU_0]>],
165                                 [7, 2], // Latency = 3
166                                 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
167  InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
168                                  InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
169                                  InstrStage<1, [E5500_LSU_0]>],
170                                 [7, 2], // Latency = 3, Repeat rate = 1
171                                 [E5500_GPR_Bypass, E5500_GPR_Bypass],
172                                 2>, // 2 micro-ops
173  InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
174                                  InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
175                                  InstrStage<1, [E5500_LSU_0]>],
176                                 [7, 2], // Latency = 3, Repeat rate = 1
177                                 [E5500_GPR_Bypass, E5500_GPR_Bypass],
178                                 2>, // 2 micro-ops
179  InstrItinData<IIC_LdStLD,      [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
180                                  InstrStage<1, [E5500_LSU_0]>],
181                                 [7, 2], // Latency = 3, Repeat rate = 1
182                                 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
183  InstrItinData<IIC_LdStLDARX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
184                                  InstrStage<3, [E5500_LSU_0]>],
185                                 [7, 2], // Latency = 3, Repeat rate = 3
186                                 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
187  InstrItinData<IIC_LdStLDU,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
188                                  InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
189                                  InstrStage<1, [E5500_LSU_0]>],
190                                 [7, 2], // Latency = 3, Repeat rate = 1
191                                 [E5500_GPR_Bypass, E5500_GPR_Bypass],
192                                 2>, // 2 micro-ops
193  InstrItinData<IIC_LdStLDUX,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
194                                  InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
195                                  InstrStage<1, [E5500_LSU_0]>],
196                                 [7, 2], // Latency = 3, Repeat rate = 1
197                                 [E5500_GPR_Bypass, E5500_GPR_Bypass],
198                                 2>, // 2 micro-ops
199  InstrItinData<IIC_LdStStore,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
200                                  InstrStage<1, [E5500_LSU_0]>],
201                                 [7, 2], // Latency = 3, Repeat rate = 1
202                                 [NoBypass, E5500_GPR_Bypass]>,
203  InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
204                                  InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
205                                  InstrStage<1, [E5500_LSU_0]>],
206                                 [7, 2], // Latency = 3, Repeat rate = 1
207                                 [NoBypass, E5500_GPR_Bypass],
208                                 2>, // 2 micro-ops
209  InstrItinData<IIC_LdStICBI,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
210                                  InstrStage<1, [E5500_LSU_0]>],
211                                 [7, 2], // Latency = 3, Repeat rate = 1
212                                 [NoBypass, E5500_GPR_Bypass]>,
213  InstrItinData<IIC_LdStSTFD,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
214                                  InstrStage<1, [E5500_LSU_0]>],
215                                 [7, 2, 2], // Latency = 3, Repeat rate = 1
216                                 [E5500_GPR_Bypass,
217                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
218  InstrItinData<IIC_LdStSTFDU,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
219                                  InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
220                                  InstrStage<1, [E5500_LSU_0]>],
221                                 [7, 2, 2], // Latency = 3, Repeat rate = 1
222                                 [E5500_GPR_Bypass,
223                                  E5500_GPR_Bypass, E5500_GPR_Bypass],
224                                 2>, // 2 micro-ops
225  InstrItinData<IIC_LdStLFD,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
226                                  InstrStage<1, [E5500_LSU_0]>],
227                                 [8, 2, 2], // Latency = 4, Repeat rate = 1
228                                 [E5500_FPR_Bypass,
229                                  E5500_GPR_Bypass, E5500_GPR_Bypass],
230                                 2>, // 2 micro-ops
231  InstrItinData<IIC_LdStLFDU,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
232                                  InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
233                                  InstrStage<1, [E5500_LSU_0]>],
234                                 [8, 2, 2], // Latency = 4, Repeat rate = 1
235                                 [E5500_FPR_Bypass,
236                                  E5500_GPR_Bypass, E5500_GPR_Bypass],
237                                 2>, // 2 micro-ops
238  InstrItinData<IIC_LdStLFDUX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
239                                  InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
240                                  InstrStage<1, [E5500_LSU_0]>],
241                                 [8, 2, 2], // Latency = 4, Repeat rate = 1
242                                 [E5500_FPR_Bypass,
243                                  E5500_GPR_Bypass, E5500_GPR_Bypass],
244                                 2>, // 2 micro-ops
245  InstrItinData<IIC_LdStLHA,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
246                                  InstrStage<1, [E5500_LSU_0]>],
247                                 [7, 2], // Latency = 3
248                                 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
249  InstrItinData<IIC_LdStLHAU,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
250                                  InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
251                                  InstrStage<1, [E5500_LSU_0]>],
252                                 [7, 2], // Latency = 3, Repeat rate = 1
253                                 [E5500_GPR_Bypass, E5500_GPR_Bypass],
254                                 2>, // 2 micro-ops
255  InstrItinData<IIC_LdStLHAUX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
256                                  InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
257                                  InstrStage<1, [E5500_LSU_0]>],
258                                 [7, 2], // Latency = 3, Repeat rate = 1
259                                 [E5500_GPR_Bypass, E5500_GPR_Bypass],
260                                 2>, // 2 micro-ops
261  InstrItinData<IIC_LdStLMW,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
262                                  InstrStage<4, [E5500_LSU_0]>],
263                                 [8, 2], // Latency = r+3, Repeat rate = r+3
264                                 [NoBypass, E5500_GPR_Bypass]>,
265  InstrItinData<IIC_LdStLWARX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
266                                  InstrStage<3, [E5500_LSU_0]>],
267                                 [7, 2, 2], // Latency = 3, Repeat rate = 3
268                                 [E5500_GPR_Bypass,
269                                  E5500_GPR_Bypass, E5500_GPR_Bypass]>,
270  InstrItinData<IIC_LdStSTD,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
271                                  InstrStage<1, [E5500_LSU_0]>],
272                                 [7, 2], // Latency = 3, Repeat rate = 1
273                                 [NoBypass, E5500_GPR_Bypass]>,
274  InstrItinData<IIC_LdStSTDCX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
275                                  InstrStage<1, [E5500_LSU_0]>],
276                                 [7, 2], // Latency = 3, Repeat rate = 1
277                                 [NoBypass, E5500_GPR_Bypass]>,
278  InstrItinData<IIC_LdStSTDU,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
279                                  InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
280                                  InstrStage<1, [E5500_LSU_0]>],
281                                 [7, 2], // Latency = 3, Repeat rate = 1
282                                 [NoBypass, E5500_GPR_Bypass],
283                                 2>, // 2 micro-ops
284  InstrItinData<IIC_LdStSTDUX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
285                                  InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
286                                  InstrStage<1, [E5500_LSU_0]>],
287                                 [7, 2], // Latency = 3, Repeat rate = 1
288                                 [NoBypass, E5500_GPR_Bypass],
289                                 2>, // 2 micro-ops
290  InstrItinData<IIC_LdStSTWCX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
291                                  InstrStage<1, [E5500_LSU_0]>],
292                                 [7, 2], // Latency = 3, Repeat rate = 1
293                                 [NoBypass, E5500_GPR_Bypass]>,
294  InstrItinData<IIC_LdStSync,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
295                                  InstrStage<1, [E5500_LSU_0]>]>,
296  InstrItinData<IIC_SprMTMSR,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
297                                  InstrStage<2, [E5500_CFX_0]>],
298                                 [6, 2], // Latency = 2, Repeat rate = 4
299                                 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
300  InstrItinData<IIC_SprTLBSYNC,  [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
301                                  InstrStage<1, [E5500_LSU_0], 0>]>,
302  InstrItinData<IIC_SprMFCR,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
303                                  InstrStage<5, [E5500_CFX_0]>],
304                                 [9, 2], // Latency = 5, Repeat rate = 5
305                                 [E5500_GPR_Bypass, E5500_CR_Bypass]>,
306  InstrItinData<IIC_SprMFCRF,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
307                                  InstrStage<5, [E5500_CFX_0]>],
308                                 [9, 2], // Latency = 5, Repeat rate = 5
309                                 [E5500_GPR_Bypass, E5500_CR_Bypass]>,
310  InstrItinData<IIC_SprMFMSR,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
311                                  InstrStage<4, [E5500_SFX0]>],
312                                 [8, 2], // Latency = 4, Repeat rate = 4
313                                 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
314  InstrItinData<IIC_SprMFSPR,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
315                                  InstrStage<1, [E5500_CFX_0]>],
316                                 [5], // Latency = 1, Repeat rate = 1
317                                 [E5500_GPR_Bypass]>,
318  InstrItinData<IIC_SprMFTB,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
319                                  InstrStage<4, [E5500_CFX_0]>],
320                                 [8, 2], // Latency = 4, Repeat rate = 4
321                                 [NoBypass, E5500_GPR_Bypass]>,
322  InstrItinData<IIC_SprMTSPR,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
323                                  InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
324                                 [5], // Latency = 1, Repeat rate = 1
325                                 [E5500_GPR_Bypass]>,
326  InstrItinData<IIC_FPGeneral,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
327                                  InstrStage<1, [E5500_FPU_0]>],
328                                 [11, 2, 2], // Latency = 7, Repeat rate = 1 
329                                 [E5500_FPR_Bypass,
330                                  E5500_FPR_Bypass, E5500_FPR_Bypass]>,
331  InstrItinData<IIC_FPAddSub,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
332                                  InstrStage<1, [E5500_FPU_0]>],
333                                 [11, 2, 2], // Latency = 7, Repeat rate = 1 
334                                 [E5500_FPR_Bypass,
335                                  E5500_FPR_Bypass, E5500_FPR_Bypass]>,
336  InstrItinData<IIC_FPCompare,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
337                                  InstrStage<1, [E5500_FPU_0]>],
338                                 [11, 2, 2], // Latency = 7, Repeat rate = 1
339                                 [E5500_CR_Bypass,
340                                  E5500_FPR_Bypass, E5500_FPR_Bypass]>,
341  InstrItinData<IIC_FPDivD,      [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
342                                  InstrStage<31, [E5500_FPU_0]>],
343                                 [39, 2, 2], // Latency = 35, Repeat rate = 31
344                                 [E5500_FPR_Bypass,
345                                  E5500_FPR_Bypass, E5500_FPR_Bypass]>,
346  InstrItinData<IIC_FPDivS,      [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
347                                  InstrStage<16, [E5500_FPU_0]>],
348                                 [24, 2, 2], // Latency = 20, Repeat rate = 16 
349                                 [E5500_FPR_Bypass,
350                                  E5500_FPR_Bypass, E5500_FPR_Bypass]>,
351  InstrItinData<IIC_FPFused,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
352                                  InstrStage<1, [E5500_FPU_0]>],
353                                 [11, 2, 2, 2], // Latency = 7, Repeat rate = 1
354                                 [E5500_FPR_Bypass,
355                                  E5500_FPR_Bypass, E5500_FPR_Bypass,
356                                  E5500_FPR_Bypass]>,
357  InstrItinData<IIC_FPRes,       [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
358                                  InstrStage<2, [E5500_FPU_0]>],
359                                 [12, 2], // Latency = 8, Repeat rate = 2
360                                 [E5500_FPR_Bypass, E5500_FPR_Bypass]>
361]>;
362
363// ===---------------------------------------------------------------------===//
364// e5500 machine model for scheduling and other instruction cost heuristics.
365
366def PPCE5500Model : SchedMachineModel {
367  let IssueWidth = 2;  // 2 micro-ops are dispatched per cycle.
368  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
369  let LoadLatency = 6; // Optimistic load latency assuming bypass.
370                       // This is overriden by OperandCycles if the
371                       // Itineraries are queried instead.
372
373  let Itineraries = PPCE5500Itineraries;
374}
375