PPCScheduleG4.td revision 928eb49cae286c95dceecf4442997dd561c6e3b7 
1//===- PPCScheduleG4.td - PPC G4 Scheduling Definitions ----*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the G4 (7400) processor.
11//
12//===----------------------------------------------------------------------===//
13
14def G4Itineraries : ProcessorItineraries<
15  [IU1, IU2, SLU, SRU, BPU, FPU1, VIU1, VIU2, VPU, VFPU], [
16  InstrItinData<IntGeneral  , [InstrStage<1, [IU1, IU2]>]>,
17  InstrItinData<IntCompare  , [InstrStage<1, [IU1, IU2]>]>,
18  InstrItinData<IntDivW     , [InstrStage<19, [IU1]>]>,
19  InstrItinData<IntMFFS     , [InstrStage<3, [FPU1]>]>,
20  InstrItinData<IntMFVSCR   , [InstrStage<1, [VIU1]>]>,
21  InstrItinData<IntMTFSB0   , [InstrStage<3, [FPU1]>]>,
22  InstrItinData<IntMulHW    , [InstrStage<5, [IU1]>]>,
23  InstrItinData<IntMulHWU   , [InstrStage<6, [IU1]>]>,
24  InstrItinData<IntMulLI    , [InstrStage<3, [IU1]>]>,
25  InstrItinData<IntRotate   , [InstrStage<1, [IU1, IU2]>]>,
26  InstrItinData<IntShift    , [InstrStage<1, [IU1, IU2]>]>,
27  InstrItinData<IntTrapW    , [InstrStage<2, [IU1, IU2]>]>,
28  InstrItinData<BrB         , [InstrStage<1, [BPU]>]>,
29  InstrItinData<BrCR        , [InstrStage<1, [SRU]>]>,
30  InstrItinData<BrMCR       , [InstrStage<1, [SRU]>]>,
31  InstrItinData<BrMCRX      , [InstrStage<1, [SRU]>]>,
32  InstrItinData<LdStDCBF    , [InstrStage<2, [SLU]>]>,
33  InstrItinData<LdStDCBI    , [InstrStage<2, [SLU]>]>,
34  InstrItinData<LdStGeneral , [InstrStage<2, [SLU]>]>,
35  InstrItinData<LdStDSS     , [InstrStage<2, [SLU]>]>,
36  InstrItinData<LdStICBI    , [InstrStage<2, [SLU]>]>,
37  InstrItinData<LdStUX      , [InstrStage<2, [SLU]>]>,
38  InstrItinData<LdStLFD     , [InstrStage<2, [SLU]>]>,
39  InstrItinData<LdStLFDU    , [InstrStage<2, [SLU]>]>,
40  InstrItinData<LdStLHA     , [InstrStage<2, [SLU]>]>,
41  InstrItinData<LdStLMW     , [InstrStage<34, [SLU]>]>,
42  InstrItinData<LdStLVecX   , [InstrStage<2, [SLU]>]>,
43  InstrItinData<LdStLWARX   , [InstrStage<3, [SLU]>]>,
44  InstrItinData<LdStSTVEBX  , [InstrStage<2, [SLU]>]>,
45  InstrItinData<LdStSTWCX   , [InstrStage<5, [SLU]>]>,
46  InstrItinData<LdStSync    , [InstrStage<8, [SLU]>]>,
47  InstrItinData<SprISYNC    , [InstrStage<2, [SRU]>]>,
48  InstrItinData<SprMFSR     , [InstrStage<3, [SRU]>]>,
49  InstrItinData<SprMTMSR    , [InstrStage<1, [SRU]>]>,
50  InstrItinData<SprMTSR     , [InstrStage<2, [SRU]>]>,
51  InstrItinData<SprTLBSYNC  , [InstrStage<8, [SRU]>]>,
52  InstrItinData<SprMFCR     , [InstrStage<1, [SRU]>]>,
53  InstrItinData<SprMFMSR    , [InstrStage<1, [SRU]>]>,
54  InstrItinData<SprMFSPR    , [InstrStage<3, [SRU]>]>,
55  InstrItinData<SprMFTB     , [InstrStage<1, [SRU]>]>,
56  InstrItinData<SprMTSPR    , [InstrStage<2, [SRU]>]>,
57  InstrItinData<SprMTSRIN   , [InstrStage<2, [SRU]>]>,
58  InstrItinData<SprRFI      , [InstrStage<2, [SRU]>]>,
59  InstrItinData<SprSC       , [InstrStage<2, [SRU]>]>,
60  InstrItinData<FPGeneral   , [InstrStage<1, [FPU1]>]>,
61  InstrItinData<FPCompare   , [InstrStage<1, [FPU1]>]>,
62  InstrItinData<FPDivD      , [InstrStage<31, [FPU1]>]>,
63  InstrItinData<FPDivS      , [InstrStage<17, [FPU1]>]>,
64  InstrItinData<FPFused     , [InstrStage<1, [FPU1]>]>,
65  InstrItinData<FPRes       , [InstrStage<10, [FPU1]>]>,
66  InstrItinData<VecGeneral  , [InstrStage<1, [VIU1]>]>,
67  InstrItinData<VecFP       , [InstrStage<4, [VFPU]>]>,
68  InstrItinData<VecFPCompare, [InstrStage<1, [VIU1]>]>,
69  InstrItinData<VecComplex  , [InstrStage<3, [VIU2]>]>,
70  InstrItinData<VecPerm     , [InstrStage<1, [VPU]>]>,
71  InstrItinData<VecFPRound  , [InstrStage<4, [VFPU]>]>,
72  InstrItinData<VecVSL      , [InstrStage<1, [VIU1]>]>,
73  InstrItinData<VecVSR      , [InstrStage<1, [VIU1]>]>
74]>;
75