1//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the PPC specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCSubtarget.h"
15#include "PPC.h"
16#include "PPCRegisterInfo.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineScheduler.h"
19#include "llvm/IR/Attributes.h"
20#include "llvm/IR/Function.h"
21#include "llvm/IR/GlobalValue.h"
22#include "llvm/Support/Host.h"
23#include "llvm/Support/TargetRegistry.h"
24#include "llvm/Target/TargetMachine.h"
25#include <cstdlib>
26
27using namespace llvm;
28
29#define DEBUG_TYPE "ppc-subtarget"
30
31#define GET_SUBTARGETINFO_TARGET_DESC
32#define GET_SUBTARGETINFO_CTOR
33#include "PPCGenSubtargetInfo.inc"
34
35/// Return the datalayout string of a subtarget.
36static std::string getDataLayoutString(const PPCSubtarget &ST) {
37  const Triple &T = ST.getTargetTriple();
38
39  std::string Ret;
40
41  // Most PPC* platforms are big endian, PPC64LE is little endian.
42  if (ST.isLittleEndian())
43    Ret = "e";
44  else
45    Ret = "E";
46
47  Ret += DataLayout::getManglingComponent(T);
48
49  // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
50  // pointers.
51  if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
52    Ret += "-p:32:32";
53
54  // Note, the alignment values for f64 and i64 on ppc64 in Darwin
55  // documentation are wrong; these are correct (i.e. "what gcc does").
56  if (ST.isPPC64() || ST.isSVR4ABI())
57    Ret += "-i64:64";
58  else
59    Ret += "-f64:32:64";
60
61  // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
62  if (ST.isPPC64())
63    Ret += "-n32:64";
64  else
65    Ret += "-n32";
66
67  return Ret;
68}
69
70PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
71                                                            StringRef FS) {
72  initializeEnvironment();
73  resetSubtargetFeatures(CPU, FS);
74  return *this;
75}
76
77PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
78                           const std::string &FS, PPCTargetMachine &TM,
79                           bool is64Bit, CodeGenOpt::Level OptLevel)
80    : PPCGenSubtargetInfo(TT, CPU, FS), IsPPC64(is64Bit), TargetTriple(TT),
81      OptLevel(OptLevel),
82      FrameLowering(initializeSubtargetDependencies(CPU, FS)),
83      DL(getDataLayoutString(*this)), InstrInfo(*this), JITInfo(*this),
84      TLInfo(TM), TSInfo(&DL) {}
85
86/// SetJITMode - This is called to inform the subtarget info that we are
87/// producing code for the JIT.
88void PPCSubtarget::SetJITMode() {
89  // JIT mode doesn't want lazy resolver stubs, it knows exactly where
90  // everything is.  This matters for PPC64, which codegens in PIC mode without
91  // stubs.
92  HasLazyResolverStubs = false;
93
94  // Calls to external functions need to use indirect calls
95  IsJITCodeModel = true;
96}
97
98void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
99  AttributeSet FnAttrs = MF->getFunction()->getAttributes();
100  Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
101                                           "target-cpu");
102  Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
103                                          "target-features");
104  std::string CPU =
105    !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
106  std::string FS =
107    !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
108  if (!FS.empty()) {
109    initializeEnvironment();
110    resetSubtargetFeatures(CPU, FS);
111  }
112}
113
114void PPCSubtarget::initializeEnvironment() {
115  StackAlignment = 16;
116  DarwinDirective = PPC::DIR_NONE;
117  HasMFOCRF = false;
118  Has64BitSupport = false;
119  Use64BitRegs = false;
120  UseCRBits = false;
121  HasAltivec = false;
122  HasQPX = false;
123  HasVSX = false;
124  HasFCPSGN = false;
125  HasFSQRT = false;
126  HasFRE = false;
127  HasFRES = false;
128  HasFRSQRTE = false;
129  HasFRSQRTES = false;
130  HasRecipPrec = false;
131  HasSTFIWX = false;
132  HasLFIWAX = false;
133  HasFPRND = false;
134  HasFPCVT = false;
135  HasISEL = false;
136  HasPOPCNTD = false;
137  HasLDBRX = false;
138  IsBookE = false;
139  DeprecatedMFTB = false;
140  DeprecatedDST = false;
141  HasLazyResolverStubs = false;
142  IsJITCodeModel = false;
143}
144
145void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
146  // Determine default and user specified characteristics
147  std::string CPUName = CPU;
148  if (CPUName.empty())
149    CPUName = "generic";
150#if (defined(__APPLE__) || defined(__linux__)) && \
151    (defined(__ppc__) || defined(__powerpc__))
152  if (CPUName == "generic")
153    CPUName = sys::getHostCPUName();
154#endif
155
156  // Initialize scheduling itinerary for the specified CPU.
157  InstrItins = getInstrItineraryForCPU(CPUName);
158
159  // Make sure 64-bit features are available when CPUname is generic
160  std::string FullFS = FS;
161
162  // If we are generating code for ppc64, verify that options make sense.
163  if (IsPPC64) {
164    Has64BitSupport = true;
165    // Silently force 64-bit register use on ppc64.
166    Use64BitRegs = true;
167    if (!FullFS.empty())
168      FullFS = "+64bit," + FullFS;
169    else
170      FullFS = "+64bit";
171  }
172
173  // At -O2 and above, track CR bits as individual registers.
174  if (OptLevel >= CodeGenOpt::Default) {
175    if (!FullFS.empty())
176      FullFS = "+crbits," + FullFS;
177    else
178      FullFS = "+crbits";
179  }
180
181  // Parse features string.
182  ParseSubtargetFeatures(CPUName, FullFS);
183
184  // If the user requested use of 64-bit regs, but the cpu selected doesn't
185  // support it, ignore.
186  if (use64BitRegs() && !has64BitSupport())
187    Use64BitRegs = false;
188
189  // Set up darwin-specific properties.
190  if (isDarwin())
191    HasLazyResolverStubs = true;
192
193  // QPX requires a 32-byte aligned stack. Note that we need to do this if
194  // we're compiling for a BG/Q system regardless of whether or not QPX
195  // is enabled because external functions will assume this alignment.
196  if (hasQPX() || isBGQ())
197    StackAlignment = 32;
198
199  // Determine endianness.
200  IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
201
202  // FIXME: For now, we disable VSX in little-endian mode until endian
203  // issues in those instructions can be addressed.
204  if (IsLittleEndian)
205    HasVSX = false;
206}
207
208/// hasLazyResolverStub - Return true if accesses to the specified global have
209/// to go through a dyld lazy resolution stub.  This means that an extra load
210/// is required to get the address of the global.
211bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
212                                       const TargetMachine &TM) const {
213  // We never have stubs if HasLazyResolverStubs=false or if in static mode.
214  if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
215    return false;
216  // If symbol visibility is hidden, the extra load is not needed if
217  // the symbol is definitely defined in the current translation unit.
218  bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
219  if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
220    return false;
221  return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
222         GV->hasCommonLinkage() || isDecl;
223}
224
225bool PPCSubtarget::enablePostRAScheduler(
226           CodeGenOpt::Level OptLevel,
227           TargetSubtargetInfo::AntiDepBreakMode& Mode,
228           RegClassVector& CriticalPathRCs) const {
229  Mode = TargetSubtargetInfo::ANTIDEP_ALL;
230
231  CriticalPathRCs.clear();
232
233  if (isPPC64())
234    CriticalPathRCs.push_back(&PPC::G8RCRegClass);
235  else
236    CriticalPathRCs.push_back(&PPC::GPRCRegClass);
237
238  return OptLevel >= CodeGenOpt::Default;
239}
240
241// Embedded cores need aggressive scheduling (and some others also benefit).
242static bool needsAggressiveScheduling(unsigned Directive) {
243  switch (Directive) {
244  default: return false;
245  case PPC::DIR_440:
246  case PPC::DIR_A2:
247  case PPC::DIR_E500mc:
248  case PPC::DIR_E5500:
249  case PPC::DIR_PWR7:
250  case PPC::DIR_PWR8:
251    return true;
252  }
253}
254
255bool PPCSubtarget::enableMachineScheduler() const {
256  // Enable MI scheduling for the embedded cores.
257  // FIXME: Enable this for all cores (some additional modeling
258  // may be necessary).
259  return needsAggressiveScheduling(DarwinDirective);
260}
261
262void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
263                                       MachineInstr *begin,
264                                       MachineInstr *end,
265                                       unsigned NumRegionInstrs) const {
266  if (needsAggressiveScheduling(DarwinDirective)) {
267    Policy.OnlyTopDown = false;
268    Policy.OnlyBottomUp = false;
269  }
270
271  // Spilling is generally expensive on all PPC cores, so always enable
272  // register-pressure tracking.
273  Policy.ShouldTrackPressure = true;
274}
275
276bool PPCSubtarget::useAA() const {
277  // Use AA during code generation for the embedded cores.
278  return needsAggressiveScheduling(DarwinDirective);
279}
280
281