PPCSubtarget.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the PPC specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCSubtarget.h"
15#include "PPC.h"
16#include "PPCRegisterInfo.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineScheduler.h"
19#include "llvm/IR/Attributes.h"
20#include "llvm/IR/Function.h"
21#include "llvm/IR/GlobalValue.h"
22#include "llvm/Support/Host.h"
23#include "llvm/Support/TargetRegistry.h"
24#include "llvm/Target/TargetMachine.h"
25#include <cstdlib>
26
27#define GET_SUBTARGETINFO_TARGET_DESC
28#define GET_SUBTARGETINFO_CTOR
29#include "PPCGenSubtargetInfo.inc"
30
31using namespace llvm;
32
33PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
34                           const std::string &FS, bool is64Bit,
35                           CodeGenOpt::Level OptLevel)
36  : PPCGenSubtargetInfo(TT, CPU, FS)
37  , IsPPC64(is64Bit)
38  , TargetTriple(TT) {
39  initializeEnvironment();
40
41  std::string FullFS = FS;
42
43  // At -O2 and above, track CR bits as individual registers.
44  if (OptLevel >= CodeGenOpt::Default) {
45    if (!FullFS.empty())
46      FullFS = "+crbits," + FullFS;
47    else
48      FullFS = "+crbits";
49  }
50
51  resetSubtargetFeatures(CPU, FullFS);
52}
53
54/// SetJITMode - This is called to inform the subtarget info that we are
55/// producing code for the JIT.
56void PPCSubtarget::SetJITMode() {
57  // JIT mode doesn't want lazy resolver stubs, it knows exactly where
58  // everything is.  This matters for PPC64, which codegens in PIC mode without
59  // stubs.
60  HasLazyResolverStubs = false;
61
62  // Calls to external functions need to use indirect calls
63  IsJITCodeModel = true;
64}
65
66void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
67  AttributeSet FnAttrs = MF->getFunction()->getAttributes();
68  Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
69                                           "target-cpu");
70  Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
71                                          "target-features");
72  std::string CPU =
73    !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
74  std::string FS =
75    !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
76  if (!FS.empty()) {
77    initializeEnvironment();
78    resetSubtargetFeatures(CPU, FS);
79  }
80}
81
82void PPCSubtarget::initializeEnvironment() {
83  StackAlignment = 16;
84  DarwinDirective = PPC::DIR_NONE;
85  HasMFOCRF = false;
86  Has64BitSupport = false;
87  Use64BitRegs = false;
88  UseCRBits = false;
89  HasAltivec = false;
90  HasQPX = false;
91  HasVSX = false;
92  HasFCPSGN = false;
93  HasFSQRT = false;
94  HasFRE = false;
95  HasFRES = false;
96  HasFRSQRTE = false;
97  HasFRSQRTES = false;
98  HasRecipPrec = false;
99  HasSTFIWX = false;
100  HasLFIWAX = false;
101  HasFPRND = false;
102  HasFPCVT = false;
103  HasISEL = false;
104  HasPOPCNTD = false;
105  HasLDBRX = false;
106  IsBookE = false;
107  DeprecatedMFTB = false;
108  DeprecatedDST = false;
109  HasLazyResolverStubs = false;
110  IsJITCodeModel = false;
111}
112
113void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
114  // Determine default and user specified characteristics
115  std::string CPUName = CPU;
116  if (CPUName.empty())
117    CPUName = "generic";
118#if (defined(__APPLE__) || defined(__linux__)) && \
119    (defined(__ppc__) || defined(__powerpc__))
120  if (CPUName == "generic")
121    CPUName = sys::getHostCPUName();
122#endif
123
124  // Initialize scheduling itinerary for the specified CPU.
125  InstrItins = getInstrItineraryForCPU(CPUName);
126
127  // Make sure 64-bit features are available when CPUname is generic
128  std::string FullFS = FS;
129
130  // If we are generating code for ppc64, verify that options make sense.
131  if (IsPPC64) {
132    Has64BitSupport = true;
133    // Silently force 64-bit register use on ppc64.
134    Use64BitRegs = true;
135    if (!FullFS.empty())
136      FullFS = "+64bit," + FullFS;
137    else
138      FullFS = "+64bit";
139  }
140
141  // Parse features string.
142  ParseSubtargetFeatures(CPUName, FullFS);
143
144  // If the user requested use of 64-bit regs, but the cpu selected doesn't
145  // support it, ignore.
146  if (use64BitRegs() && !has64BitSupport())
147    Use64BitRegs = false;
148
149  // Set up darwin-specific properties.
150  if (isDarwin())
151    HasLazyResolverStubs = true;
152
153  // QPX requires a 32-byte aligned stack. Note that we need to do this if
154  // we're compiling for a BG/Q system regardless of whether or not QPX
155  // is enabled because external functions will assume this alignment.
156  if (hasQPX() || isBGQ())
157    StackAlignment = 32;
158
159  // Determine endianness.
160  IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
161}
162
163/// hasLazyResolverStub - Return true if accesses to the specified global have
164/// to go through a dyld lazy resolution stub.  This means that an extra load
165/// is required to get the address of the global.
166bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
167                                       const TargetMachine &TM) const {
168  // We never have stubs if HasLazyResolverStubs=false or if in static mode.
169  if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
170    return false;
171  // If symbol visibility is hidden, the extra load is not needed if
172  // the symbol is definitely defined in the current translation unit.
173  bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
174  if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
175    return false;
176  return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
177         GV->hasCommonLinkage() || isDecl;
178}
179
180bool PPCSubtarget::enablePostRAScheduler(
181           CodeGenOpt::Level OptLevel,
182           TargetSubtargetInfo::AntiDepBreakMode& Mode,
183           RegClassVector& CriticalPathRCs) const {
184  Mode = TargetSubtargetInfo::ANTIDEP_ALL;
185
186  CriticalPathRCs.clear();
187
188  if (isPPC64())
189    CriticalPathRCs.push_back(&PPC::G8RCRegClass);
190  else
191    CriticalPathRCs.push_back(&PPC::GPRCRegClass);
192
193  return OptLevel >= CodeGenOpt::Default;
194}
195
196// Embedded cores need aggressive scheduling (and some others also benefit).
197static bool needsAggressiveScheduling(unsigned Directive) {
198  switch (Directive) {
199  default: return false;
200  case PPC::DIR_440:
201  case PPC::DIR_A2:
202  case PPC::DIR_E500mc:
203  case PPC::DIR_E5500:
204  case PPC::DIR_PWR7:
205    return true;
206  }
207}
208
209bool PPCSubtarget::enableMachineScheduler() const {
210  // Enable MI scheduling for the embedded cores.
211  // FIXME: Enable this for all cores (some additional modeling
212  // may be necessary).
213  return needsAggressiveScheduling(DarwinDirective);
214}
215
216void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
217                                       MachineInstr *begin,
218                                       MachineInstr *end,
219                                       unsigned NumRegionInstrs) const {
220  if (needsAggressiveScheduling(DarwinDirective)) {
221    Policy.OnlyTopDown = false;
222    Policy.OnlyBottomUp = false;
223  }
224
225  // Spilling is generally expensive on all PPC cores, so always enable
226  // register-pressure tracking.
227  Policy.ShouldTrackPressure = true;
228}
229
230bool PPCSubtarget::useAA() const {
231  // Use AA during code generation for the embedded cores.
232  return needsAggressiveScheduling(DarwinDirective);
233}
234
235